Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[1]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[2]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[3]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[4]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[5]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[6]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[7]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[8]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[9]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[10]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[11]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[12]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[13]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[14]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[15]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[16]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[17]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[18]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[19]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[20]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[21]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[22]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[23]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[24]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[25]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[26]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[27]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[28]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[29]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[30]	5122371	1			T20	110640		T21	204947		T22	74
all_pins[31]	5122371	1			T20	110640		T21	204947		T22	74

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	101817986	1			T20	220317		T21	407172		T22	1963
values[0x1]	62097886	1			T20	133730		T21	248658		T22	405
transitions[0x0=>0x1]	37216098	1			T20	805438		T21	149012		T22	288
transitions[0x1=>0x0]	37215951	1			T20	805438		T21	149012		T22	288

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3184220	1			T20	68152		T21	126886		T22	63
all_pins[0]	values[0x1]	1938151	1			T20	42488		T21	78061		T22	11
all_pins[0]	transitions[0x0=>0x1]	1202408	1			T20	26399		T21	48671		T22	11
all_pins[0]	transitions[0x1=>0x0]	1204882	1			T20	25142		T21	47808		T22	8
all_pins[1]	values[0x0]	3188328	1			T20	68690		T21	126120		T22	55
all_pins[1]	values[0x1]	1934043	1			T20	41950		T21	78827		T22	19
all_pins[1]	transitions[0x0=>0x1]	1157623	1			T20	25123		T21	47393		T22	16
all_pins[1]	transitions[0x1=>0x0]	1161731	1			T20	25661		T21	46627		T22	8
all_pins[2]	values[0x0]	3181860	1			T20	68855		T21	128318		T22	55
all_pins[2]	values[0x1]	1940511	1			T20	41785		T21	76629		T22	19
all_pins[2]	transitions[0x0=>0x1]	1162619	1			T20	25064		T21	44981		T22	12
all_pins[2]	transitions[0x1=>0x0]	1156151	1			T20	25229		T21	47179		T22	12
all_pins[3]	values[0x0]	3178269	1			T20	68482		T21	127141		T22	61
all_pins[3]	values[0x1]	1944102	1			T20	42158		T21	77806		T22	13
all_pins[3]	transitions[0x0=>0x1]	1163319	1			T20	25264		T21	46938		T22	5
all_pins[3]	transitions[0x1=>0x0]	1159728	1			T20	24891		T21	45761		T22	11
all_pins[4]	values[0x0]	3184032	1			T20	69950		T21	126344		T22	58
all_pins[4]	values[0x1]	1938339	1			T20	40690		T21	78603		T22	16
all_pins[4]	transitions[0x0=>0x1]	1157795	1			T20	24205		T21	46827		T22	13
all_pins[4]	transitions[0x1=>0x0]	1163558	1			T20	25673		T21	46030		T22	10
all_pins[5]	values[0x0]	3175933	1			T20	69059		T21	127494		T22	61
all_pins[5]	values[0x1]	1946438	1			T20	41581		T21	77453		T22	13
all_pins[5]	transitions[0x0=>0x1]	1166815	1			T20	25607		T21	45596		T22	9
all_pins[5]	transitions[0x1=>0x0]	1158716	1			T20	24716		T21	46746		T22	12
all_pins[6]	values[0x0]	3179246	1			T20	67815		T21	125682		T22	64
all_pins[6]	values[0x1]	1943125	1			T20	42825		T21	79265		T22	10
all_pins[6]	transitions[0x0=>0x1]	1160459	1			T20	25547		T21	47663		T22	6
all_pins[6]	transitions[0x1=>0x0]	1163772	1			T20	24303		T21	45851		T22	9
all_pins[7]	values[0x0]	3179739	1			T20	68453		T21	127746		T22	55
all_pins[7]	values[0x1]	1942632	1			T20	42187		T21	77201		T22	19
all_pins[7]	transitions[0x0=>0x1]	1164258	1			T20	24669		T21	46102		T22	13
all_pins[7]	transitions[0x1=>0x0]	1164751	1			T20	25307		T21	48166		T22	4
all_pins[8]	values[0x0]	3191842	1			T20	69190		T21	126668		T22	52
all_pins[8]	values[0x1]	1930529	1			T20	41450		T21	78279		T22	22
all_pins[8]	transitions[0x0=>0x1]	1155904	1			T20	24889		T21	47681		T22	15
all_pins[8]	transitions[0x1=>0x0]	1168007	1			T20	25626		T21	46603		T22	12
all_pins[9]	values[0x0]	3178030	1			T20	69872		T21	127621		T22	59
all_pins[9]	values[0x1]	1944341	1			T20	40768		T21	77326		T22	15
all_pins[9]	transitions[0x0=>0x1]	1169829	1			T20	24586		T21	46292		T22	9
all_pins[9]	transitions[0x1=>0x0]	1156017	1			T20	25268		T21	47245		T22	16
all_pins[10]	values[0x0]	3182632	1			T20	68699		T21	126076		T22	64
all_pins[10]	values[0x1]	1939739	1			T20	41941		T21	78871		T22	10
all_pins[10]	transitions[0x0=>0x1]	1157894	1			T20	25596		T21	47877		T22	7
all_pins[10]	transitions[0x1=>0x0]	1162496	1			T20	24423		T21	46332		T22	12
all_pins[11]	values[0x0]	3182731	1			T20	67834		T21	128064		T22	63
all_pins[11]	values[0x1]	1939640	1			T20	42806		T21	76883		T22	11
all_pins[11]	transitions[0x0=>0x1]	1159933	1			T20	25471		T21	46382		T22	6
all_pins[11]	transitions[0x1=>0x0]	1160032	1			T20	24606		T21	48370		T22	5
all_pins[12]	values[0x0]	3179570	1			T20	68983		T21	127354		T22	64
all_pins[12]	values[0x1]	1942801	1			T20	41657		T21	77593		T22	10
all_pins[12]	transitions[0x0=>0x1]	1162013	1			T20	24780		T21	46642		T22	10
all_pins[12]	transitions[0x1=>0x0]	1158852	1			T20	25929		T21	45932		T22	11
all_pins[13]	values[0x0]	3181523	1			T20	68435		T21	127454		T22	65
all_pins[13]	values[0x1]	1940848	1			T20	42205		T21	77493		T22	9
all_pins[13]	transitions[0x0=>0x1]	1159283	1			T20	25413		T21	46460		T22	6
all_pins[13]	transitions[0x1=>0x0]	1161236	1			T20	24865		T21	46560		T22	7
all_pins[14]	values[0x0]	3176596	1			T20	69325		T21	126090		T22	57
all_pins[14]	values[0x1]	1945775	1			T20	41315		T21	78857		T22	17
all_pins[14]	transitions[0x0=>0x1]	1164079	1			T20	24482		T21	47016		T22	17
all_pins[14]	transitions[0x1=>0x0]	1159152	1			T20	25372		T21	45652		T22	9
all_pins[15]	values[0x0]	3176388	1			T20	68378		T21	127379		T22	70
all_pins[15]	values[0x1]	1945983	1			T20	42262		T21	77568		T22	4
all_pins[15]	transitions[0x0=>0x1]	1161776	1			T20	25848		T21	45850		T22	4
all_pins[15]	transitions[0x1=>0x0]	1161568	1			T20	24901		T21	47139		T22	17
all_pins[16]	values[0x0]	3184643	1			T20	69121		T21	127335		T22	63
all_pins[16]	values[0x1]	1937728	1			T20	41519		T21	77612		T22	11
all_pins[16]	transitions[0x0=>0x1]	1157943	1			T20	24790		T21	46410		T22	9
all_pins[16]	transitions[0x1=>0x0]	1166198	1			T20	25533		T21	46366		T22	2
all_pins[17]	values[0x0]	3184579	1			T20	68999		T21	128267		T22	53
all_pins[17]	values[0x1]	1937792	1			T20	41641		T21	76680		T22	21
all_pins[17]	transitions[0x0=>0x1]	1160560	1			T20	25495		T21	45958		T22	12
all_pins[17]	transitions[0x1=>0x0]	1160496	1			T20	25373		T21	46890		T22	2
all_pins[18]	values[0x0]	3182653	1			T20	68744		T21	126465		T22	59
all_pins[18]	values[0x1]	1939718	1			T20	41896		T21	78482		T22	15
all_pins[18]	transitions[0x0=>0x1]	1162828	1			T20	24670		T21	46772		T22	12
all_pins[18]	transitions[0x1=>0x0]	1160902	1			T20	24415		T21	44970		T22	18
all_pins[19]	values[0x0]	3176969	1			T20	69943		T21	127572		T22	54
all_pins[19]	values[0x1]	1945402	1			T20	40697		T21	77375		T22	20
all_pins[19]	transitions[0x0=>0x1]	1164346	1			T20	24786		T21	45758		T22	12
all_pins[19]	transitions[0x1=>0x0]	1158662	1			T20	25985		T21	46865		T22	7
all_pins[20]	values[0x0]	3187501	1			T20	68732		T21	126298		T22	63
all_pins[20]	values[0x1]	1934870	1			T20	41908		T21	78649		T22	11
all_pins[20]	transitions[0x0=>0x1]	1159299	1			T20	25282		T21	47235		T22	4
all_pins[20]	transitions[0x1=>0x0]	1169831	1			T20	24071		T21	45961		T22	13
all_pins[21]	values[0x0]	3175944	1			T20	68317		T21	128398		T22	57
all_pins[21]	values[0x1]	1946427	1			T20	42323		T21	76549		T22	17
all_pins[21]	transitions[0x0=>0x1]	1171674	1			T20	25484		T21	45335		T22	13
all_pins[21]	transitions[0x1=>0x0]	1160117	1			T20	25069		T21	47435		T22	7
all_pins[22]	values[0x0]	3182964	1			T20	68695		T21	127181		T22	64
all_pins[22]	values[0x1]	1939407	1			T20	41945		T21	77766		T22	10
all_pins[22]	transitions[0x0=>0x1]	1158133	1			T20	25316		T21	46849		T22	5
all_pins[22]	transitions[0x1=>0x0]	1165153	1			T20	25694		T21	45632		T22	12
all_pins[23]	values[0x0]	3180532	1			T20	68956		T21	127308		T22	66
all_pins[23]	values[0x1]	1941839	1			T20	41684		T21	77639		T22	8
all_pins[23]	transitions[0x0=>0x1]	1164097	1			T20	25221		T21	46319		T22	6
all_pins[23]	transitions[0x1=>0x0]	1161665	1			T20	25482		T21	46446		T22	8
all_pins[24]	values[0x0]	3182940	1			T20	68714		T21	127439		T22	69
all_pins[24]	values[0x1]	1939431	1			T20	41926		T21	77508		T22	5
all_pins[24]	transitions[0x0=>0x1]	1161105	1			T20	25315		T21	46356		T22	3
all_pins[24]	transitions[0x1=>0x0]	1163513	1			T20	25073		T21	46487		T22	6
all_pins[25]	values[0x0]	3184865	1			T20	68790		T21	127260		T22	69
all_pins[25]	values[0x1]	1937506	1			T20	41850		T21	77687		T22	5
all_pins[25]	transitions[0x0=>0x1]	1158828	1			T20	25387		T21	46471		T22	3
all_pins[25]	transitions[0x1=>0x0]	1160753	1			T20	25463		T21	46292		T22	3
all_pins[26]	values[0x0]	3182434	1			T20	68235		T21	127867		T22	55
all_pins[26]	values[0x1]	1939937	1			T20	42405		T21	77080		T22	19
all_pins[26]	transitions[0x0=>0x1]	1163993	1			T20	25642		T21	46356		T22	19
all_pins[26]	transitions[0x1=>0x0]	1161562	1			T20	25087		T21	46963		T22	5
all_pins[27]	values[0x0]	3188852	1			T20	69710		T21	127961		T22	63
all_pins[27]	values[0x1]	1933519	1			T20	40930		T21	76986		T22	11
all_pins[27]	transitions[0x0=>0x1]	1158258	1			T20	24424		T21	46402		T22	6
all_pins[27]	transitions[0x1=>0x0]	1164676	1			T20	25899		T21	46496		T22	14
all_pins[28]	values[0x0]	3181579	1			T20	68562		T21	127658		T22	61
all_pins[28]	values[0x1]	1940792	1			T20	42078		T21	77289		T22	13
all_pins[28]	transitions[0x0=>0x1]	1162928	1			T20	25672		T21	45889		T22	11
all_pins[28]	transitions[0x1=>0x0]	1155655	1			T20	24524		T21	45586		T22	9
all_pins[29]	values[0x0]	3181138	1			T20	68974		T21	126742		T22	69
all_pins[29]	values[0x1]	1941233	1			T20	41666		T21	78205		T22	5
all_pins[29]	transitions[0x0=>0x1]	1162677	1			T20	25168		T21	46930		T22	5
all_pins[29]	transitions[0x1=>0x0]	1162236	1			T20	25580		T21	46014		T22	13
all_pins[30]	values[0x0]	3177855	1			T20	69101		T21	127786		T22	66
all_pins[30]	values[0x1]	1944516	1			T20	41539		T21	77161		T22	8
all_pins[30]	transitions[0x0=>0x1]	1163509	1			T20	25263		T21	46314		T22	4
all_pins[30]	transitions[0x1=>0x0]	1160226	1			T20	25390		T21	47358		T22	1
all_pins[31]	values[0x0]	3181599	1			T20	69409		T21	127749		T22	66
all_pins[31]	values[0x1]	1940772	1			T20	41231		T21	77198		T22	8
all_pins[31]	transitions[0x0=>0x1]	1159913	1			T20	24580		T21	46398		T22	5
all_pins[31]	transitions[0x1=>0x0]	1163657	1			T20	24888		T21	46361		T22	5