Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[1]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[2]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[3]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[4]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[5]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[6]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[7]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[8]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[9]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[10]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[11]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[12]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[13]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[14]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[15]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[16]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[17]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[18]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[19]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[20]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[21]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[22]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[23]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[24]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[25]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[26]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[27]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[28]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[29]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[30]	16666584	1			T20	316255		T21	580736		T22	225
bins_for_gpio_bits[31]	16666584	1			T20	316255		T21	580736		T22	225

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324393815

1

T20

674400

T21

120774

T22

3488

auto[1]

208936873

1

T20

337615

T21

650607

T22

3712

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

426053550

1

T20

770033

T21

146749

T22

6636

auto[1]

107277138

1

T20

241982

T21

390859

T22

564

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

394629031

1

T20

702268

T21

134757

T22

5575

auto[1]

138701657

1

T20

309747

T21

510781

T22

1625

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6228379	1			T20	115601		T21	224022		T22	88
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4416310	1			T20	63725		T21	135705		T22	73
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1687861	1			T20	38062		T21	61400		T22	12
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2215110	1			T20	56921		T21	92143		T22	11
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	447086	1			T20	4036		T21	6759		T22	17
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1671838	1			T20	37910		T21	60707		T22	24
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6218974	1			T20	117246		T21	224106		T22	42
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4420662	1			T20	64243		T21	135574		T22	101
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1681566	1			T20	37550		T21	60841		T22	14
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2219303	1			T20	55502		T21	92658		T22	22
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	448899	1			T20	3640		T21	6905		T22	27
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1677180	1			T20	38074		T21	60652		T22	19
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6224558	1			T20	116885		T21	223768		T22	78
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4418600	1			T20	63991		T21	136313		T22	92
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1682718	1			T20	38101		T21	61463		T22	5
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2214387	1			T20	55304		T21	92208		T22	24
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	447753	1			T20	3814		T21	6722		T22	11
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1678568	1			T20	38160		T21	60262		T22	15
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6231376	1			T20	117951		T21	223432		T22	63
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4406853	1			T20	63955		T21	136340		T22	91
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1689302	1			T20	38372		T21	61272		T23	6691
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2214174	1			T20	54976		T21	92521		T22	32
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	446269	1			T20	3812		T21	6657		T22	20
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1678610	1			T20	37189		T21	60514		T22	19
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6244806	1			T20	118273		T21	223688		T22	72
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4406136	1			T20	64128		T21	135942		T22	87
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1690095	1			T20	38626		T21	62295		T22	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2205589	1			T20	54133		T21	91458		T22	17
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	445220	1			T20	3769		T21	6667		T22	27
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1674738	1			T20	37326		T21	60686		T22	12
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6236089	1			T20	117418		T21	225584		T22	72
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4414847	1			T20	64100		T21	135722		T22	99
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1684895	1			T20	37998		T21	62656		T22	5
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2210093	1			T20	55161		T21	90351		T22	22
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	443606	1			T20	3699		T21	6307		T22	13
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1677054	1			T20	37879		T21	60116		T22	14
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6230947	1			T20	116764		T21	223234		T22	117
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4416010	1			T20	64001		T21	135701		T22	57
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1683139	1			T20	38114		T21	60786		T22	18
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2216235	1			T20	55874		T21	93564		T22	25
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	446400	1			T20	3866		T21	6823		T22	2
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1673853	1			T20	37636		T21	60628		T22	6
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6231984	1			T20	116393		T21	224029		T22	72
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4408612	1			T20	63941		T21	136163		T22	66
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1684030	1			T20	37874		T21	61628		T22	8
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2220526	1			T20	56173		T21	91794		T22	41
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	447621	1			T20	3824		T21	6740		T22	20
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1673811	1			T20	38050		T21	60382		T22	18
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6219270	1			T20	117732		T21	225412		T22	72
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4425882	1			T20	63965		T21	135703		T22	85
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1689059	1			T20	38117		T21	61415		T23	6355
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2213119	1			T20	55070		T21	91258		T22	51
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	445649	1			T20	3862		T21	6485		T22	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1673605	1			T20	37509		T21	60463		T22	3
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6234857	1			T20	118310		T21	223191		T22	93
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4411394	1			T20	64092		T21	135772		T22	70
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1685908	1			T20	38444		T21	61508		T22	11
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2211732	1			T20	55068		T21	91846		T22	8
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	444466	1			T20	3668		T21	6654		T22	22
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1678227	1			T20	36673		T21	61765		T22	21
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6240988	1			T20	117606		T21	223544		T22	81
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4405064	1			T20	64055		T21	135808		T22	89
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1683975	1			T20	37878		T21	61478		T22	5
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2216254	1			T20	55697		T21	92394		T22	26
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	448043	1			T20	3684		T21	6612		T22	22
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1672260	1			T20	37335		T21	60900		T22	2
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6234693	1			T20	116569		T21	222567		T22	84
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4417810	1			T20	64596		T21	136067		T22	90
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1682475	1			T20	38029		T21	62592		T22	8
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2215469	1			T20	54933		T21	91350		T22	19
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	446822	1			T20	3641		T21	6829		T22	13
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1669315	1			T20	38487		T21	61331		T22	11
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6238490	1			T20	117834		T21	224898		T22	76
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4414379	1			T20	64565		T21	136254		T22	77
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1683218	1			T20	38543		T21	61438		T22	6
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2214484	1			T20	54253		T21	91088		T22	26
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	445644	1			T20	3515		T21	6441		T22	27
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1670369	1			T20	37545		T21	60617		T22	13
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6238210	1			T20	116682		T21	223330		T22	60
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4406244	1			T20	63638		T21	135747		T22	111
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1684560	1			T20	38322		T21	61316		T22	11
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2223205	1			T20	55824		T21	92619		T22	29
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	445523	1			T20	3903		T21	6558		T22	5
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1668842	1			T20	37886		T21	61166		T22	9
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6232266	1			T20	116900		T21	223959		T22	72
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4411771	1			T20	64273		T21	135476		T22	90
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1683774	1			T20	38417		T21	60957		T22	10
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2218205	1			T20	54509		T21	92261		T22	26
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	446162	1			T20	3688		T21	6991		T22	10
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1674406	1			T20	38468		T21	61092		T22	17
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6231909	1			T20	116815		T21	222817		T22	95
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4412146	1			T20	64157		T21	135759		T22	87
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1683163	1			T20	38183		T21	62254		T23	6379
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2217402	1			T20	55125		T21	91899		T22	17
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	446804	1			T20	3706		T21	6762		T22	11
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1675160	1			T20	38269		T21	61245		T22	15
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6236365	1			T20	117191		T21	222984		T22	94
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4422161	1			T20	64123		T21	135917		T22	86
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1683092	1			T20	36920		T21	61212		T22	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2219345	1			T20	56454		T21	92343		T22	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	442505	1			T20	3911		T21	6899		T22	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1663116	1			T20	37656		T21	61381		T22	19
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6250393	1			T20	117766		T21	223233		T22	97
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4402007	1			T20	64181		T21	135550		T22	90
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1681451	1			T20	37868		T21	61742		T22	5
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2222038	1			T20	55504		T21	92748		T22	15
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	446680	1			T20	3800		T21	6937		T22	10
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1664015	1			T20	37136		T21	60526		T22	8
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6252814	1			T20	117683		T21	221674		T22	111
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4398094	1			T20	63931		T21	135140		T22	50
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1680231	1			T20	37427		T21	61190		T22	14
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2219891	1			T20	55994		T21	94093		T22	39
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	448095	1			T20	3664		T21	6955		T22	9
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1667459	1			T20	37556		T21	61684		T22	2
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6245727	1			T20	116750		T21	224473		T22	47
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4408965	1			T20	64271		T21	135655		T22	135
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1674487	1			T20	37448		T21	62166		T22	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2221761	1			T20	56132		T21	91392		T22	9
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	448339	1			T20	3856		T21	6835		T22	25
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1667305	1			T20	37798		T21	60215		T22	6
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6253342	1			T20	118466		T21	225969		T22	65
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4404043	1			T20	64310		T21	135731		T22	77
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1680358	1			T20	37315		T21	62672		T22	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2222421	1			T20	55197		T21	90638		T22	45
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	446499	1			T20	3647		T21	6707		T22	23
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1659921	1			T20	37320		T21	59019		T22	10
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6240799	1			T20	117999		T21	224685		T22	116
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4419289	1			T20	64337		T21	135683		T22	69
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1679906	1			T20	38285		T21	60874		T22	7
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2217408	1			T20	55136		T21	91945		T22	28
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	445351	1			T20	3753		T21	6819		T22	4
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1663831	1			T20	36745		T21	60730		T22	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6235347	1			T20	117016		T21	224769		T22	69
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4416879	1			T20	64096		T21	136384		T22	125
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1679771	1			T20	37909		T21	60293		T22	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2220929	1			T20	55541		T21	92248		T22	28
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	447705	1			T20	3795		T21	6820		T22	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1665953	1			T20	37898		T21	60222		T23	6093
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6244637	1			T20	118064		T21	224762		T22	106
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4407740	1			T20	64059		T21	135900		T22	67
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1675659	1			T20	37914		T21	62320		T22	5
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2223672	1			T20	55861		T21	91922		T22	33
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	448240	1			T20	3564		T21	6565		T22	12
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1666636	1			T20	36793		T21	59267		T22	2
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6236865	1			T20	117001		T21	223107		T22	64
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4418875	1			T20	64327		T21	135993		T22	102
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1684060	1			T20	37534		T21	62099		T22	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2215552	1			T20	55688		T21	92104		T22	15
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	447186	1			T20	3598		T21	6856		T22	39
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1664046	1			T20	38107		T21	60577		T22	4
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6241172	1			T20	116781		T21	224122		T22	62
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4412919	1			T20	64302		T21	135761		T22	122
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1679366	1			T20	37413		T21	60811		T22	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2224369	1			T20	56149		T21	92097		T22	5
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	446317	1			T20	3778		T21	6922		T22	18
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1662441	1			T20	37832		T21	61023		T22	5
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6249873	1			T20	117258		T21	224492		T22	72
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4413328	1			T20	63978		T21	135791		T22	84
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1679611	1			T20	37914		T21	61061		T22	21
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2220101	1			T20	55780		T21	92442		T22	20
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	443667	1			T20	3793		T21	6898		T22	17
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1660004	1			T20	37532		T21	60052		T22	11
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6235395	1			T20	118494		T21	224005		T22	107
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4414794	1			T20	64049		T21	136173		T22	63
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1679181	1			T20	38011		T21	60705		T22	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2221982	1			T20	55197		T21	91991		T22	26
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	446197	1			T20	3670		T21	6845		T22	15
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1669035	1			T20	36834		T21	61017		T22	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6232160	1			T20	117834		T21	223633		T22	53
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4423625	1			T20	63915		T21	135821		T22	116
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1677597	1			T20	38550		T21	61166		T23	6345
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2219238	1			T20	54162		T21	92557		T22	10
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	443868	1			T20	3762		T21	6661		T22	33
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1670096	1			T20	38032		T21	60898		T22	13
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6246949	1			T20	117667		T21	222177		T22	49
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4402072	1			T20	64285		T21	135659		T22	113
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1680753	1			T20	38391		T21	60523		T22	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2220847	1			T20	54696		T21	93403		T22	29
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	445197	1			T20	3742		T21	6762		T22	27
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1670766	1			T20	37474		T21	62212		T22	5
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6224604	1			T20	116513		T21	223683		T22	76
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4421829	1			T20	63971		T21	135982		T22	56
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1684474	1			T20	37804		T21	60850		T22	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2222688	1			T20	55961		T21	92583		T22	47
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	446156	1			T20	3808		T21	6773		T22	15
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1666833	1			T20	38198		T21	60865		T22	23
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6234805	1			T20	118775		T21	223519		T22	64
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4415519	1			T20	63838		T21	136067		T22	134
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1675394	1			T20	37721		T21	60632		T22	4
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2222114	1			T20	54743		T21	93072		T22	15
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	446036	1			T20	3713		T21	6677		T22	5
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1672716	1			T20	37465		T21	60769		T22	3

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal