Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9670371 |
1 |
|
|
T20 |
160461 |
|
T21 |
302559 |
|
T22 |
106 |
| auto[1] |
7248411 |
1 |
|
|
T20 |
160570 |
|
T21 |
290464 |
|
T22 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15987066 |
1 |
|
|
T20 |
302375 |
|
T21 |
553205 |
|
T22 |
132 |
| auto[1] |
931716 |
1 |
|
|
T20 |
18656 |
|
T21 |
39818 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9621247 |
1 |
|
|
T20 |
167444 |
|
T21 |
299015 |
|
T22 |
110 |
| auto[1] |
7297535 |
1 |
|
|
T20 |
153587 |
|
T21 |
294008 |
|
T22 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3199359 |
1 |
|
|
T20 |
66908 |
|
T21 |
130873 |
|
T22 |
19 |
| auto[1] |
auto[0] |
auto[1] |
469158 |
1 |
|
|
T20 |
9213 |
|
T21 |
20659 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3166460 |
1 |
|
|
T20 |
68023 |
|
T21 |
123317 |
|
T22 |
3 |
| auto[1] |
auto[1] |
auto[1] |
462558 |
1 |
|
|
T20 |
9443 |
|
T21 |
19159 |
|
T23 |
1487 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9667066 |
1 |
|
|
T20 |
161244 |
|
T21 |
294214 |
|
T22 |
85 |
| auto[1] |
7251716 |
1 |
|
|
T20 |
159787 |
|
T21 |
298809 |
|
T22 |
49 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15991818 |
1 |
|
|
T20 |
302193 |
|
T21 |
553696 |
|
T22 |
134 |
| auto[1] |
926964 |
1 |
|
|
T20 |
18838 |
|
T21 |
39327 |
|
T23 |
2860 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9652284 |
1 |
|
|
T20 |
165579 |
|
T21 |
301263 |
|
T22 |
118 |
| auto[1] |
7266498 |
1 |
|
|
T20 |
155452 |
|
T21 |
291760 |
|
T22 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3186356 |
1 |
|
|
T20 |
66469 |
|
T21 |
124645 |
|
T22 |
2 |
| auto[1] |
auto[0] |
auto[1] |
466801 |
1 |
|
|
T20 |
9052 |
|
T21 |
19366 |
|
T23 |
1459 |
| auto[1] |
auto[1] |
auto[0] |
3153178 |
1 |
|
|
T20 |
70145 |
|
T21 |
127788 |
|
T22 |
14 |
| auto[1] |
auto[1] |
auto[1] |
460163 |
1 |
|
|
T20 |
9786 |
|
T21 |
19961 |
|
T23 |
1401 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9637362 |
1 |
|
|
T20 |
159087 |
|
T21 |
291176 |
|
T22 |
110 |
| auto[1] |
7281420 |
1 |
|
|
T20 |
161944 |
|
T21 |
301847 |
|
T22 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15989966 |
1 |
|
|
T20 |
301329 |
|
T21 |
553769 |
|
T22 |
131 |
| auto[1] |
928816 |
1 |
|
|
T20 |
19702 |
|
T21 |
39254 |
|
T22 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9650240 |
1 |
|
|
T20 |
160749 |
|
T21 |
302185 |
|
T22 |
84 |
| auto[1] |
7268542 |
1 |
|
|
T20 |
160282 |
|
T21 |
290838 |
|
T22 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3168571 |
1 |
|
|
T20 |
70590 |
|
T21 |
123487 |
|
T22 |
42 |
| auto[1] |
auto[0] |
auto[1] |
463198 |
1 |
|
|
T20 |
9853 |
|
T21 |
19077 |
|
T22 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3171155 |
1 |
|
|
T20 |
69990 |
|
T21 |
128097 |
|
T22 |
5 |
| auto[1] |
auto[1] |
auto[1] |
465618 |
1 |
|
|
T20 |
9849 |
|
T21 |
20177 |
|
T23 |
1354 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9622984 |
1 |
|
|
T20 |
160317 |
|
T21 |
302198 |
|
T22 |
111 |
| auto[1] |
7295798 |
1 |
|
|
T20 |
160714 |
|
T21 |
290825 |
|
T22 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15992098 |
1 |
|
|
T20 |
302286 |
|
T21 |
551493 |
|
T22 |
133 |
| auto[1] |
926684 |
1 |
|
|
T20 |
18745 |
|
T21 |
41530 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9654364 |
1 |
|
|
T20 |
165636 |
|
T21 |
286048 |
|
T22 |
98 |
| auto[1] |
7264418 |
1 |
|
|
T20 |
155395 |
|
T21 |
306975 |
|
T22 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3164558 |
1 |
|
|
T20 |
69289 |
|
T21 |
134645 |
|
T22 |
30 |
| auto[1] |
auto[0] |
auto[1] |
462255 |
1 |
|
|
T20 |
9591 |
|
T21 |
20765 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3173176 |
1 |
|
|
T20 |
67361 |
|
T21 |
130800 |
|
T22 |
5 |
| auto[1] |
auto[1] |
auto[1] |
464429 |
1 |
|
|
T20 |
9154 |
|
T21 |
20765 |
|
T23 |
1368 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9615045 |
1 |
|
|
T20 |
159683 |
|
T21 |
293633 |
|
T22 |
95 |
| auto[1] |
7303737 |
1 |
|
|
T20 |
161348 |
|
T21 |
299390 |
|
T22 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15992874 |
1 |
|
|
T20 |
300835 |
|
T21 |
553546 |
|
T22 |
133 |
| auto[1] |
925908 |
1 |
|
|
T20 |
20196 |
|
T21 |
39477 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9660240 |
1 |
|
|
T20 |
157335 |
|
T21 |
300217 |
|
T22 |
98 |
| auto[1] |
7258542 |
1 |
|
|
T20 |
163696 |
|
T21 |
292806 |
|
T22 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3149933 |
1 |
|
|
T20 |
69840 |
|
T21 |
125385 |
|
T22 |
23 |
| auto[1] |
auto[0] |
auto[1] |
461067 |
1 |
|
|
T20 |
9786 |
|
T21 |
19478 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3182701 |
1 |
|
|
T20 |
73660 |
|
T21 |
127944 |
|
T22 |
12 |
| auto[1] |
auto[1] |
auto[1] |
464841 |
1 |
|
|
T20 |
10410 |
|
T21 |
19999 |
|
T23 |
1287 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9645475 |
1 |
|
|
T20 |
164385 |
|
T21 |
296909 |
|
T22 |
100 |
| auto[1] |
7273307 |
1 |
|
|
T20 |
156646 |
|
T21 |
296114 |
|
T22 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15993384 |
1 |
|
|
T20 |
301547 |
|
T21 |
552298 |
|
T22 |
133 |
| auto[1] |
925398 |
1 |
|
|
T20 |
19484 |
|
T21 |
40725 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9652041 |
1 |
|
|
T20 |
159510 |
|
T21 |
291947 |
|
T22 |
108 |
| auto[1] |
7266741 |
1 |
|
|
T20 |
161521 |
|
T21 |
301076 |
|
T22 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3162488 |
1 |
|
|
T20 |
73279 |
|
T21 |
130111 |
|
T22 |
18 |
| auto[1] |
auto[0] |
auto[1] |
461107 |
1 |
|
|
T20 |
10168 |
|
T21 |
20289 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3178855 |
1 |
|
|
T20 |
68758 |
|
T21 |
130240 |
|
T22 |
7 |
| auto[1] |
auto[1] |
auto[1] |
464291 |
1 |
|
|
T20 |
9316 |
|
T21 |
20436 |
|
T23 |
1207 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9664034 |
1 |
|
|
T20 |
160844 |
|
T21 |
295798 |
|
T22 |
96 |
| auto[1] |
7254748 |
1 |
|
|
T20 |
160187 |
|
T21 |
297225 |
|
T22 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15989923 |
1 |
|
|
T20 |
302196 |
|
T21 |
551235 |
|
T22 |
132 |
| auto[1] |
928859 |
1 |
|
|
T20 |
18835 |
|
T21 |
41788 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9627645 |
1 |
|
|
T20 |
164441 |
|
T21 |
285685 |
|
T22 |
89 |
| auto[1] |
7291137 |
1 |
|
|
T20 |
156590 |
|
T21 |
307338 |
|
T22 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3209861 |
1 |
|
|
T20 |
68777 |
|
T21 |
130601 |
|
T22 |
27 |
| auto[1] |
auto[0] |
auto[1] |
469380 |
1 |
|
|
T20 |
9563 |
|
T21 |
20869 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3152417 |
1 |
|
|
T20 |
68978 |
|
T21 |
134949 |
|
T22 |
16 |
| auto[1] |
auto[1] |
auto[1] |
459479 |
1 |
|
|
T20 |
9272 |
|
T21 |
20919 |
|
T22 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9607677 |
1 |
|
|
T20 |
161445 |
|
T21 |
293263 |
|
T22 |
118 |
| auto[1] |
7311105 |
1 |
|
|
T20 |
159586 |
|
T21 |
299760 |
|
T22 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15987028 |
1 |
|
|
T20 |
301565 |
|
T21 |
552960 |
|
T22 |
133 |
| auto[1] |
931754 |
1 |
|
|
T20 |
19466 |
|
T21 |
40063 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9627465 |
1 |
|
|
T20 |
162107 |
|
T21 |
297736 |
|
T22 |
79 |
| auto[1] |
7291317 |
1 |
|
|
T20 |
158924 |
|
T21 |
295287 |
|
T22 |
55 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3171802 |
1 |
|
|
T20 |
68672 |
|
T21 |
124783 |
|
T22 |
47 |
| auto[1] |
auto[0] |
auto[1] |
463024 |
1 |
|
|
T20 |
9436 |
|
T21 |
19412 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3187761 |
1 |
|
|
T20 |
70786 |
|
T21 |
130441 |
|
T22 |
7 |
| auto[1] |
auto[1] |
auto[1] |
468730 |
1 |
|
|
T20 |
10030 |
|
T21 |
20651 |
|
T23 |
1485 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9634690 |
1 |
|
|
T20 |
157837 |
|
T21 |
298353 |
|
T22 |
88 |
| auto[1] |
7284092 |
1 |
|
|
T20 |
163194 |
|
T21 |
294670 |
|
T22 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15993268 |
1 |
|
|
T20 |
301663 |
|
T21 |
553122 |
|
T22 |
134 |
| auto[1] |
925514 |
1 |
|
|
T20 |
19368 |
|
T21 |
39901 |
|
T23 |
2481 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9647174 |
1 |
|
|
T20 |
160411 |
|
T21 |
296732 |
|
T22 |
109 |
| auto[1] |
7271608 |
1 |
|
|
T20 |
160620 |
|
T21 |
296291 |
|
T22 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3160474 |
1 |
|
|
T20 |
67950 |
|
T21 |
130404 |
|
T22 |
10 |
| auto[1] |
auto[0] |
auto[1] |
459864 |
1 |
|
|
T20 |
9324 |
|
T21 |
20165 |
|
T23 |
1130 |
| auto[1] |
auto[1] |
auto[0] |
3185620 |
1 |
|
|
T20 |
73302 |
|
T21 |
125986 |
|
T22 |
15 |
| auto[1] |
auto[1] |
auto[1] |
465650 |
1 |
|
|
T20 |
10044 |
|
T21 |
19736 |
|
T23 |
1351 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9640414 |
1 |
|
|
T20 |
161064 |
|
T21 |
304576 |
|
T22 |
87 |
| auto[1] |
7278368 |
1 |
|
|
T20 |
159967 |
|
T21 |
288447 |
|
T22 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15996962 |
1 |
|
|
T20 |
301551 |
|
T21 |
554827 |
|
T22 |
133 |
| auto[1] |
921820 |
1 |
|
|
T20 |
19480 |
|
T21 |
38196 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9685332 |
1 |
|
|
T20 |
161273 |
|
T21 |
307132 |
|
T22 |
98 |
| auto[1] |
7233450 |
1 |
|
|
T20 |
159758 |
|
T21 |
285891 |
|
T22 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3161110 |
1 |
|
|
T20 |
68563 |
|
T21 |
125826 |
|
T22 |
24 |
| auto[1] |
auto[0] |
auto[1] |
461519 |
1 |
|
|
T20 |
9337 |
|
T21 |
19539 |
|
T23 |
1453 |
| auto[1] |
auto[1] |
auto[0] |
3150520 |
1 |
|
|
T20 |
71715 |
|
T21 |
121869 |
|
T22 |
11 |
| auto[1] |
auto[1] |
auto[1] |
460301 |
1 |
|
|
T20 |
10143 |
|
T21 |
18657 |
|
T22 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9663970 |
1 |
|
|
T20 |
159127 |
|
T21 |
296109 |
|
T22 |
90 |
| auto[1] |
7254812 |
1 |
|
|
T20 |
161904 |
|
T21 |
296914 |
|
T22 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15991943 |
1 |
|
|
T20 |
301861 |
|
T21 |
554835 |
|
T22 |
133 |
| auto[1] |
926839 |
1 |
|
|
T20 |
19170 |
|
T21 |
38188 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9655321 |
1 |
|
|
T20 |
164308 |
|
T21 |
306898 |
|
T22 |
96 |
| auto[1] |
7263461 |
1 |
|
|
T20 |
156723 |
|
T21 |
286125 |
|
T22 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3178640 |
1 |
|
|
T20 |
70387 |
|
T21 |
122670 |
|
T22 |
35 |
| auto[1] |
auto[0] |
auto[1] |
464488 |
1 |
|
|
T20 |
9883 |
|
T21 |
18647 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3157982 |
1 |
|
|
T20 |
67166 |
|
T21 |
125267 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[1] |
462351 |
1 |
|
|
T20 |
9287 |
|
T21 |
19541 |
|
T23 |
1338 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9615577 |
1 |
|
|
T20 |
165779 |
|
T21 |
300054 |
|
T22 |
68 |
| auto[1] |
7303205 |
1 |
|
|
T20 |
155252 |
|
T21 |
292969 |
|
T22 |
66 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15992922 |
1 |
|
|
T20 |
301391 |
|
T21 |
553105 |
|
T22 |
132 |
| auto[1] |
925860 |
1 |
|
|
T20 |
19640 |
|
T21 |
39918 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9648455 |
1 |
|
|
T20 |
159362 |
|
T21 |
297676 |
|
T22 |
98 |
| auto[1] |
7270327 |
1 |
|
|
T20 |
161669 |
|
T21 |
295347 |
|
T22 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3169478 |
1 |
|
|
T20 |
69920 |
|
T21 |
128097 |
|
T22 |
14 |
| auto[1] |
auto[0] |
auto[1] |
462021 |
1 |
|
|
T20 |
9566 |
|
T21 |
20034 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3174989 |
1 |
|
|
T20 |
72109 |
|
T21 |
127332 |
|
T22 |
20 |
| auto[1] |
auto[1] |
auto[1] |
463839 |
1 |
|
|
T20 |
10074 |
|
T21 |
19884 |
|
T22 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9652856 |
1 |
|
|
T20 |
163071 |
|
T21 |
304076 |
|
T22 |
88 |
| auto[1] |
7265926 |
1 |
|
|
T20 |
157960 |
|
T21 |
288947 |
|
T22 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15992112 |
1 |
|
|
T20 |
301033 |
|
T21 |
552373 |
|
T22 |
134 |
| auto[1] |
926670 |
1 |
|
|
T20 |
19998 |
|
T21 |
40650 |
|
T23 |
2544 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9655323 |
1 |
|
|
T20 |
157834 |
|
T21 |
292831 |
|
T22 |
103 |
| auto[1] |
7263459 |
1 |
|
|
T20 |
163197 |
|
T21 |
300192 |
|
T22 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3177839 |
1 |
|
|
T20 |
71606 |
|
T21 |
133131 |
|
T22 |
19 |
| auto[1] |
auto[0] |
auto[1] |
465091 |
1 |
|
|
T20 |
10044 |
|
T21 |
21036 |
|
T23 |
1248 |
| auto[1] |
auto[1] |
auto[0] |
3158950 |
1 |
|
|
T20 |
71593 |
|
T21 |
126411 |
|
T22 |
12 |
| auto[1] |
auto[1] |
auto[1] |
461579 |
1 |
|
|
T20 |
9954 |
|
T21 |
19614 |
|
T23 |
1296 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9636893 |
1 |
|
|
T20 |
157639 |
|
T21 |
289459 |
|
T22 |
83 |
| auto[1] |
7281889 |
1 |
|
|
T20 |
163392 |
|
T21 |
303564 |
|
T22 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15984971 |
1 |
|
|
T20 |
301556 |
|
T21 |
553599 |
|
T22 |
133 |
| auto[1] |
933811 |
1 |
|
|
T20 |
19475 |
|
T21 |
39424 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9612376 |
1 |
|
|
T20 |
161637 |
|
T21 |
300419 |
|
T22 |
89 |
| auto[1] |
7306406 |
1 |
|
|
T20 |
159394 |
|
T21 |
292604 |
|
T22 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3179383 |
1 |
|
|
T20 |
66331 |
|
T21 |
124725 |
|
T22 |
18 |
| auto[1] |
auto[0] |
auto[1] |
466429 |
1 |
|
|
T20 |
8899 |
|
T21 |
19184 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3193212 |
1 |
|
|
T20 |
73588 |
|
T21 |
128455 |
|
T22 |
26 |
| auto[1] |
auto[1] |
auto[1] |
467382 |
1 |
|
|
T20 |
10576 |
|
T21 |
20240 |
|
T23 |
1224 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9651854 |
1 |
|
|
T20 |
165248 |
|
T21 |
302097 |
|
T22 |
90 |
| auto[1] |
7266928 |
1 |
|
|
T20 |
155783 |
|
T21 |
290926 |
|
T22 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15981678 |
1 |
|
|
T20 |
301764 |
|
T21 |
553056 |
|
T22 |
133 |
| auto[1] |
937104 |
1 |
|
|
T20 |
19267 |
|
T21 |
39967 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9581402 |
1 |
|
|
T20 |
161926 |
|
T21 |
297554 |
|
T22 |
96 |
| auto[1] |
7337380 |
1 |
|
|
T20 |
159105 |
|
T21 |
295469 |
|
T22 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3199641 |
1 |
|
|
T20 |
73277 |
|
T21 |
129122 |
|
T22 |
18 |
| auto[1] |
auto[0] |
auto[1] |
469002 |
1 |
|
|
T20 |
10246 |
|
T21 |
20335 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3200635 |
1 |
|
|
T20 |
66561 |
|
T21 |
126380 |
|
T22 |
19 |
| auto[1] |
auto[1] |
auto[1] |
468102 |
1 |
|
|
T20 |
9021 |
|
T21 |
19632 |
|
T23 |
1371 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9629222 |
1 |
|
|
T20 |
156701 |
|
T21 |
295215 |
|
T22 |
98 |
| auto[1] |
7289560 |
1 |
|
|
T20 |
164330 |
|
T21 |
297808 |
|
T22 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15990814 |
1 |
|
|
T20 |
300497 |
|
T21 |
553304 |
|
T22 |
134 |
| auto[1] |
927968 |
1 |
|
|
T20 |
20534 |
|
T21 |
39719 |
|
T23 |
2760 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9637559 |
1 |
|
|
T20 |
154052 |
|
T21 |
299014 |
|
T22 |
119 |
| auto[1] |
7281223 |
1 |
|
|
T20 |
166979 |
|
T21 |
294009 |
|
T22 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3180254 |
1 |
|
|
T20 |
70391 |
|
T21 |
127449 |
|
T22 |
15 |
| auto[1] |
auto[0] |
auto[1] |
463928 |
1 |
|
|
T20 |
9737 |
|
T21 |
19947 |
|
T23 |
1421 |
| auto[1] |
auto[1] |
auto[0] |
3173001 |
1 |
|
|
T20 |
76054 |
|
T21 |
126841 |
|
T23 |
10427 |
| auto[1] |
auto[1] |
auto[1] |
464040 |
1 |
|
|
T20 |
10797 |
|
T21 |
19772 |
|
T23 |
1339 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9617900 |
1 |
|
|
T20 |
160403 |
|
T21 |
299731 |
|
T22 |
102 |
| auto[1] |
7300882 |
1 |
|
|
T20 |
160628 |
|
T21 |
293292 |
|
T22 |
32 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15990300 |
1 |
|
|
T20 |
301913 |
|
T21 |
553811 |
|
T22 |
133 |
| auto[1] |
928482 |
1 |
|
|
T20 |
19118 |
|
T21 |
39212 |
|
T22 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9638993 |
1 |
|
|
T20 |
164177 |
|
T21 |
298690 |
|
T22 |
98 |
| auto[1] |
7279789 |
1 |
|
|
T20 |
156854 |
|
T21 |
294333 |
|
T22 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3175267 |
1 |
|
|
T20 |
68298 |
|
T21 |
130319 |
|
T22 |
25 |
| auto[1] |
auto[0] |
auto[1] |
463951 |
1 |
|
|
T20 |
9619 |
|
T21 |
19855 |
|
T22 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3176040 |
1 |
|
|
T20 |
69438 |
|
T21 |
124802 |
|
T22 |
10 |
| auto[1] |
auto[1] |
auto[1] |
464531 |
1 |
|
|
T20 |
9499 |
|
T21 |
19357 |
|
T23 |
1430 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9623641 |
1 |
|
|
T20 |
163897 |
|
T21 |
299370 |
|
T22 |
118 |
| auto[1] |
7295141 |
1 |
|
|
T20 |
157134 |
|
T21 |
293653 |
|
T22 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15990854 |
1 |
|
|
T20 |
301878 |
|
T21 |
553380 |
|
T22 |
132 |
| auto[1] |
927928 |
1 |
|
|
T20 |
19153 |
|
T21 |
39643 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9645669 |
1 |
|
|
T20 |
164436 |
|
T21 |
299560 |
|
T22 |
104 |
| auto[1] |
7273113 |
1 |
|
|
T20 |
156595 |
|
T21 |
293463 |
|
T22 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3168209 |
1 |
|
|
T20 |
69624 |
|
T21 |
123825 |
|
T22 |
23 |
| auto[1] |
auto[0] |
auto[1] |
463762 |
1 |
|
|
T20 |
9560 |
|
T21 |
19266 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3176976 |
1 |
|
|
T20 |
67818 |
|
T21 |
129995 |
|
T22 |
5 |
| auto[1] |
auto[1] |
auto[1] |
464166 |
1 |
|
|
T20 |
9593 |
|
T21 |
20377 |
|
T23 |
1366 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9619319 |
1 |
|
|
T20 |
159934 |
|
T21 |
295461 |
|
T22 |
110 |
| auto[1] |
7299463 |
1 |
|
|
T20 |
161097 |
|
T21 |
297562 |
|
T22 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15988511 |
1 |
|
|
T20 |
302359 |
|
T21 |
552148 |
|
T22 |
132 |
| auto[1] |
930271 |
1 |
|
|
T20 |
18672 |
|
T21 |
40875 |
|
T22 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9626004 |
1 |
|
|
T20 |
166368 |
|
T21 |
291245 |
|
T22 |
87 |
| auto[1] |
7292778 |
1 |
|
|
T20 |
154663 |
|
T21 |
301778 |
|
T22 |
47 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3175407 |
1 |
|
|
T20 |
67802 |
|
T21 |
128349 |
|
T22 |
35 |
| auto[1] |
auto[0] |
auto[1] |
463523 |
1 |
|
|
T20 |
9213 |
|
T21 |
19859 |
|
T22 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3187100 |
1 |
|
|
T20 |
68189 |
|
T21 |
132554 |
|
T22 |
10 |
| auto[1] |
auto[1] |
auto[1] |
466748 |
1 |
|
|
T20 |
9459 |
|
T21 |
21016 |
|
T23 |
1262 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |