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Group Instance : intr_event_lvllow_pin0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin0
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin1
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin10
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin10

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin10
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin10
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin11
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin11

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin11
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin11
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin12
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin12

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin12
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin12
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin13
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin13

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin13
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin13
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin14
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin14

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin14
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin14
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin15
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin15

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin15
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin15
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin16
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin16

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin16
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin16
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin17
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin17

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin17
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin17
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin18
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin18

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin18
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin18
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin19
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin19

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin19
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin19
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin2
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin20
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin20

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin20
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin20
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0

Go back
Group Instances:
intr_event_lvllow_pin0
intr_event_lvllow_pin1
intr_event_lvllow_pin10
intr_event_lvllow_pin11
intr_event_lvllow_pin12
intr_event_lvllow_pin13
intr_event_lvllow_pin14
intr_event_lvllow_pin15
intr_event_lvllow_pin16
intr_event_lvllow_pin17
intr_event_lvllow_pin18
intr_event_lvllow_pin19
intr_event_lvllow_pin2
intr_event_lvllow_pin20

Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9670371 1 T20 160461 T21 302559 T22 106
auto[1] 7248411 1 T20 160570 T21 290464 T22 28


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12587970 1 T20 219149 T21 410880 T22 118
auto[1] 4330812 1 T20 101882 T21 182143 T22 16


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9644643 1 T20 160589 T21 295659 T22 75
auto[1] 7274139 1 T20 160442 T21 297364 T22 59


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1480765 1 T20 28662 T21 59255 T22 34
auto[1] auto[0] auto[1] 2184552 1 T20 49197 T21 95295 T22 14
auto[1] auto[1] auto[0] 1462562 1 T20 29898 T21 55966 T22 9
auto[1] auto[1] auto[1] 2146260 1 T20 52685 T21 86848 T22 2


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9667066 1 T20 161244 T21 294214 T22 85
auto[1] 7251716 1 T20 159787 T21 298809 T22 49


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12590894 1 T20 221048 T21 416484 T22 108
auto[1] 4327888 1 T20 99983 T21 176539 T22 26


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9657178 1 T20 162671 T21 304154 T22 79
auto[1] 7261604 1 T20 158360 T21 288869 T22 55


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1477150 1 T20 28238 T21 56187 T22 10
auto[1] auto[0] auto[1] 2176088 1 T20 47777 T21 89721 T22 14
auto[1] auto[1] auto[0] 1456566 1 T20 30139 T21 56143 T22 19
auto[1] auto[1] auto[1] 2151800 1 T20 52206 T21 86818 T22 12


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9637362 1 T20 159087 T21 291176 T22 110
auto[1] 7281420 1 T20 161944 T21 301847 T22 24


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12592552 1 T20 218919 T21 414158 T22 119
auto[1] 4326230 1 T20 102112 T21 178865 T22 15


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9659555 1 T20 160878 T21 299880 T22 94
auto[1] 7259227 1 T20 160153 T21 293143 T22 40


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1473635 1 T20 27947 T21 56048 T22 24
auto[1] auto[0] auto[1] 2173311 1 T20 49184 T21 88161 T22 6
auto[1] auto[1] auto[0] 1459362 1 T20 30094 T21 58230 T22 1
auto[1] auto[1] auto[1] 2152919 1 T20 52928 T21 90704 T22 9


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9622984 1 T20 160317 T21 302198 T22 111
auto[1] 7295798 1 T20 160714 T21 290825 T22 23


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12578630 1 T20 221894 T21 417586 T22 119
auto[1] 4340152 1 T20 99137 T21 175437 T22 15


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9635821 1 T20 162329 T21 303944 T22 101
auto[1] 7282961 1 T20 158702 T21 289079 T22 33


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1469775 1 T20 28866 T21 56939 T22 15
auto[1] auto[0] auto[1] 2162918 1 T20 48113 T21 87015 T22 14
auto[1] auto[1] auto[0] 1473034 1 T20 30699 T21 56703 T22 3
auto[1] auto[1] auto[1] 2177234 1 T20 51024 T21 88422 T22 1


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9615045 1 T20 159683 T21 293633 T22 95
auto[1] 7303737 1 T20 161348 T21 299390 T22 39


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12572218 1 T20 218741 T21 416184 T22 128
auto[1] 4346564 1 T20 102290 T21 176839 T22 6


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9626014 1 T20 160410 T21 303497 T22 94
auto[1] 7292768 1 T20 160621 T21 289526 T22 40


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1478777 1 T20 29346 T21 56175 T22 21
auto[1] auto[0] auto[1] 2180546 1 T20 50333 T21 89575 T22 4
auto[1] auto[1] auto[0] 1467427 1 T20 28985 T21 56512 T22 13
auto[1] auto[1] auto[1] 2166018 1 T20 51957 T21 87264 T22 2


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9645475 1 T20 164385 T21 296909 T22 100
auto[1] 7273307 1 T20 156646 T21 296114 T22 34


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12585436 1 T20 223812 T21 415374 T22 121
auto[1] 4333346 1 T20 97219 T21 177649 T22 13


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9642538 1 T20 167205 T21 302708 T22 108
auto[1] 7276244 1 T20 153826 T21 290315 T22 26


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1473942 1 T20 29082 T21 56442 T22 5
auto[1] auto[0] auto[1] 2174368 1 T20 50609 T21 89302 T22 13
auto[1] auto[1] auto[0] 1468956 1 T20 27525 T21 56224 T22 8
auto[1] auto[1] auto[1] 2158978 1 T20 46610 T21 88347 T23 4221


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9664034 1 T20 160844 T21 295798 T22 96
auto[1] 7254748 1 T20 160187 T21 297225 T22 38


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12563165 1 T20 217156 T21 411300 T22 100
auto[1] 4355617 1 T20 103875 T21 181723 T22 34


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9606864 1 T20 157508 T21 296026 T22 63
auto[1] 7311918 1 T20 163523 T21 296997 T22 71


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1481294 1 T20 29799 T21 55194 T22 34
auto[1] auto[0] auto[1] 2183983 1 T20 50537 T21 85916 T22 14
auto[1] auto[1] auto[0] 1475007 1 T20 29849 T21 60080 T22 3
auto[1] auto[1] auto[1] 2171634 1 T20 53338 T21 95807 T22 20


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9607677 1 T20 161445 T21 293263 T22 118
auto[1] 7311105 1 T20 159586 T21 299760 T22 16


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12586393 1 T20 222617 T21 417532 T22 105
auto[1] 4332389 1 T20 98414 T21 175491 T22 29


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9648119 1 T20 164494 T21 305419 T22 91
auto[1] 7270663 1 T20 156537 T21 287604 T22 43


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1465790 1 T20 29062 T21 55460 T22 14
auto[1] auto[0] auto[1] 2162605 1 T20 49877 T21 87067 T22 26
auto[1] auto[1] auto[0] 1472484 1 T20 29061 T21 56653 T23 7837
auto[1] auto[1] auto[1] 2169784 1 T20 48537 T21 88424 T22 3


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9634690 1 T20 157837 T21 298353 T22 88
auto[1] 7284092 1 T20 163194 T21 294670 T22 46


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12571439 1 T20 219414 T21 406971 T22 126
auto[1] 4347343 1 T20 101617 T21 186052 T22 8


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9629391 1 T20 160326 T21 288778 T22 100
auto[1] 7289391 1 T20 160705 T21 304245 T22 34


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1475898 1 T20 29474 T21 59652 T22 18
auto[1] auto[0] auto[1] 2181986 1 T20 50727 T21 95316 T22 8
auto[1] auto[1] auto[0] 1466150 1 T20 29614 T21 58541 T22 8
auto[1] auto[1] auto[1] 2165357 1 T20 50890 T21 90736 T23 4390


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9640414 1 T20 161064 T21 304576 T22 87
auto[1] 7278368 1 T20 159967 T21 288447 T22 47


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12543916 1 T20 221262 T21 410471 T22 112
auto[1] 4374866 1 T20 99769 T21 182552 T22 22


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9582830 1 T20 163116 T21 295108 T22 95
auto[1] 7335952 1 T20 157915 T21 297915 T22 39


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1478529 1 T20 29332 T21 57721 T22 14
auto[1] auto[0] auto[1] 2181103 1 T20 48741 T21 91589 T22 14
auto[1] auto[1] auto[0] 1482557 1 T20 28814 T21 57642 T22 3
auto[1] auto[1] auto[1] 2193763 1 T20 51028 T21 90963 T22 8


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9663970 1 T20 159127 T21 296109 T22 90
auto[1] 7254812 1 T20 161904 T21 296914 T22 44


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12616120 1 T20 217732 T21 411726 T22 98
auto[1] 4302662 1 T20 103299 T21 181297 T22 36


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9693190 1 T20 159468 T21 296217 T22 84
auto[1] 7225592 1 T20 161563 T21 296806 T22 50


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1468103 1 T20 28771 T21 57200 T22 11
auto[1] auto[0] auto[1] 2159373 1 T20 50032 T21 89734 T22 20
auto[1] auto[1] auto[0] 1454827 1 T20 29493 T21 58309 T22 3
auto[1] auto[1] auto[1] 2143289 1 T20 53267 T21 91563 T22 16


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9615577 1 T20 165779 T21 300054 T22 68
auto[1] 7303205 1 T20 155252 T21 292969 T22 66


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12564967 1 T20 222240 T21 412954 T22 123
auto[1] 4353815 1 T20 98791 T21 180069 T22 11


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9615335 1 T20 164186 T21 298984 T22 92
auto[1] 7303447 1 T20 156845 T21 294039 T22 42


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1477708 1 T20 30755 T21 57488 T22 13
auto[1] auto[0] auto[1] 2183643 1 T20 52414 T21 89851 T22 6
auto[1] auto[1] auto[0] 1471924 1 T20 27299 T21 56482 T22 18
auto[1] auto[1] auto[1] 2170172 1 T20 46377 T21 90218 T22 5


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9652856 1 T20 163071 T21 304076 T22 88
auto[1] 7265926 1 T20 157960 T21 288947 T22 46


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12579344 1 T20 223066 T21 416647 T22 114
auto[1] 4339438 1 T20 97965 T21 176376 T22 20


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9624125 1 T20 165165 T21 304523 T22 90
auto[1] 7294657 1 T20 155866 T21 288500 T22 44


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1485639 1 T20 29439 T21 56956 T22 19
auto[1] auto[0] auto[1] 2180740 1 T20 50175 T21 89807 T22 7
auto[1] auto[1] auto[0] 1469580 1 T20 28462 T21 55168 T22 5
auto[1] auto[1] auto[1] 2158698 1 T20 47790 T21 86569 T22 13


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9636893 1 T20 157639 T21 289459 T22 83
auto[1] 7281889 1 T20 163392 T21 303564 T22 51


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12572990 1 T20 217331 T21 409018 T22 98
auto[1] 4345792 1 T20 103700 T21 184005 T22 36


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9625187 1 T20 157020 T21 294037 T22 79
auto[1] 7293595 1 T20 164011 T21 298986 T22 55


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1479177 1 T20 29159 T21 57159 T22 5
auto[1] auto[0] auto[1] 2170437 1 T20 50454 T21 92129 T22 23
auto[1] auto[1] auto[0] 1468626 1 T20 31152 T21 57822 T22 14
auto[1] auto[1] auto[1] 2175355 1 T20 53246 T21 91876 T22 13


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%