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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 949
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T74 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1800731573 Jul 24 05:13:57 PM PDT 24 Jul 24 05:13:58 PM PDT 24 92549397 ps
T759 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3928604429 Jul 24 05:13:49 PM PDT 24 Jul 24 05:13:50 PM PDT 24 22698124 ps
T760 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3862031634 Jul 24 05:14:09 PM PDT 24 Jul 24 05:14:10 PM PDT 24 71214199 ps
T761 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2360350596 Jul 24 05:14:06 PM PDT 24 Jul 24 05:14:08 PM PDT 24 48395163 ps
T762 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1135821063 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 72073387 ps
T763 /workspace/coverage/cover_reg_top/35.gpio_intr_test.4251021939 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 18081702 ps
T764 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1006419753 Jul 24 05:14:00 PM PDT 24 Jul 24 05:14:01 PM PDT 24 48182353 ps
T765 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1159419280 Jul 24 05:14:12 PM PDT 24 Jul 24 05:14:13 PM PDT 24 18317150 ps
T766 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1774351900 Jul 24 05:14:02 PM PDT 24 Jul 24 05:14:03 PM PDT 24 111490336 ps
T767 /workspace/coverage/cover_reg_top/20.gpio_intr_test.153213051 Jul 24 05:14:06 PM PDT 24 Jul 24 05:14:07 PM PDT 24 30047515 ps
T768 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2632856632 Jul 24 05:14:03 PM PDT 24 Jul 24 05:14:04 PM PDT 24 16712431 ps
T769 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.697792337 Jul 24 05:14:07 PM PDT 24 Jul 24 05:14:08 PM PDT 24 137145455 ps
T770 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.49949293 Jul 24 05:14:00 PM PDT 24 Jul 24 05:14:02 PM PDT 24 117106101 ps
T771 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3650728194 Jul 24 05:14:00 PM PDT 24 Jul 24 05:14:01 PM PDT 24 82620295 ps
T772 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4073414499 Jul 24 05:14:33 PM PDT 24 Jul 24 05:14:35 PM PDT 24 289388504 ps
T773 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4124559732 Jul 24 05:14:00 PM PDT 24 Jul 24 05:14:01 PM PDT 24 16980203 ps
T774 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3370170589 Jul 24 05:13:58 PM PDT 24 Jul 24 05:13:58 PM PDT 24 15730289 ps
T775 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3928648989 Jul 24 05:13:57 PM PDT 24 Jul 24 05:13:58 PM PDT 24 65991083 ps
T776 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1974327542 Jul 24 05:13:57 PM PDT 24 Jul 24 05:13:58 PM PDT 24 145415034 ps
T777 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3716784275 Jul 24 05:14:02 PM PDT 24 Jul 24 05:14:03 PM PDT 24 14070457 ps
T778 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1305214671 Jul 24 05:14:02 PM PDT 24 Jul 24 05:14:03 PM PDT 24 12686470 ps
T779 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3629748136 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 13879214 ps
T780 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2963639064 Jul 24 05:14:03 PM PDT 24 Jul 24 05:14:04 PM PDT 24 15824204 ps
T781 /workspace/coverage/cover_reg_top/3.gpio_intr_test.517536613 Jul 24 05:13:58 PM PDT 24 Jul 24 05:13:59 PM PDT 24 15060773 ps
T782 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2114442339 Jul 24 05:14:17 PM PDT 24 Jul 24 05:14:17 PM PDT 24 32085494 ps
T783 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2193452246 Jul 24 05:13:58 PM PDT 24 Jul 24 05:13:59 PM PDT 24 59337947 ps
T784 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2784433819 Jul 24 05:13:54 PM PDT 24 Jul 24 05:13:55 PM PDT 24 78610699 ps
T75 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1729355156 Jul 24 05:14:04 PM PDT 24 Jul 24 05:14:06 PM PDT 24 66291888 ps
T76 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2589657892 Jul 24 05:14:15 PM PDT 24 Jul 24 05:14:16 PM PDT 24 19178119 ps
T785 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1200496039 Jul 24 05:14:02 PM PDT 24 Jul 24 05:14:04 PM PDT 24 129181659 ps
T786 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3258589668 Jul 24 05:14:32 PM PDT 24 Jul 24 05:14:34 PM PDT 24 20217881 ps
T787 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.309541292 Jul 24 05:14:05 PM PDT 24 Jul 24 05:14:06 PM PDT 24 167914453 ps
T788 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1534025027 Jul 24 05:14:26 PM PDT 24 Jul 24 05:14:26 PM PDT 24 75954524 ps
T789 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3837974346 Jul 24 05:14:07 PM PDT 24 Jul 24 05:14:07 PM PDT 24 32465897 ps
T77 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3795073395 Jul 24 05:14:16 PM PDT 24 Jul 24 05:14:16 PM PDT 24 90824544 ps
T790 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1673247956 Jul 24 05:13:54 PM PDT 24 Jul 24 05:13:54 PM PDT 24 33633321 ps
T791 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.776405371 Jul 24 05:14:06 PM PDT 24 Jul 24 05:14:07 PM PDT 24 43069531 ps
T792 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4094698238 Jul 24 05:14:06 PM PDT 24 Jul 24 05:14:07 PM PDT 24 15090600 ps
T793 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2164892173 Jul 24 05:14:06 PM PDT 24 Jul 24 05:14:07 PM PDT 24 14677568 ps
T794 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2854057491 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 14222241 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2279388212 Jul 24 05:13:56 PM PDT 24 Jul 24 05:13:56 PM PDT 24 28530666 ps
T78 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.874345542 Jul 24 05:13:57 PM PDT 24 Jul 24 05:13:58 PM PDT 24 67706469 ps
T796 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3559364660 Jul 24 05:14:10 PM PDT 24 Jul 24 05:14:12 PM PDT 24 37305394 ps
T797 /workspace/coverage/cover_reg_top/43.gpio_intr_test.4151243345 Jul 24 05:14:02 PM PDT 24 Jul 24 05:14:03 PM PDT 24 20690225 ps
T798 /workspace/coverage/cover_reg_top/10.gpio_intr_test.929986422 Jul 24 05:14:01 PM PDT 24 Jul 24 05:14:01 PM PDT 24 43771682 ps
T799 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4115164093 Jul 24 05:14:02 PM PDT 24 Jul 24 05:14:03 PM PDT 24 23740665 ps
T800 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3905277150 Jul 24 05:13:54 PM PDT 24 Jul 24 05:13:55 PM PDT 24 30759251 ps
T96 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1916957245 Jul 24 05:14:02 PM PDT 24 Jul 24 05:14:04 PM PDT 24 157191673 ps
T801 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2699720051 Jul 24 05:14:03 PM PDT 24 Jul 24 05:14:04 PM PDT 24 112451050 ps
T802 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.381730598 Jul 24 05:13:58 PM PDT 24 Jul 24 05:14:00 PM PDT 24 128362590 ps
T803 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2417287954 Jul 24 05:13:56 PM PDT 24 Jul 24 05:13:58 PM PDT 24 96396797 ps
T79 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1475854911 Jul 24 05:13:53 PM PDT 24 Jul 24 05:13:54 PM PDT 24 26340699 ps
T804 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3071945805 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 14167154 ps
T805 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2802609265 Jul 24 05:13:58 PM PDT 24 Jul 24 05:14:01 PM PDT 24 1025983395 ps
T806 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.210854239 Jul 24 05:14:10 PM PDT 24 Jul 24 05:14:12 PM PDT 24 149106888 ps
T807 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4148649654 Jul 24 05:13:57 PM PDT 24 Jul 24 05:13:58 PM PDT 24 16247425 ps
T808 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3706611885 Jul 24 05:13:50 PM PDT 24 Jul 24 05:13:51 PM PDT 24 14665757 ps
T809 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1767761607 Jul 24 05:14:09 PM PDT 24 Jul 24 05:14:11 PM PDT 24 272555132 ps
T810 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1700613916 Jul 24 05:14:03 PM PDT 24 Jul 24 05:14:05 PM PDT 24 159961114 ps
T811 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1527939242 Jul 24 05:13:58 PM PDT 24 Jul 24 05:14:01 PM PDT 24 2235434688 ps
T812 /workspace/coverage/cover_reg_top/28.gpio_intr_test.461589222 Jul 24 05:14:06 PM PDT 24 Jul 24 05:14:07 PM PDT 24 66935631 ps
T813 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3874591674 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 13204184 ps
T80 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3911930280 Jul 24 05:13:53 PM PDT 24 Jul 24 05:13:54 PM PDT 24 52285912 ps
T814 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3494825576 Jul 24 05:13:50 PM PDT 24 Jul 24 05:13:52 PM PDT 24 453551312 ps
T815 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1102056839 Jul 24 05:14:12 PM PDT 24 Jul 24 05:14:13 PM PDT 24 11687082 ps
T816 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.611204458 Jul 24 05:13:55 PM PDT 24 Jul 24 05:13:57 PM PDT 24 91972849 ps
T817 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4090942890 Jul 24 05:14:03 PM PDT 24 Jul 24 05:14:04 PM PDT 24 33762972 ps
T818 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.980397959 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 66353764 ps
T819 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3227311135 Jul 24 05:14:05 PM PDT 24 Jul 24 05:14:08 PM PDT 24 486080824 ps
T820 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.215778344 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:10 PM PDT 24 302805400 ps
T821 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3174101579 Jul 24 05:14:06 PM PDT 24 Jul 24 05:14:07 PM PDT 24 154413244 ps
T822 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2143197316 Jul 24 05:14:02 PM PDT 24 Jul 24 05:14:03 PM PDT 24 35978455 ps
T823 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2778423818 Jul 24 05:13:54 PM PDT 24 Jul 24 05:13:55 PM PDT 24 52538358 ps
T824 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.272764990 Jul 24 05:13:59 PM PDT 24 Jul 24 05:14:02 PM PDT 24 154037236 ps
T825 /workspace/coverage/cover_reg_top/16.gpio_intr_test.672664333 Jul 24 05:14:13 PM PDT 24 Jul 24 05:14:14 PM PDT 24 46740595 ps
T826 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2347578399 Jul 24 05:14:10 PM PDT 24 Jul 24 05:14:11 PM PDT 24 36481919 ps
T827 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3713642135 Jul 24 05:14:10 PM PDT 24 Jul 24 05:14:11 PM PDT 24 17959961 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.26352105 Jul 24 05:14:05 PM PDT 24 Jul 24 05:14:06 PM PDT 24 18052243 ps
T829 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2917799190 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 23821573 ps
T830 /workspace/coverage/cover_reg_top/30.gpio_intr_test.4168348510 Jul 24 05:14:04 PM PDT 24 Jul 24 05:14:05 PM PDT 24 37692784 ps
T831 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3528386730 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 12298424 ps
T832 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1079490183 Jul 24 05:14:02 PM PDT 24 Jul 24 05:14:03 PM PDT 24 20483926 ps
T833 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2912431373 Jul 24 05:14:11 PM PDT 24 Jul 24 05:14:11 PM PDT 24 21271382 ps
T834 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2809987104 Jul 24 05:14:04 PM PDT 24 Jul 24 05:14:05 PM PDT 24 33689219 ps
T835 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3782296709 Jul 24 05:14:11 PM PDT 24 Jul 24 05:14:12 PM PDT 24 130051636 ps
T836 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3764368395 Jul 24 05:14:10 PM PDT 24 Jul 24 05:14:11 PM PDT 24 16532853 ps
T837 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3167439188 Jul 24 05:14:03 PM PDT 24 Jul 24 05:14:04 PM PDT 24 21470898 ps
T838 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.671218310 Jul 24 05:13:53 PM PDT 24 Jul 24 05:13:54 PM PDT 24 160915779 ps
T839 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2737384720 Jul 24 05:14:07 PM PDT 24 Jul 24 05:14:09 PM PDT 24 50454583 ps
T840 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1660732116 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:10 PM PDT 24 36943108 ps
T841 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2765278388 Jul 24 05:13:59 PM PDT 24 Jul 24 05:14:00 PM PDT 24 29111642 ps
T842 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1855132628 Jul 24 05:14:07 PM PDT 24 Jul 24 05:14:10 PM PDT 24 108974842 ps
T843 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.959745595 Jul 24 05:13:51 PM PDT 24 Jul 24 05:13:53 PM PDT 24 147595387 ps
T844 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2007480940 Jul 24 05:13:58 PM PDT 24 Jul 24 05:13:59 PM PDT 24 18263549 ps
T845 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.341247371 Jul 24 05:14:10 PM PDT 24 Jul 24 05:14:11 PM PDT 24 13442669 ps
T846 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1806242559 Jul 24 05:13:51 PM PDT 24 Jul 24 05:13:52 PM PDT 24 11333194 ps
T847 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3540267941 Jul 24 05:14:07 PM PDT 24 Jul 24 05:14:08 PM PDT 24 91950980 ps
T848 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.21274641 Jul 24 05:14:04 PM PDT 24 Jul 24 05:14:07 PM PDT 24 159120877 ps
T849 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1725103316 Jul 24 05:14:04 PM PDT 24 Jul 24 05:14:05 PM PDT 24 49118233 ps
T850 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1113399987 Jul 24 05:14:40 PM PDT 24 Jul 24 05:14:41 PM PDT 24 239842381 ps
T851 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3285731786 Jul 24 05:14:26 PM PDT 24 Jul 24 05:14:27 PM PDT 24 35649418 ps
T852 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3399911272 Jul 24 05:14:10 PM PDT 24 Jul 24 05:14:12 PM PDT 24 58904887 ps
T853 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1590103692 Jul 24 05:14:21 PM PDT 24 Jul 24 05:14:22 PM PDT 24 216182745 ps
T854 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2943277078 Jul 24 05:14:14 PM PDT 24 Jul 24 05:14:14 PM PDT 24 80522120 ps
T855 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3323262919 Jul 24 05:14:22 PM PDT 24 Jul 24 05:14:23 PM PDT 24 445207265 ps
T856 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3893466113 Jul 24 05:14:32 PM PDT 24 Jul 24 05:14:34 PM PDT 24 302197484 ps
T857 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2105219028 Jul 24 05:14:09 PM PDT 24 Jul 24 05:14:10 PM PDT 24 230994520 ps
T858 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4085847702 Jul 24 05:14:38 PM PDT 24 Jul 24 05:14:39 PM PDT 24 29163217 ps
T859 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.240624259 Jul 24 05:14:22 PM PDT 24 Jul 24 05:14:23 PM PDT 24 56779626 ps
T860 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3524135800 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 195444569 ps
T861 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4292883072 Jul 24 05:14:25 PM PDT 24 Jul 24 05:14:27 PM PDT 24 102409104 ps
T862 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.845436735 Jul 24 05:14:18 PM PDT 24 Jul 24 05:14:19 PM PDT 24 38876646 ps
T863 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3790825719 Jul 24 05:14:25 PM PDT 24 Jul 24 05:14:27 PM PDT 24 643154406 ps
T864 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2608400111 Jul 24 05:14:41 PM PDT 24 Jul 24 05:14:43 PM PDT 24 233513608 ps
T865 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2837377365 Jul 24 05:14:14 PM PDT 24 Jul 24 05:14:15 PM PDT 24 171495452 ps
T866 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3079926265 Jul 24 05:14:18 PM PDT 24 Jul 24 05:14:19 PM PDT 24 433974759 ps
T867 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1235915717 Jul 24 05:14:09 PM PDT 24 Jul 24 05:14:10 PM PDT 24 65220620 ps
T868 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1735857674 Jul 24 05:14:27 PM PDT 24 Jul 24 05:14:29 PM PDT 24 69740666 ps
T869 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1025243434 Jul 24 05:14:13 PM PDT 24 Jul 24 05:14:14 PM PDT 24 323441774 ps
T870 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.476702091 Jul 24 05:14:28 PM PDT 24 Jul 24 05:14:30 PM PDT 24 47522027 ps
T871 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.507698392 Jul 24 05:14:30 PM PDT 24 Jul 24 05:14:31 PM PDT 24 109207179 ps
T872 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3858089539 Jul 24 05:14:18 PM PDT 24 Jul 24 05:14:19 PM PDT 24 708231864 ps
T873 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2897169166 Jul 24 05:14:26 PM PDT 24 Jul 24 05:14:27 PM PDT 24 419403201 ps
T874 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3234616509 Jul 24 05:14:25 PM PDT 24 Jul 24 05:14:27 PM PDT 24 160549445 ps
T875 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1658928389 Jul 24 05:14:30 PM PDT 24 Jul 24 05:14:32 PM PDT 24 444661664 ps
T876 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1296986061 Jul 24 05:14:14 PM PDT 24 Jul 24 05:14:15 PM PDT 24 40090885 ps
T877 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2103834478 Jul 24 05:14:17 PM PDT 24 Jul 24 05:14:18 PM PDT 24 209238470 ps
T878 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1777170967 Jul 24 05:14:17 PM PDT 24 Jul 24 05:14:18 PM PDT 24 289408925 ps
T879 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4172292966 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:10 PM PDT 24 175562648 ps
T880 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2623084856 Jul 24 05:14:20 PM PDT 24 Jul 24 05:14:21 PM PDT 24 22781918 ps
T881 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.12106246 Jul 24 05:14:26 PM PDT 24 Jul 24 05:14:27 PM PDT 24 37950987 ps
T882 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2132058865 Jul 24 05:14:23 PM PDT 24 Jul 24 05:14:24 PM PDT 24 173412009 ps
T883 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3822221104 Jul 24 05:14:05 PM PDT 24 Jul 24 05:14:06 PM PDT 24 100789901 ps
T884 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3683421112 Jul 24 05:14:38 PM PDT 24 Jul 24 05:14:40 PM PDT 24 189073907 ps
T885 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1890961992 Jul 24 05:14:50 PM PDT 24 Jul 24 05:14:51 PM PDT 24 144601654 ps
T886 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1709390243 Jul 24 05:14:48 PM PDT 24 Jul 24 05:14:49 PM PDT 24 301296002 ps
T887 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1013760816 Jul 24 05:14:32 PM PDT 24 Jul 24 05:14:33 PM PDT 24 201157167 ps
T888 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3046430996 Jul 24 05:14:24 PM PDT 24 Jul 24 05:14:26 PM PDT 24 45496203 ps
T889 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3586045160 Jul 24 05:14:12 PM PDT 24 Jul 24 05:14:13 PM PDT 24 61338287 ps
T890 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3172019215 Jul 24 05:14:27 PM PDT 24 Jul 24 05:14:28 PM PDT 24 57811831 ps
T891 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2998500140 Jul 24 05:14:33 PM PDT 24 Jul 24 05:14:34 PM PDT 24 40378474 ps
T892 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.749200787 Jul 24 05:14:25 PM PDT 24 Jul 24 05:14:26 PM PDT 24 149548429 ps
T893 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4201851813 Jul 24 05:14:32 PM PDT 24 Jul 24 05:14:33 PM PDT 24 52724141 ps
T894 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1859820018 Jul 24 05:14:38 PM PDT 24 Jul 24 05:14:40 PM PDT 24 563418732 ps
T895 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3114755730 Jul 24 05:14:43 PM PDT 24 Jul 24 05:14:45 PM PDT 24 83432967 ps
T896 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2868205907 Jul 24 05:14:38 PM PDT 24 Jul 24 05:14:39 PM PDT 24 54831850 ps
T897 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3103398995 Jul 24 05:14:09 PM PDT 24 Jul 24 05:14:10 PM PDT 24 95021513 ps
T898 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3152039372 Jul 24 05:14:19 PM PDT 24 Jul 24 05:14:20 PM PDT 24 194487473 ps
T899 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3984395142 Jul 24 05:14:17 PM PDT 24 Jul 24 05:14:17 PM PDT 24 19803042 ps
T900 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3563740218 Jul 24 05:14:34 PM PDT 24 Jul 24 05:14:35 PM PDT 24 81400561 ps
T901 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3810399552 Jul 24 05:14:52 PM PDT 24 Jul 24 05:14:53 PM PDT 24 113279323 ps
T902 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.346969606 Jul 24 05:14:09 PM PDT 24 Jul 24 05:14:10 PM PDT 24 291064152 ps
T903 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2967735794 Jul 24 05:14:12 PM PDT 24 Jul 24 05:14:13 PM PDT 24 197876280 ps
T904 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.834487534 Jul 24 05:14:32 PM PDT 24 Jul 24 05:14:34 PM PDT 24 63953763 ps
T905 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2375343751 Jul 24 05:14:44 PM PDT 24 Jul 24 05:14:45 PM PDT 24 808688057 ps
T906 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3765428140 Jul 24 05:14:15 PM PDT 24 Jul 24 05:14:17 PM PDT 24 247799156 ps
T907 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1293180189 Jul 24 05:14:30 PM PDT 24 Jul 24 05:14:31 PM PDT 24 164954508 ps
T908 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1714751198 Jul 24 05:14:47 PM PDT 24 Jul 24 05:14:48 PM PDT 24 128205596 ps
T909 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1331306954 Jul 24 05:14:06 PM PDT 24 Jul 24 05:14:07 PM PDT 24 42331827 ps
T910 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3405800669 Jul 24 05:14:10 PM PDT 24 Jul 24 05:14:12 PM PDT 24 275995373 ps
T911 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2637468925 Jul 24 05:14:27 PM PDT 24 Jul 24 05:14:28 PM PDT 24 120028542 ps
T912 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3763248589 Jul 24 05:14:07 PM PDT 24 Jul 24 05:14:08 PM PDT 24 61676566 ps
T913 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.767120391 Jul 24 05:14:30 PM PDT 24 Jul 24 05:14:31 PM PDT 24 24283182 ps
T914 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1738602759 Jul 24 05:14:21 PM PDT 24 Jul 24 05:14:23 PM PDT 24 194270837 ps
T915 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.993412880 Jul 24 05:14:13 PM PDT 24 Jul 24 05:14:14 PM PDT 24 91737036 ps
T916 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2714495392 Jul 24 05:14:11 PM PDT 24 Jul 24 05:14:12 PM PDT 24 47456123 ps
T917 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1848316109 Jul 24 05:14:24 PM PDT 24 Jul 24 05:14:25 PM PDT 24 134619909 ps
T918 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1049548728 Jul 24 05:14:21 PM PDT 24 Jul 24 05:14:21 PM PDT 24 126718936 ps
T919 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.415593507 Jul 24 05:14:16 PM PDT 24 Jul 24 05:14:17 PM PDT 24 369955842 ps
T920 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.106778353 Jul 24 05:14:27 PM PDT 24 Jul 24 05:14:28 PM PDT 24 61292086 ps
T921 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.645133897 Jul 24 05:14:37 PM PDT 24 Jul 24 05:14:38 PM PDT 24 100153516 ps
T922 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1004880765 Jul 24 05:14:26 PM PDT 24 Jul 24 05:14:27 PM PDT 24 45555545 ps
T923 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3462062004 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:10 PM PDT 24 138938965 ps
T924 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.60476917 Jul 24 05:14:16 PM PDT 24 Jul 24 05:14:17 PM PDT 24 51468755 ps
T925 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1267711236 Jul 24 05:14:25 PM PDT 24 Jul 24 05:14:27 PM PDT 24 51309256 ps
T926 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.252795733 Jul 24 05:14:26 PM PDT 24 Jul 24 05:14:27 PM PDT 24 260633241 ps
T927 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1910592984 Jul 24 05:14:36 PM PDT 24 Jul 24 05:14:38 PM PDT 24 165385184 ps
T928 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249730103 Jul 24 05:14:47 PM PDT 24 Jul 24 05:14:49 PM PDT 24 413553293 ps
T929 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.961956235 Jul 24 05:14:04 PM PDT 24 Jul 24 05:14:05 PM PDT 24 121846916 ps
T930 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3401228127 Jul 24 05:14:25 PM PDT 24 Jul 24 05:14:27 PM PDT 24 92036912 ps
T931 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2664984364 Jul 24 05:14:26 PM PDT 24 Jul 24 05:14:32 PM PDT 24 130803711 ps
T932 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1611788729 Jul 24 05:14:09 PM PDT 24 Jul 24 05:14:10 PM PDT 24 108733849 ps
T933 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1704139065 Jul 24 05:14:15 PM PDT 24 Jul 24 05:14:17 PM PDT 24 366067693 ps
T934 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2204771337 Jul 24 05:14:15 PM PDT 24 Jul 24 05:14:16 PM PDT 24 56561658 ps
T935 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1754332471 Jul 24 05:14:36 PM PDT 24 Jul 24 05:14:37 PM PDT 24 41423450 ps
T936 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2595940565 Jul 24 05:14:33 PM PDT 24 Jul 24 05:14:35 PM PDT 24 72224629 ps
T937 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2681472181 Jul 24 05:14:17 PM PDT 24 Jul 24 05:14:18 PM PDT 24 79708452 ps
T938 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2917948513 Jul 24 05:14:21 PM PDT 24 Jul 24 05:14:22 PM PDT 24 71893726 ps
T939 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2447759882 Jul 24 05:14:21 PM PDT 24 Jul 24 05:14:22 PM PDT 24 794323217 ps
T940 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.383390322 Jul 24 05:14:33 PM PDT 24 Jul 24 05:14:34 PM PDT 24 75317228 ps
T941 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1106033468 Jul 24 05:14:36 PM PDT 24 Jul 24 05:14:37 PM PDT 24 134644906 ps
T942 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3508480013 Jul 24 05:14:04 PM PDT 24 Jul 24 05:14:05 PM PDT 24 29305205 ps
T943 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3702808128 Jul 24 05:14:28 PM PDT 24 Jul 24 05:14:29 PM PDT 24 222688460 ps
T944 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3370906656 Jul 24 05:14:31 PM PDT 24 Jul 24 05:14:32 PM PDT 24 50029853 ps
T945 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1756182149 Jul 24 05:14:08 PM PDT 24 Jul 24 05:14:09 PM PDT 24 42901902 ps
T946 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1786367155 Jul 24 05:14:15 PM PDT 24 Jul 24 05:14:16 PM PDT 24 90021707 ps
T947 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3566982734 Jul 24 05:14:36 PM PDT 24 Jul 24 05:14:37 PM PDT 24 105488056 ps
T948 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3853721855 Jul 24 05:14:12 PM PDT 24 Jul 24 05:14:13 PM PDT 24 181160352 ps
T949 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2245696134 Jul 24 05:14:10 PM PDT 24 Jul 24 05:14:11 PM PDT 24 60037618 ps

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1203317450
Short name T21
Test name
Test status
Simulation time 53634212962 ps
CPU time 1486.21 seconds
Started Jul 24 05:17:02 PM PDT 24
Finished Jul 24 05:41:48 PM PDT 24
Peak memory 198736 kb
Host smart-8ea896ca-e9fd-49b7-b060-5532e9cad69a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1203317450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1203317450
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1234462750
Short name T24
Test name
Test status
Simulation time 34823960 ps
CPU time 1.38 seconds
Started Jul 24 05:17:22 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 198548 kb
Host smart-8a0707c3-f3db-43c1-aac1-d8d5075c87b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234462750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1234462750
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4082713625
Short name T12
Test name
Test status
Simulation time 59705399 ps
CPU time 0.86 seconds
Started Jul 24 05:16:39 PM PDT 24
Finished Jul 24 05:16:40 PM PDT 24
Peak memory 214268 kb
Host smart-413e002f-97ca-4e9d-829b-d2ec76bc362b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082713625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4082713625
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2015411479
Short name T70
Test name
Test status
Simulation time 21149703 ps
CPU time 0.67 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 195968 kb
Host smart-e7a1dc8e-63b0-4ecb-8f98-54a1ce3f8809
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015411479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2015411479
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3503413062
Short name T4
Test name
Test status
Simulation time 196907974 ps
CPU time 2.38 seconds
Started Jul 24 05:17:09 PM PDT 24
Finished Jul 24 05:17:12 PM PDT 24
Peak memory 197824 kb
Host smart-1f936945-abbb-4aa0-8673-8cc262a3a1d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503413062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3503413062
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3193385228
Short name T38
Test name
Test status
Simulation time 116287346 ps
CPU time 1.4 seconds
Started Jul 24 05:13:57 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 198348 kb
Host smart-b2cee5f0-3842-4971-ae71-6fe107dcabe9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193385228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3193385228
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2952064630
Short name T35
Test name
Test status
Simulation time 98670208 ps
CPU time 0.6 seconds
Started Jul 24 05:16:51 PM PDT 24
Finished Jul 24 05:16:52 PM PDT 24
Peak memory 194984 kb
Host smart-0e2d5acd-a2d9-480f-a569-abc345672cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952064630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2952064630
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3267271314
Short name T82
Test name
Test status
Simulation time 20686393 ps
CPU time 0.67 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 195616 kb
Host smart-84409ae9-24dd-467f-993d-6e9755910787
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267271314 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3267271314
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.215778344
Short name T820
Test name
Test status
Simulation time 302805400 ps
CPU time 1.13 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 198336 kb
Host smart-d7cc2d08-485a-4bf6-a68d-dde0adeb0c8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215778344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.215778344
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.431689507
Short name T31
Test name
Test status
Simulation time 70896993 ps
CPU time 1.12 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 198328 kb
Host smart-03b08759-2040-4007-ae92-b3ae84b658a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431689507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.431689507
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1475854911
Short name T79
Test name
Test status
Simulation time 26340699 ps
CPU time 0.74 seconds
Started Jul 24 05:13:53 PM PDT 24
Finished Jul 24 05:13:54 PM PDT 24
Peak memory 196852 kb
Host smart-9dbba7fe-318d-4447-8a2b-eb981f098f5e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475854911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1475854911
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.669588063
Short name T95
Test name
Test status
Simulation time 1242910105 ps
CPU time 3.19 seconds
Started Jul 24 05:13:50 PM PDT 24
Finished Jul 24 05:13:53 PM PDT 24
Peak memory 196932 kb
Host smart-75b14bfb-e3c4-4dfd-ac18-164a354287ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669588063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.669588063
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.874345542
Short name T78
Test name
Test status
Simulation time 67706469 ps
CPU time 0.63 seconds
Started Jul 24 05:13:57 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 195120 kb
Host smart-34fa10c7-9112-469c-a02e-4944f98bcd2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874345542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.874345542
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2784433819
Short name T784
Test name
Test status
Simulation time 78610699 ps
CPU time 0.87 seconds
Started Jul 24 05:13:54 PM PDT 24
Finished Jul 24 05:13:55 PM PDT 24
Peak memory 198140 kb
Host smart-b4c82c68-aaa0-45c1-84de-48c68b548f86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784433819 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2784433819
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2778423818
Short name T823
Test name
Test status
Simulation time 52538358 ps
CPU time 0.61 seconds
Started Jul 24 05:13:54 PM PDT 24
Finished Jul 24 05:13:55 PM PDT 24
Peak memory 195596 kb
Host smart-67cfbd87-d461-4423-9612-7b8b4be17ea4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778423818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2778423818
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3706611885
Short name T808
Test name
Test status
Simulation time 14665757 ps
CPU time 0.58 seconds
Started Jul 24 05:13:50 PM PDT 24
Finished Jul 24 05:13:51 PM PDT 24
Peak memory 194672 kb
Host smart-b79f137e-e182-4a50-902c-7ef6b9a3333e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706611885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3706611885
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3593688216
Short name T756
Test name
Test status
Simulation time 129675439 ps
CPU time 0.74 seconds
Started Jul 24 05:13:47 PM PDT 24
Finished Jul 24 05:13:48 PM PDT 24
Peak memory 196428 kb
Host smart-461d5dfb-029d-47d7-84e0-07c9827cb38f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593688216 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3593688216
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3494825576
Short name T814
Test name
Test status
Simulation time 453551312 ps
CPU time 1.93 seconds
Started Jul 24 05:13:50 PM PDT 24
Finished Jul 24 05:13:52 PM PDT 24
Peak memory 198312 kb
Host smart-0d32be7f-5468-471d-bfc4-e90b863954bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494825576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3494825576
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1306798647
Short name T29
Test name
Test status
Simulation time 46177534 ps
CPU time 0.88 seconds
Started Jul 24 05:13:54 PM PDT 24
Finished Jul 24 05:13:55 PM PDT 24
Peak memory 197392 kb
Host smart-91ba309b-7f19-488d-b396-5c3ea2d4ff5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306798647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1306798647
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3911930280
Short name T80
Test name
Test status
Simulation time 52285912 ps
CPU time 0.73 seconds
Started Jul 24 05:13:53 PM PDT 24
Finished Jul 24 05:13:54 PM PDT 24
Peak memory 196324 kb
Host smart-7e6f9872-115c-4a9b-96ba-2ee84bfeebe1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911930280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3911930280
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3963206260
Short name T69
Test name
Test status
Simulation time 79432446 ps
CPU time 2.89 seconds
Started Jul 24 05:14:01 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 196936 kb
Host smart-28788db6-7d87-4afd-842f-a2e108d3ad7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963206260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3963206260
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2007480940
Short name T844
Test name
Test status
Simulation time 18263549 ps
CPU time 0.67 seconds
Started Jul 24 05:13:58 PM PDT 24
Finished Jul 24 05:13:59 PM PDT 24
Peak memory 195836 kb
Host smart-d08a51c6-2375-46d6-8677-6d3c8d85d225
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007480940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2007480940
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1305214671
Short name T778
Test name
Test status
Simulation time 12686470 ps
CPU time 0.68 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:03 PM PDT 24
Peak memory 197736 kb
Host smart-1135c079-4660-4085-b0ad-8db049bd24fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305214671 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1305214671
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1800731573
Short name T74
Test name
Test status
Simulation time 92549397 ps
CPU time 0.6 seconds
Started Jul 24 05:13:57 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 195808 kb
Host smart-271942fa-0acd-4647-8fc1-31d4054e6ce3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800731573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1800731573
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1806242559
Short name T846
Test name
Test status
Simulation time 11333194 ps
CPU time 0.56 seconds
Started Jul 24 05:13:51 PM PDT 24
Finished Jul 24 05:13:52 PM PDT 24
Peak memory 194016 kb
Host smart-d66e38de-ea00-42c9-9aa8-cafd70a0a8a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806242559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1806242559
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3862031634
Short name T760
Test name
Test status
Simulation time 71214199 ps
CPU time 0.82 seconds
Started Jul 24 05:14:09 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 196460 kb
Host smart-ddb93aea-c53c-4815-b2c8-d4243f3b57e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862031634 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3862031634
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2417287954
Short name T803
Test name
Test status
Simulation time 96396797 ps
CPU time 1.22 seconds
Started Jul 24 05:13:56 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 198096 kb
Host smart-e0cecfd5-5bce-4894-a5e8-84fe141da1b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417287954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2417287954
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3005551006
Short name T30
Test name
Test status
Simulation time 463845434 ps
CPU time 1.4 seconds
Started Jul 24 05:13:51 PM PDT 24
Finished Jul 24 05:13:52 PM PDT 24
Peak memory 198408 kb
Host smart-6a7e09a9-d278-40f2-b4d8-18f28533e1fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005551006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3005551006
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4090942890
Short name T817
Test name
Test status
Simulation time 33762972 ps
CPU time 0.83 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 198256 kb
Host smart-1412a366-35a2-432e-8507-19413a1ee705
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090942890 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.4090942890
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3528386730
Short name T831
Test name
Test status
Simulation time 12298424 ps
CPU time 0.61 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 195500 kb
Host smart-0e8e0f69-9bb6-49c5-8af3-ab57432acf86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528386730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3528386730
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.929986422
Short name T798
Test name
Test status
Simulation time 43771682 ps
CPU time 0.64 seconds
Started Jul 24 05:14:01 PM PDT 24
Finished Jul 24 05:14:01 PM PDT 24
Peak memory 194016 kb
Host smart-233b7aa7-b124-4ca8-8cb2-620a46cf9405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929986422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.929986422
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3981116363
Short name T746
Test name
Test status
Simulation time 89105231 ps
CPU time 1.98 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 198384 kb
Host smart-63806afb-9b3d-4dd0-bbde-5b3a1e9cac4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981116363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3981116363
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.341247371
Short name T845
Test name
Test status
Simulation time 13442669 ps
CPU time 0.69 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:11 PM PDT 24
Peak memory 198160 kb
Host smart-abf12aa4-8984-46c9-b9cc-d3e4556e2e1c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341247371 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.341247371
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1022282584
Short name T72
Test name
Test status
Simulation time 14200510 ps
CPU time 0.6 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 193972 kb
Host smart-a55c7959-42ed-4933-9e55-5e880444bc13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022282584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1022282584
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3877559347
Short name T731
Test name
Test status
Simulation time 61764563 ps
CPU time 0.61 seconds
Started Jul 24 05:14:00 PM PDT 24
Finished Jul 24 05:14:01 PM PDT 24
Peak memory 194152 kb
Host smart-f6eed575-6a53-4425-92d2-76c1fc33a451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877559347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3877559347
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.210037365
Short name T81
Test name
Test status
Simulation time 137957680 ps
CPU time 0.72 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:03 PM PDT 24
Peak memory 196048 kb
Host smart-7b41a99f-732f-442f-896b-51915aab1593
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210037365 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.210037365
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2242333193
Short name T747
Test name
Test status
Simulation time 158173794 ps
CPU time 0.94 seconds
Started Jul 24 05:13:59 PM PDT 24
Finished Jul 24 05:14:00 PM PDT 24
Peak memory 198140 kb
Host smart-3ce16a6d-bce7-463b-96dd-7ad904b6133a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242333193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2242333193
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2737384720
Short name T839
Test name
Test status
Simulation time 50454583 ps
CPU time 0.88 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 198064 kb
Host smart-bc238e42-6083-4b21-95f4-2207d500948f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737384720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2737384720
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3540267941
Short name T847
Test name
Test status
Simulation time 91950980 ps
CPU time 1.28 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:08 PM PDT 24
Peak memory 198456 kb
Host smart-e6e8bdda-3d46-4f7d-be7b-56c4adcf4cd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540267941 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3540267941
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1670552506
Short name T751
Test name
Test status
Simulation time 74242055 ps
CPU time 0.62 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:08 PM PDT 24
Peak memory 194736 kb
Host smart-23eebd40-3809-4796-a182-1c2f15eba4a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670552506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1670552506
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3650728194
Short name T771
Test name
Test status
Simulation time 82620295 ps
CPU time 0.58 seconds
Started Jul 24 05:14:00 PM PDT 24
Finished Jul 24 05:14:01 PM PDT 24
Peak memory 194088 kb
Host smart-15714c74-8f36-47bf-8a15-e42d11771b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650728194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3650728194
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2612956144
Short name T71
Test name
Test status
Simulation time 30717196 ps
CPU time 0.64 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 194964 kb
Host smart-f0f6bc79-5a60-468a-83eb-b713239c06fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612956144 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2612956144
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2808576132
Short name T726
Test name
Test status
Simulation time 66328279 ps
CPU time 1.76 seconds
Started Jul 24 05:13:56 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 198124 kb
Host smart-61cdc599-7e9b-4867-9bb1-a26f8255f64a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808576132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2808576132
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3999549217
Short name T40
Test name
Test status
Simulation time 116105955 ps
CPU time 1.13 seconds
Started Jul 24 05:13:57 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 198328 kb
Host smart-fa5612ce-ee04-45f2-b614-9c8619b77199
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999549217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3999549217
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2699720051
Short name T801
Test name
Test status
Simulation time 112451050 ps
CPU time 0.97 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 198244 kb
Host smart-122e1ca3-7e84-4583-9e8b-c93c53be448d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699720051 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2699720051
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4232340358
Short name T94
Test name
Test status
Simulation time 18373308 ps
CPU time 0.63 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:06 PM PDT 24
Peak memory 195748 kb
Host smart-795cd0b2-226f-46d8-827c-4609f391d025
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232340358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4232340358
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2143197316
Short name T822
Test name
Test status
Simulation time 35978455 ps
CPU time 0.6 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:03 PM PDT 24
Peak memory 194048 kb
Host smart-f5cd5295-c667-4d49-82b1-7e819323b9c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143197316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2143197316
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3590867007
Short name T83
Test name
Test status
Simulation time 16743612 ps
CPU time 0.78 seconds
Started Jul 24 05:13:59 PM PDT 24
Finished Jul 24 05:14:00 PM PDT 24
Peak memory 197160 kb
Host smart-9e437236-f5f2-4376-ade3-988950db411e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590867007 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3590867007
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3227311135
Short name T819
Test name
Test status
Simulation time 486080824 ps
CPU time 2.48 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:08 PM PDT 24
Peak memory 198324 kb
Host smart-2afb9be0-f787-49c5-849d-3cc7358d18fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227311135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3227311135
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2590543826
Short name T41
Test name
Test status
Simulation time 266183831 ps
CPU time 1.11 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 197840 kb
Host smart-75cfb379-e52b-4a37-8d49-028343ddb082
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590543826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2590543826
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1029797603
Short name T733
Test name
Test status
Simulation time 18921316 ps
CPU time 0.71 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 197424 kb
Host smart-6241a489-464d-4914-a9bd-d4f252af9f87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029797603 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1029797603
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2931337542
Short name T73
Test name
Test status
Simulation time 31364400 ps
CPU time 0.6 seconds
Started Jul 24 05:14:01 PM PDT 24
Finished Jul 24 05:14:02 PM PDT 24
Peak memory 195016 kb
Host smart-18b97a50-b430-45e5-9bbb-ad166dc8afd0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931337542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2931337542
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4148649654
Short name T807
Test name
Test status
Simulation time 16247425 ps
CPU time 0.56 seconds
Started Jul 24 05:13:57 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 194644 kb
Host smart-b02db1bb-f22c-4320-952f-8a457beb52be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148649654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4148649654
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3258589668
Short name T786
Test name
Test status
Simulation time 20217881 ps
CPU time 0.82 seconds
Started Jul 24 05:14:32 PM PDT 24
Finished Jul 24 05:14:34 PM PDT 24
Peak memory 196616 kb
Host smart-20bd9189-78a0-4600-af47-3764caadcf28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258589668 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3258589668
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.21274641
Short name T848
Test name
Test status
Simulation time 159120877 ps
CPU time 2.65 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 198388 kb
Host smart-57327883-8685-418c-aea5-4aa24ca5b811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21274641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.21274641
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1774351900
Short name T766
Test name
Test status
Simulation time 111490336 ps
CPU time 0.72 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:03 PM PDT 24
Peak memory 197504 kb
Host smart-fa173c2e-02a9-490c-836a-7399cf02f314
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774351900 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1774351900
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.26352105
Short name T828
Test name
Test status
Simulation time 18052243 ps
CPU time 0.57 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:06 PM PDT 24
Peak memory 193576 kb
Host smart-c4c3db93-f665-41a8-990c-14e823f63088
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26352105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_
csr_rw.26352105
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2917799190
Short name T829
Test name
Test status
Simulation time 23821573 ps
CPU time 0.57 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 194196 kb
Host smart-5646627f-1d19-47f3-98b6-868e896b818e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917799190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2917799190
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.210854239
Short name T806
Test name
Test status
Simulation time 149106888 ps
CPU time 0.87 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:12 PM PDT 24
Peak memory 197180 kb
Host smart-ad8727f5-4dcf-4d81-95cb-cecab02817df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210854239 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.210854239
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2630202541
Short name T740
Test name
Test status
Simulation time 42862508 ps
CPU time 2.08 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 198384 kb
Host smart-62d617ea-6ba5-4de6-ab28-1352254b0111
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630202541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2630202541
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1893698703
Short name T742
Test name
Test status
Simulation time 432709846 ps
CPU time 1.44 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 198372 kb
Host smart-6c6f836b-f18a-49a1-9860-1bf6fba3f3f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893698703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1893698703
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.776405371
Short name T791
Test name
Test status
Simulation time 43069531 ps
CPU time 0.76 seconds
Started Jul 24 05:14:06 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 198196 kb
Host smart-611acac8-9722-46a1-9376-80c2a8dc9888
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776405371 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.776405371
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.980397959
Short name T818
Test name
Test status
Simulation time 66353764 ps
CPU time 0.58 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 194180 kb
Host smart-b8473d55-bdcc-4de6-953c-abf928e84d4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980397959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.980397959
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.672664333
Short name T825
Test name
Test status
Simulation time 46740595 ps
CPU time 0.57 seconds
Started Jul 24 05:14:13 PM PDT 24
Finished Jul 24 05:14:14 PM PDT 24
Peak memory 194020 kb
Host smart-47fda595-001c-4941-93cb-870d0ec2249b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672664333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.672664333
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2347578399
Short name T826
Test name
Test status
Simulation time 36481919 ps
CPU time 0.79 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:11 PM PDT 24
Peak memory 196668 kb
Host smart-31f97e78-48c6-406a-8d71-e6e459118ad6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347578399 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2347578399
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3559364660
Short name T796
Test name
Test status
Simulation time 37305394 ps
CPU time 1.92 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:12 PM PDT 24
Peak memory 198372 kb
Host smart-cb653fc9-1f44-42b6-8810-d8815fd6cdb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559364660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3559364660
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.309541292
Short name T787
Test name
Test status
Simulation time 167914453 ps
CPU time 0.87 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:06 PM PDT 24
Peak memory 197280 kb
Host smart-b54aa7ad-bc96-45d4-85ba-6e3eb1e9a814
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309541292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.309541292
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.819773677
Short name T722
Test name
Test status
Simulation time 32603156 ps
CPU time 0.92 seconds
Started Jul 24 05:14:17 PM PDT 24
Finished Jul 24 05:14:18 PM PDT 24
Peak memory 198096 kb
Host smart-c999c781-a794-4fd8-b89a-08f3a80bebe6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819773677 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.819773677
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4094698238
Short name T792
Test name
Test status
Simulation time 15090600 ps
CPU time 0.56 seconds
Started Jul 24 05:14:06 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 195208 kb
Host smart-4aeb66f8-bf4a-4ea4-a02c-02d8fdb1ff6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094698238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4094698238
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2632856632
Short name T768
Test name
Test status
Simulation time 16712431 ps
CPU time 0.65 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 194084 kb
Host smart-677712c5-0e7b-4a69-9e3a-6a8489042451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632856632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2632856632
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2809987104
Short name T834
Test name
Test status
Simulation time 33689219 ps
CPU time 0.69 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 195964 kb
Host smart-16a68b68-307d-4f1e-91d2-0c98d5d469f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809987104 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2809987104
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3678390400
Short name T728
Test name
Test status
Simulation time 168334188 ps
CPU time 1.54 seconds
Started Jul 24 05:14:15 PM PDT 24
Finished Jul 24 05:14:16 PM PDT 24
Peak memory 198432 kb
Host smart-d1845f02-9dd9-4f69-b1fc-9e942a1a7841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678390400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3678390400
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1767761607
Short name T809
Test name
Test status
Simulation time 272555132 ps
CPU time 1.15 seconds
Started Jul 24 05:14:09 PM PDT 24
Finished Jul 24 05:14:11 PM PDT 24
Peak memory 198364 kb
Host smart-caa29f68-48f5-4706-b2be-d6cffb7abeca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767761607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1767761607
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3782296709
Short name T835
Test name
Test status
Simulation time 130051636 ps
CPU time 0.9 seconds
Started Jul 24 05:14:11 PM PDT 24
Finished Jul 24 05:14:12 PM PDT 24
Peak memory 198236 kb
Host smart-8f3f2f9f-66fe-43a1-8a80-d2e9cfc6a52f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782296709 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3782296709
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2783969848
Short name T66
Test name
Test status
Simulation time 45061379 ps
CPU time 0.67 seconds
Started Jul 24 05:14:13 PM PDT 24
Finished Jul 24 05:14:13 PM PDT 24
Peak memory 195068 kb
Host smart-519cdb68-eee1-43ab-840e-70f77f7e7582
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783969848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2783969848
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2279312625
Short name T721
Test name
Test status
Simulation time 14223955 ps
CPU time 0.56 seconds
Started Jul 24 05:13:58 PM PDT 24
Finished Jul 24 05:13:59 PM PDT 24
Peak memory 194612 kb
Host smart-a5f570ba-cbef-439b-bdec-6661acc9667c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279312625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2279312625
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1675316939
Short name T86
Test name
Test status
Simulation time 66363886 ps
CPU time 0.79 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 196708 kb
Host smart-c6eb7f03-3989-4e9b-b08b-6e1e514ca9a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675316939 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1675316939
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1855132628
Short name T842
Test name
Test status
Simulation time 108974842 ps
CPU time 2.21 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 198452 kb
Host smart-c8a0025a-e132-4962-95eb-637a545a35b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855132628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1855132628
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3905277150
Short name T800
Test name
Test status
Simulation time 30759251 ps
CPU time 0.84 seconds
Started Jul 24 05:13:54 PM PDT 24
Finished Jul 24 05:13:55 PM PDT 24
Peak memory 198140 kb
Host smart-73903d70-b001-4606-baa0-13ec40de1b3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905277150 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3905277150
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2589657892
Short name T76
Test name
Test status
Simulation time 19178119 ps
CPU time 0.58 seconds
Started Jul 24 05:14:15 PM PDT 24
Finished Jul 24 05:14:16 PM PDT 24
Peak memory 193932 kb
Host smart-06b477e1-8e7a-4e8b-8ef6-98fc86f203b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589657892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2589657892
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2314765202
Short name T727
Test name
Test status
Simulation time 14473844 ps
CPU time 0.57 seconds
Started Jul 24 05:14:16 PM PDT 24
Finished Jul 24 05:14:16 PM PDT 24
Peak memory 194096 kb
Host smart-0d723a84-0448-41fb-bde1-4b3180d41bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314765202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2314765202
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2451861848
Short name T64
Test name
Test status
Simulation time 211860253 ps
CPU time 0.8 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 196668 kb
Host smart-545e6265-38b7-4988-8bcd-9d90c923becc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451861848 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2451861848
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1517915765
Short name T725
Test name
Test status
Simulation time 134567155 ps
CPU time 1.54 seconds
Started Jul 24 05:14:13 PM PDT 24
Finished Jul 24 05:14:15 PM PDT 24
Peak memory 198432 kb
Host smart-950ef716-c5dc-405f-a474-809f3bee3688
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517915765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1517915765
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3928648989
Short name T775
Test name
Test status
Simulation time 65991083 ps
CPU time 0.82 seconds
Started Jul 24 05:13:57 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 198160 kb
Host smart-e2920dd1-132f-47fc-bfd9-f18f07475722
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928648989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3928648989
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1452541782
Short name T68
Test name
Test status
Simulation time 19778572 ps
CPU time 0.82 seconds
Started Jul 24 05:13:50 PM PDT 24
Finished Jul 24 05:13:51 PM PDT 24
Peak memory 196408 kb
Host smart-b28c8eed-76ff-45fc-9320-a77bb8614736
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452541782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1452541782
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2802609265
Short name T805
Test name
Test status
Simulation time 1025983395 ps
CPU time 3.29 seconds
Started Jul 24 05:13:58 PM PDT 24
Finished Jul 24 05:14:01 PM PDT 24
Peak memory 197404 kb
Host smart-d8bf54e4-8030-43da-9533-e07dc9179906
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802609265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2802609265
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3696041096
Short name T752
Test name
Test status
Simulation time 119851439 ps
CPU time 0.84 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 198276 kb
Host smart-86a36f82-b99b-4ee2-a8b7-fad23103b2cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696041096 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3696041096
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1673247956
Short name T790
Test name
Test status
Simulation time 33633321 ps
CPU time 0.63 seconds
Started Jul 24 05:13:54 PM PDT 24
Finished Jul 24 05:13:54 PM PDT 24
Peak memory 195228 kb
Host smart-dc74b323-29b6-47a5-b542-50fec8dbdcae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673247956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1673247956
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2279388212
Short name T795
Test name
Test status
Simulation time 28530666 ps
CPU time 0.58 seconds
Started Jul 24 05:13:56 PM PDT 24
Finished Jul 24 05:13:56 PM PDT 24
Peak memory 194088 kb
Host smart-590bcaa8-33cc-492f-8620-2ee8a8acd015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279388212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2279388212
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3370170589
Short name T774
Test name
Test status
Simulation time 15730289 ps
CPU time 0.65 seconds
Started Jul 24 05:13:58 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 195052 kb
Host smart-4ebd9c93-084f-4652-bd4d-f895a43ca70c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370170589 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3370170589
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1527939242
Short name T811
Test name
Test status
Simulation time 2235434688 ps
CPU time 2.4 seconds
Started Jul 24 05:13:58 PM PDT 24
Finished Jul 24 05:14:01 PM PDT 24
Peak memory 198396 kb
Host smart-6b5dad27-8222-4c36-a045-aa396f3a7201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527939242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1527939242
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.697792337
Short name T769
Test name
Test status
Simulation time 137145455 ps
CPU time 0.86 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:08 PM PDT 24
Peak memory 197564 kb
Host smart-399d3bff-ae5b-4bf6-83ba-b190ecea1afd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697792337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.697792337
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.153213051
Short name T767
Test name
Test status
Simulation time 30047515 ps
CPU time 0.6 seconds
Started Jul 24 05:14:06 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 194096 kb
Host smart-40d63d90-e34e-4e2b-b953-50459cfaad4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153213051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.153213051
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.737694300
Short name T729
Test name
Test status
Simulation time 36369043 ps
CPU time 0.56 seconds
Started Jul 24 05:14:14 PM PDT 24
Finished Jul 24 05:14:15 PM PDT 24
Peak memory 193860 kb
Host smart-a638053d-7edb-4b47-b274-aee76efad449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737694300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.737694300
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3716784275
Short name T777
Test name
Test status
Simulation time 14070457 ps
CPU time 0.58 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:03 PM PDT 24
Peak memory 193932 kb
Host smart-f9b6678b-67bc-44f1-8aa3-c8f1b599a35f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716784275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3716784275
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2114442339
Short name T782
Test name
Test status
Simulation time 32085494 ps
CPU time 0.56 seconds
Started Jul 24 05:14:17 PM PDT 24
Finished Jul 24 05:14:17 PM PDT 24
Peak memory 194020 kb
Host smart-332e5cbe-53cf-4b65-84fc-fe1f6e82faf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114442339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2114442339
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1660732116
Short name T840
Test name
Test status
Simulation time 36943108 ps
CPU time 0.59 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 194056 kb
Host smart-33a1efbe-1081-4c18-a532-1edc80b9314d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660732116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1660732116
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2164892173
Short name T793
Test name
Test status
Simulation time 14677568 ps
CPU time 0.65 seconds
Started Jul 24 05:14:06 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 194656 kb
Host smart-78486091-7e70-4cbe-b87d-b09aa0c24766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164892173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2164892173
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3702297753
Short name T754
Test name
Test status
Simulation time 15544303 ps
CPU time 0.58 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 194240 kb
Host smart-4d6a5388-7f16-4692-b1ad-3cf1af05cdca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702297753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3702297753
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1534025027
Short name T788
Test name
Test status
Simulation time 75954524 ps
CPU time 0.56 seconds
Started Jul 24 05:14:26 PM PDT 24
Finished Jul 24 05:14:26 PM PDT 24
Peak memory 194592 kb
Host smart-cb63aceb-f059-42e1-a7e5-16227a0cbf40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534025027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1534025027
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.461589222
Short name T812
Test name
Test status
Simulation time 66935631 ps
CPU time 0.57 seconds
Started Jul 24 05:14:06 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 193992 kb
Host smart-279f1335-2ea4-4940-bd4c-42ff282461cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461589222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.461589222
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2058495289
Short name T738
Test name
Test status
Simulation time 29920029 ps
CPU time 0.58 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:06 PM PDT 24
Peak memory 193936 kb
Host smart-2847e6a3-7de6-4263-b2ae-d368606ac076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058495289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2058495289
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1729355156
Short name T75
Test name
Test status
Simulation time 66291888 ps
CPU time 0.82 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:06 PM PDT 24
Peak memory 196320 kb
Host smart-19a96d0e-6a23-4fdc-b57f-e1885362611a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729355156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1729355156
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4160326997
Short name T737
Test name
Test status
Simulation time 2107730267 ps
CPU time 2.34 seconds
Started Jul 24 05:13:54 PM PDT 24
Finished Jul 24 05:13:57 PM PDT 24
Peak memory 198344 kb
Host smart-18ec6e72-2b7f-4a41-a8eb-6b434e931682
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160326997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4160326997
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3795073395
Short name T77
Test name
Test status
Simulation time 90824544 ps
CPU time 0.64 seconds
Started Jul 24 05:14:16 PM PDT 24
Finished Jul 24 05:14:16 PM PDT 24
Peak memory 196072 kb
Host smart-68fa18e2-bb74-470d-8b91-24d06e69ebf4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795073395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3795073395
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4011390741
Short name T720
Test name
Test status
Simulation time 29081012 ps
CPU time 0.73 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 198140 kb
Host smart-eaf76c8b-d069-4ffa-8f22-16384be71f47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011390741 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4011390741
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1135821063
Short name T762
Test name
Test status
Simulation time 72073387 ps
CPU time 0.6 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 194984 kb
Host smart-9fff40ad-6545-4fe6-8fd8-e3c53725ce0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135821063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1135821063
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.517536613
Short name T781
Test name
Test status
Simulation time 15060773 ps
CPU time 0.6 seconds
Started Jul 24 05:13:58 PM PDT 24
Finished Jul 24 05:13:59 PM PDT 24
Peak memory 194056 kb
Host smart-d637ce23-bfe3-47e5-b42c-4764ac78cba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517536613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.517536613
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2507414254
Short name T84
Test name
Test status
Simulation time 40201586 ps
CPU time 0.9 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 197252 kb
Host smart-5fcb3ede-9267-44b1-886a-1b482df84d5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507414254 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2507414254
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.821653217
Short name T730
Test name
Test status
Simulation time 494165639 ps
CPU time 2.57 seconds
Started Jul 24 05:13:56 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 198284 kb
Host smart-c0b2d60b-090d-4da5-a66d-a381c1c67d41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821653217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.821653217
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.49949293
Short name T770
Test name
Test status
Simulation time 117106101 ps
CPU time 1.44 seconds
Started Jul 24 05:14:00 PM PDT 24
Finished Jul 24 05:14:02 PM PDT 24
Peak memory 198368 kb
Host smart-e19aa387-6e57-4ddf-b819-09e02b6de64d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49949293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_tl_intg_err.49949293
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4168348510
Short name T830
Test name
Test status
Simulation time 37692784 ps
CPU time 0.57 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 193984 kb
Host smart-a777f6a0-bb0f-468b-bb20-52e58e78aa82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168348510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4168348510
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1725103316
Short name T849
Test name
Test status
Simulation time 49118233 ps
CPU time 0.64 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 194104 kb
Host smart-98a06dd8-c2bf-4b9e-94c3-f9dda62e600e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725103316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1725103316
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1150176875
Short name T750
Test name
Test status
Simulation time 50165802 ps
CPU time 0.67 seconds
Started Jul 24 05:13:57 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 194040 kb
Host smart-5cef1637-cd7d-453b-93da-8a6990709819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150176875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1150176875
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3827908454
Short name T724
Test name
Test status
Simulation time 21436146 ps
CPU time 0.61 seconds
Started Jul 24 05:14:13 PM PDT 24
Finished Jul 24 05:14:14 PM PDT 24
Peak memory 194092 kb
Host smart-a4676b4b-052d-4219-bd3d-d1aec994765a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827908454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3827908454
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2778963057
Short name T744
Test name
Test status
Simulation time 76844928 ps
CPU time 0.59 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:11 PM PDT 24
Peak memory 194084 kb
Host smart-9cbb2237-98a3-44df-9251-761926184721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778963057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2778963057
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.4251021939
Short name T763
Test name
Test status
Simulation time 18081702 ps
CPU time 0.61 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 194088 kb
Host smart-a83441f3-37c0-43a4-a118-4ccd590c1673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251021939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.4251021939
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2912431373
Short name T833
Test name
Test status
Simulation time 21271382 ps
CPU time 0.57 seconds
Started Jul 24 05:14:11 PM PDT 24
Finished Jul 24 05:14:11 PM PDT 24
Peak memory 194048 kb
Host smart-103646b6-73d8-45fa-8638-fd1456cadb42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912431373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2912431373
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3837974346
Short name T789
Test name
Test status
Simulation time 32465897 ps
CPU time 0.58 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 194700 kb
Host smart-2e139121-967f-4a83-a0f9-e8bc6cfe2fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837974346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3837974346
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3764368395
Short name T836
Test name
Test status
Simulation time 16532853 ps
CPU time 0.62 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:11 PM PDT 24
Peak memory 194756 kb
Host smart-721ba5ac-3153-4e9c-83b0-fe24213d95d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764368395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3764368395
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1159419280
Short name T765
Test name
Test status
Simulation time 18317150 ps
CPU time 0.62 seconds
Started Jul 24 05:14:12 PM PDT 24
Finished Jul 24 05:14:13 PM PDT 24
Peak memory 194096 kb
Host smart-bd5983fa-f247-40ed-bee2-54b91d5b1a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159419280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1159419280
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.4190925161
Short name T758
Test name
Test status
Simulation time 213229178 ps
CPU time 0.85 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:06 PM PDT 24
Peak memory 196344 kb
Host smart-9ae637b4-3eec-4531-a61d-2d725968e483
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190925161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.4190925161
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.754198395
Short name T734
Test name
Test status
Simulation time 94760814 ps
CPU time 1.41 seconds
Started Jul 24 05:14:00 PM PDT 24
Finished Jul 24 05:14:01 PM PDT 24
Peak memory 197076 kb
Host smart-31f4159f-8193-4825-b4a3-1ac3ab2b5e31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754198395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.754198395
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4124559732
Short name T773
Test name
Test status
Simulation time 16980203 ps
CPU time 0.64 seconds
Started Jul 24 05:14:00 PM PDT 24
Finished Jul 24 05:14:01 PM PDT 24
Peak memory 195036 kb
Host smart-2ef46d1c-38fa-42f6-9ad5-4e02b2dbc0a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124559732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.4124559732
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3928604429
Short name T759
Test name
Test status
Simulation time 22698124 ps
CPU time 0.68 seconds
Started Jul 24 05:13:49 PM PDT 24
Finished Jul 24 05:13:50 PM PDT 24
Peak memory 198124 kb
Host smart-f4ac7328-d453-445c-b294-62c99d3dfafc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928604429 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3928604429
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4115164093
Short name T799
Test name
Test status
Simulation time 23740665 ps
CPU time 0.58 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:03 PM PDT 24
Peak memory 193548 kb
Host smart-a93c85c7-6543-4f22-a824-3336afdb944a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115164093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.4115164093
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.798965353
Short name T745
Test name
Test status
Simulation time 39649938 ps
CPU time 0.64 seconds
Started Jul 24 05:13:53 PM PDT 24
Finished Jul 24 05:13:54 PM PDT 24
Peak memory 194784 kb
Host smart-21dc1e97-1db7-4410-983f-40677298d5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798965353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.798965353
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2613593974
Short name T63
Test name
Test status
Simulation time 109958184 ps
CPU time 0.71 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 195240 kb
Host smart-7a872033-209e-4bba-9503-12f4af1ee948
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613593974 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2613593974
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.381730598
Short name T802
Test name
Test status
Simulation time 128362590 ps
CPU time 2.59 seconds
Started Jul 24 05:13:58 PM PDT 24
Finished Jul 24 05:14:00 PM PDT 24
Peak memory 198228 kb
Host smart-7cb89a93-b3e5-4514-b916-285642c3751e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381730598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.381730598
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1916957245
Short name T96
Test name
Test status
Simulation time 157191673 ps
CPU time 1.22 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 198388 kb
Host smart-8c205348-a1f0-46e4-9847-ea9296f114ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916957245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1916957245
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2854057491
Short name T794
Test name
Test status
Simulation time 14222241 ps
CPU time 0.59 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 194008 kb
Host smart-a2735e2f-c6f5-43a1-b86f-2de0af2e21ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854057491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2854057491
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1102056839
Short name T815
Test name
Test status
Simulation time 11687082 ps
CPU time 0.6 seconds
Started Jul 24 05:14:12 PM PDT 24
Finished Jul 24 05:14:13 PM PDT 24
Peak memory 193936 kb
Host smart-fcf3ecf7-9037-4c7a-b086-e7146ec32570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102056839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1102056839
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3713642135
Short name T827
Test name
Test status
Simulation time 17959961 ps
CPU time 0.6 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:11 PM PDT 24
Peak memory 193684 kb
Host smart-d19c3e26-d114-445e-8dde-6e49549e0537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713642135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3713642135
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4151243345
Short name T797
Test name
Test status
Simulation time 20690225 ps
CPU time 0.56 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:03 PM PDT 24
Peak memory 194520 kb
Host smart-24a00ed1-2f02-4cdb-bc7e-857ae8dab067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151243345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4151243345
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1177498835
Short name T735
Test name
Test status
Simulation time 10993804 ps
CPU time 0.62 seconds
Started Jul 24 05:13:55 PM PDT 24
Finished Jul 24 05:13:56 PM PDT 24
Peak memory 194084 kb
Host smart-f517d707-9205-46e3-b490-f75924973582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177498835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1177498835
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2274621363
Short name T755
Test name
Test status
Simulation time 15259972 ps
CPU time 0.66 seconds
Started Jul 24 05:14:11 PM PDT 24
Finished Jul 24 05:14:12 PM PDT 24
Peak memory 194772 kb
Host smart-5bfb625a-adcb-4e8d-a83a-4deca20d6ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274621363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2274621363
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2989712507
Short name T739
Test name
Test status
Simulation time 13715748 ps
CPU time 0.56 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 194016 kb
Host smart-6ad5a89c-4f5d-4e44-bd03-2c432dac8476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989712507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2989712507
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.254452550
Short name T743
Test name
Test status
Simulation time 11210438 ps
CPU time 0.57 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 194668 kb
Host smart-7d827d59-b193-4c08-bc72-70bfff2be851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254452550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.254452550
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3650352474
Short name T749
Test name
Test status
Simulation time 44760875 ps
CPU time 0.59 seconds
Started Jul 24 05:14:11 PM PDT 24
Finished Jul 24 05:14:12 PM PDT 24
Peak memory 194036 kb
Host smart-b13ab278-94c0-4f15-b63a-2794c348a43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650352474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3650352474
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3874591674
Short name T813
Test name
Test status
Simulation time 13204184 ps
CPU time 0.58 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 194612 kb
Host smart-c7cc9cf4-e643-4b0e-a498-69a0e884f3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874591674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3874591674
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.959745595
Short name T843
Test name
Test status
Simulation time 147595387 ps
CPU time 1.55 seconds
Started Jul 24 05:13:51 PM PDT 24
Finished Jul 24 05:13:53 PM PDT 24
Peak memory 195252 kb
Host smart-baa67964-4319-47db-b7e9-cd6e865ae60c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959745595 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.959745595
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.471805729
Short name T67
Test name
Test status
Simulation time 23448585 ps
CPU time 0.61 seconds
Started Jul 24 05:14:13 PM PDT 24
Finished Jul 24 05:14:13 PM PDT 24
Peak memory 195884 kb
Host smart-cbbd6ac7-3eb2-4c41-bd3a-f826e742f1a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471805729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.471805729
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2193452246
Short name T783
Test name
Test status
Simulation time 59337947 ps
CPU time 0.58 seconds
Started Jul 24 05:13:58 PM PDT 24
Finished Jul 24 05:13:59 PM PDT 24
Peak memory 193952 kb
Host smart-4bd5c392-f83a-45a1-b0b5-5a0d4527d3cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193452246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2193452246
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2765278388
Short name T841
Test name
Test status
Simulation time 29111642 ps
CPU time 0.75 seconds
Started Jul 24 05:13:59 PM PDT 24
Finished Jul 24 05:14:00 PM PDT 24
Peak memory 197228 kb
Host smart-be8acffb-9589-4ff5-a167-6a23cc7f2350
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765278388 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2765278388
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.611204458
Short name T816
Test name
Test status
Simulation time 91972849 ps
CPU time 1.19 seconds
Started Jul 24 05:13:55 PM PDT 24
Finished Jul 24 05:13:57 PM PDT 24
Peak memory 198392 kb
Host smart-89a519d1-8064-4288-b667-0214decc2f18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611204458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.611204458
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3174101579
Short name T821
Test name
Test status
Simulation time 154413244 ps
CPU time 1.13 seconds
Started Jul 24 05:14:06 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 198004 kb
Host smart-8df9a087-85d0-45a0-b150-f92b35a2d7b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174101579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3174101579
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1013239836
Short name T753
Test name
Test status
Simulation time 29595152 ps
CPU time 0.8 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:08 PM PDT 24
Peak memory 198200 kb
Host smart-8f89428e-4427-4eb9-96c8-2614e12f8f3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013239836 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1013239836
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2361737496
Short name T732
Test name
Test status
Simulation time 51322774 ps
CPU time 0.61 seconds
Started Jul 24 05:14:31 PM PDT 24
Finished Jul 24 05:14:31 PM PDT 24
Peak memory 194992 kb
Host smart-d2e2c389-e3f8-42ee-9c23-7c2d3018e28a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361737496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2361737496
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3071945805
Short name T804
Test name
Test status
Simulation time 14167154 ps
CPU time 0.54 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 193928 kb
Host smart-b38185d8-e041-44b7-865b-1f0a7f60dff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071945805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3071945805
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4261145061
Short name T757
Test name
Test status
Simulation time 18946547 ps
CPU time 0.64 seconds
Started Jul 24 05:13:52 PM PDT 24
Finished Jul 24 05:13:53 PM PDT 24
Peak memory 195016 kb
Host smart-55df2be6-e182-4bc2-aeed-1aed0f89c535
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261145061 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.4261145061
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.272764990
Short name T824
Test name
Test status
Simulation time 154037236 ps
CPU time 2.65 seconds
Started Jul 24 05:13:59 PM PDT 24
Finished Jul 24 05:14:02 PM PDT 24
Peak memory 198356 kb
Host smart-2f2ec5e5-421e-41ed-b057-6a98182a22af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272764990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.272764990
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1006419753
Short name T764
Test name
Test status
Simulation time 48182353 ps
CPU time 0.82 seconds
Started Jul 24 05:14:00 PM PDT 24
Finished Jul 24 05:14:01 PM PDT 24
Peak memory 198132 kb
Host smart-982f8d02-ba0d-433a-924b-ece3a8c8c77f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006419753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1006419753
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2805515137
Short name T741
Test name
Test status
Simulation time 157720723 ps
CPU time 0.81 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 198224 kb
Host smart-ae84e808-fbde-4947-9739-19ddcb3f634c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805515137 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2805515137
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.344357691
Short name T748
Test name
Test status
Simulation time 13975122 ps
CPU time 0.56 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:06 PM PDT 24
Peak memory 194260 kb
Host smart-37b02970-ca87-45fe-bb6d-efe430f7838c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344357691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.344357691
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1271496518
Short name T723
Test name
Test status
Simulation time 32050443 ps
CPU time 0.59 seconds
Started Jul 24 05:13:59 PM PDT 24
Finished Jul 24 05:13:59 PM PDT 24
Peak memory 194092 kb
Host smart-45b3ad0d-fa76-495e-b37e-f547f0d53bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271496518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1271496518
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.153285608
Short name T85
Test name
Test status
Simulation time 256618398 ps
CPU time 0.84 seconds
Started Jul 24 05:14:01 PM PDT 24
Finished Jul 24 05:14:02 PM PDT 24
Peak memory 196292 kb
Host smart-31a59060-b9a6-4dd8-8347-b64d89056eca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153285608 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.153285608
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4073414499
Short name T772
Test name
Test status
Simulation time 289388504 ps
CPU time 1.59 seconds
Started Jul 24 05:14:33 PM PDT 24
Finished Jul 24 05:14:35 PM PDT 24
Peak memory 198376 kb
Host smart-b4dbe9ec-3158-4724-8b3f-71646f8883d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073414499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.4073414499
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.671218310
Short name T838
Test name
Test status
Simulation time 160915779 ps
CPU time 0.87 seconds
Started Jul 24 05:13:53 PM PDT 24
Finished Jul 24 05:13:54 PM PDT 24
Peak memory 197552 kb
Host smart-b13a2a16-9307-46bd-b73e-493c3b6d24e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671218310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.671218310
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1700613916
Short name T810
Test name
Test status
Simulation time 159961114 ps
CPU time 1.59 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 198416 kb
Host smart-9dc20e57-1728-4c27-85f6-29dd18fc8bdc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700613916 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1700613916
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3167439188
Short name T837
Test name
Test status
Simulation time 21470898 ps
CPU time 0.64 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 195700 kb
Host smart-dc9143c7-06ba-4a59-902e-35c07ba52e31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167439188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3167439188
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3629748136
Short name T779
Test name
Test status
Simulation time 13879214 ps
CPU time 0.56 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 194044 kb
Host smart-4c745d95-4392-4b87-8986-5cbdd1b137f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629748136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3629748136
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1079490183
Short name T832
Test name
Test status
Simulation time 20483926 ps
CPU time 0.61 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:03 PM PDT 24
Peak memory 194936 kb
Host smart-1d5da72d-64a6-49f1-a3f6-303e24fd111c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079490183 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1079490183
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1200496039
Short name T785
Test name
Test status
Simulation time 129181659 ps
CPU time 2.16 seconds
Started Jul 24 05:14:02 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 198360 kb
Host smart-587a1583-cf2e-4842-84b8-9f0f1c4d494f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200496039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1200496039
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.726496113
Short name T39
Test name
Test status
Simulation time 120256360 ps
CPU time 1.47 seconds
Started Jul 24 05:13:56 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 198400 kb
Host smart-3d2ad424-d2d0-432c-84c8-940bd10bd2c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726496113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.726496113
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1974327542
Short name T776
Test name
Test status
Simulation time 145415034 ps
CPU time 1.18 seconds
Started Jul 24 05:13:57 PM PDT 24
Finished Jul 24 05:13:58 PM PDT 24
Peak memory 198304 kb
Host smart-fb323f40-7444-4316-8654-12072f473020
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974327542 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1974327542
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1063478709
Short name T736
Test name
Test status
Simulation time 31461452 ps
CPU time 0.58 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 195824 kb
Host smart-c65d21db-b108-4459-a0df-0bd2641deedb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063478709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1063478709
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2963639064
Short name T780
Test name
Test status
Simulation time 15824204 ps
CPU time 0.64 seconds
Started Jul 24 05:14:03 PM PDT 24
Finished Jul 24 05:14:04 PM PDT 24
Peak memory 193984 kb
Host smart-5b684544-1394-4585-9c26-0ce379d6f837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963639064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2963639064
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3306912360
Short name T65
Test name
Test status
Simulation time 49826396 ps
CPU time 0.73 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 196328 kb
Host smart-f5db463d-f774-4201-9c06-6dcab37a52cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306912360 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3306912360
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2360350596
Short name T761
Test name
Test status
Simulation time 48395163 ps
CPU time 1.94 seconds
Started Jul 24 05:14:06 PM PDT 24
Finished Jul 24 05:14:08 PM PDT 24
Peak memory 198248 kb
Host smart-6730119a-5336-48bc-a753-cd9b10616665
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360350596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2360350596
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2985602609
Short name T37
Test name
Test status
Simulation time 165153529 ps
CPU time 1.34 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 198296 kb
Host smart-2cd88710-4f05-45be-97fd-e0d82e29646d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985602609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2985602609
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2193833286
Short name T300
Test name
Test status
Simulation time 41903692 ps
CPU time 0.57 seconds
Started Jul 24 05:16:28 PM PDT 24
Finished Jul 24 05:16:29 PM PDT 24
Peak memory 194424 kb
Host smart-51aea1d3-eb58-4d84-b3ef-7502bee071b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193833286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2193833286
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.305115119
Short name T429
Test name
Test status
Simulation time 20281549 ps
CPU time 0.62 seconds
Started Jul 24 05:16:28 PM PDT 24
Finished Jul 24 05:16:29 PM PDT 24
Peak memory 195156 kb
Host smart-bf0257fe-e876-4343-81ac-4f5c6398bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305115119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.305115119
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2097944093
Short name T190
Test name
Test status
Simulation time 812597753 ps
CPU time 27.36 seconds
Started Jul 24 05:16:30 PM PDT 24
Finished Jul 24 05:16:58 PM PDT 24
Peak memory 197360 kb
Host smart-396c3633-569b-473e-a570-eb2c66255d3e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097944093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2097944093
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2153392789
Short name T673
Test name
Test status
Simulation time 156499048 ps
CPU time 1.08 seconds
Started Jul 24 05:16:31 PM PDT 24
Finished Jul 24 05:16:33 PM PDT 24
Peak memory 197068 kb
Host smart-de08e58c-50b4-4d60-8461-f53803b5e358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153392789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2153392789
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3971290791
Short name T284
Test name
Test status
Simulation time 43134457 ps
CPU time 1.24 seconds
Started Jul 24 05:16:26 PM PDT 24
Finished Jul 24 05:16:28 PM PDT 24
Peak memory 197644 kb
Host smart-6a2d7146-500b-4727-bdbf-c6df2929703a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971290791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3971290791
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.80753011
Short name T646
Test name
Test status
Simulation time 26785737 ps
CPU time 1.03 seconds
Started Jul 24 05:16:45 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 196508 kb
Host smart-518f49e2-86dd-480e-a842-c0c1de4f801c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80753011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.gpio_intr_with_filter_rand_intr_event.80753011
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2043584581
Short name T504
Test name
Test status
Simulation time 36443411 ps
CPU time 1.06 seconds
Started Jul 24 05:16:27 PM PDT 24
Finished Jul 24 05:16:28 PM PDT 24
Peak memory 196176 kb
Host smart-4a8b78a6-e0fe-48b6-b708-748962ca3b1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043584581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2043584581
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3267911182
Short name T104
Test name
Test status
Simulation time 59825027 ps
CPU time 1.06 seconds
Started Jul 24 05:16:19 PM PDT 24
Finished Jul 24 05:16:21 PM PDT 24
Peak memory 196292 kb
Host smart-591b3dbd-6712-4f99-9ae4-8c5f276df216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267911182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3267911182
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3637994301
Short name T456
Test name
Test status
Simulation time 25665120 ps
CPU time 0.72 seconds
Started Jul 24 05:16:28 PM PDT 24
Finished Jul 24 05:16:29 PM PDT 24
Peak memory 196524 kb
Host smart-bd869197-cb68-4373-928c-be57a4605a21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637994301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3637994301
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.820304
Short name T440
Test name
Test status
Simulation time 211385095 ps
CPU time 3.66 seconds
Started Jul 24 05:16:37 PM PDT 24
Finished Jul 24 05:16:41 PM PDT 24
Peak memory 198460 kb
Host smart-e1aa0f57-bb44-42c1-8aa4-ab3ff6ffa56e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_wri
tes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_
long_reg_writes_reg_reads.820304
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1820030428
Short name T42
Test name
Test status
Simulation time 79981169 ps
CPU time 0.97 seconds
Started Jul 24 05:16:33 PM PDT 24
Finished Jul 24 05:16:34 PM PDT 24
Peak memory 215424 kb
Host smart-54a6c1a6-5beb-4ec1-90a9-bf89b517943c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820030428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1820030428
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.573627639
Short name T239
Test name
Test status
Simulation time 35778515 ps
CPU time 1.01 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 196236 kb
Host smart-9f6d16fc-28e0-417c-a47b-13231a1f8969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573627639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.573627639
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2954714770
Short name T146
Test name
Test status
Simulation time 46137961 ps
CPU time 0.92 seconds
Started Jul 24 05:16:25 PM PDT 24
Finished Jul 24 05:16:26 PM PDT 24
Peak memory 196916 kb
Host smart-b24bf65e-f0d2-40e8-a991-88a0cb86db39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954714770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2954714770
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.403458976
Short name T519
Test name
Test status
Simulation time 15449412323 ps
CPU time 140.8 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:19:08 PM PDT 24
Peak memory 198636 kb
Host smart-34b605ef-87c8-49d5-b819-416e9821ac75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403458976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.403458976
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3818229980
Short name T271
Test name
Test status
Simulation time 36889514935 ps
CPU time 762.69 seconds
Started Jul 24 05:16:33 PM PDT 24
Finished Jul 24 05:29:17 PM PDT 24
Peak memory 198724 kb
Host smart-10b3709c-a793-44be-aa0d-b22b548ab5d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3818229980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3818229980
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2898606716
Short name T539
Test name
Test status
Simulation time 36908820 ps
CPU time 0.56 seconds
Started Jul 24 05:16:32 PM PDT 24
Finished Jul 24 05:16:33 PM PDT 24
Peak memory 194392 kb
Host smart-0d9fb66c-6d27-4a05-ab11-cb5b517fd40e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898606716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2898606716
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.4042774418
Short name T186
Test name
Test status
Simulation time 69155139 ps
CPU time 0.71 seconds
Started Jul 24 05:16:15 PM PDT 24
Finished Jul 24 05:16:16 PM PDT 24
Peak memory 195752 kb
Host smart-eb7db791-09ee-417c-a947-051dc9d5f1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042774418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.4042774418
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2854706105
Short name T91
Test name
Test status
Simulation time 231176199 ps
CPU time 12.09 seconds
Started Jul 24 05:16:39 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 198468 kb
Host smart-115ffcf7-bd49-4f37-936c-e061442b7abf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854706105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2854706105
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3091050443
Short name T410
Test name
Test status
Simulation time 36635994 ps
CPU time 0.75 seconds
Started Jul 24 05:16:31 PM PDT 24
Finished Jul 24 05:16:32 PM PDT 24
Peak memory 196408 kb
Host smart-699ec626-e60d-4421-aa92-7ee386e5bfae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091050443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3091050443
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.92155249
Short name T147
Test name
Test status
Simulation time 72013044 ps
CPU time 0.81 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:45 PM PDT 24
Peak memory 196672 kb
Host smart-9fb64869-71f6-4fdb-a874-a4e982fbfd2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92155249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.92155249
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1360032101
Short name T600
Test name
Test status
Simulation time 27949221 ps
CPU time 1.12 seconds
Started Jul 24 05:16:33 PM PDT 24
Finished Jul 24 05:16:34 PM PDT 24
Peak memory 197796 kb
Host smart-6372d25b-9b6b-4dc2-9dc3-ed67f3d56756
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360032101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1360032101
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2104800556
Short name T270
Test name
Test status
Simulation time 100856042 ps
CPU time 2.97 seconds
Started Jul 24 05:16:22 PM PDT 24
Finished Jul 24 05:16:25 PM PDT 24
Peak memory 197640 kb
Host smart-e931912d-9ebe-4914-ac84-004ae619edac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104800556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2104800556
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.439738270
Short name T715
Test name
Test status
Simulation time 161231696 ps
CPU time 1.04 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:16:37 PM PDT 24
Peak memory 197092 kb
Host smart-dbbca737-04fa-4f35-b143-ceaee4349edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439738270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.439738270
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3020933964
Short name T261
Test name
Test status
Simulation time 98841522 ps
CPU time 1.02 seconds
Started Jul 24 05:16:30 PM PDT 24
Finished Jul 24 05:16:31 PM PDT 24
Peak memory 196388 kb
Host smart-791f24cc-f1c4-434b-a4cd-42bb61595598
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020933964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3020933964
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2167627719
Short name T656
Test name
Test status
Simulation time 585974946 ps
CPU time 1.92 seconds
Started Jul 24 05:16:28 PM PDT 24
Finished Jul 24 05:16:30 PM PDT 24
Peak memory 198476 kb
Host smart-5f35744f-fc3a-4671-83bb-8f694a4587b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167627719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2167627719
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.319285572
Short name T33
Test name
Test status
Simulation time 177320044 ps
CPU time 0.77 seconds
Started Jul 24 05:16:20 PM PDT 24
Finished Jul 24 05:16:21 PM PDT 24
Peak memory 214396 kb
Host smart-1d656158-3610-4db5-8a6f-0a1d4c9b1516
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319285572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.319285572
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.1038286775
Short name T303
Test name
Test status
Simulation time 34285035 ps
CPU time 1.04 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:45 PM PDT 24
Peak memory 197140 kb
Host smart-ff23c83b-18e7-4e2c-9f9f-6ab44c9db2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038286775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1038286775
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2920105308
Short name T510
Test name
Test status
Simulation time 138859869 ps
CPU time 1.18 seconds
Started Jul 24 05:16:28 PM PDT 24
Finished Jul 24 05:16:29 PM PDT 24
Peak memory 196184 kb
Host smart-018e5073-cb04-461a-aff8-07928ed5aabd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920105308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2920105308
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1667542021
Short name T8
Test name
Test status
Simulation time 132934438768 ps
CPU time 176.63 seconds
Started Jul 24 05:16:33 PM PDT 24
Finished Jul 24 05:19:30 PM PDT 24
Peak memory 198656 kb
Host smart-959685c4-c87b-4006-a3dd-73cc9946b8b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667542021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1667542021
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2738819767
Short name T373
Test name
Test status
Simulation time 12855088 ps
CPU time 0.57 seconds
Started Jul 24 05:16:50 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 194264 kb
Host smart-f0888e37-0547-4fd4-9e47-160e63de6a34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738819767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2738819767
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1637507378
Short name T349
Test name
Test status
Simulation time 122722118 ps
CPU time 0.9 seconds
Started Jul 24 05:16:38 PM PDT 24
Finished Jul 24 05:16:39 PM PDT 24
Peak memory 196484 kb
Host smart-61f8959f-c6e2-4e6f-8c41-2e9fef74ac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637507378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1637507378
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3113188436
Short name T612
Test name
Test status
Simulation time 4045958187 ps
CPU time 12.65 seconds
Started Jul 24 05:16:46 PM PDT 24
Finished Jul 24 05:16:59 PM PDT 24
Peak memory 197840 kb
Host smart-02f99a94-840b-4972-8846-0c6a3a762868
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113188436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3113188436
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3608248529
Short name T626
Test name
Test status
Simulation time 75345859 ps
CPU time 0.77 seconds
Started Jul 24 05:17:11 PM PDT 24
Finished Jul 24 05:17:12 PM PDT 24
Peak memory 196964 kb
Host smart-9ba494e9-f908-458c-a4fe-99fed1bfe498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608248529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3608248529
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2195792883
Short name T516
Test name
Test status
Simulation time 99494170 ps
CPU time 1.49 seconds
Started Jul 24 05:17:00 PM PDT 24
Finished Jul 24 05:17:02 PM PDT 24
Peak memory 198540 kb
Host smart-4df949ae-8c38-4aac-9fe9-436c365a0958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195792883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2195792883
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3198985947
Short name T244
Test name
Test status
Simulation time 298319511 ps
CPU time 3 seconds
Started Jul 24 05:16:55 PM PDT 24
Finished Jul 24 05:16:58 PM PDT 24
Peak memory 197792 kb
Host smart-f4f8877e-3f74-4451-9165-57535ddb1d1a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198985947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3198985947
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1803673489
Short name T92
Test name
Test status
Simulation time 149240964 ps
CPU time 2.17 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 196336 kb
Host smart-3868d2bd-1a39-4def-8950-c3dcc6eb9f35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803673489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1803673489
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1387683952
Short name T528
Test name
Test status
Simulation time 108277418 ps
CPU time 1.28 seconds
Started Jul 24 05:16:51 PM PDT 24
Finished Jul 24 05:16:52 PM PDT 24
Peak memory 196960 kb
Host smart-fa0cc556-b89f-4694-97b4-4708bc6280d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387683952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1387683952
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2832060323
Short name T637
Test name
Test status
Simulation time 51898772 ps
CPU time 1.01 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 195992 kb
Host smart-fea61fc6-4946-4b33-8a41-abe736c7682c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832060323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2832060323
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4014682349
Short name T672
Test name
Test status
Simulation time 98928088 ps
CPU time 1.91 seconds
Started Jul 24 05:17:02 PM PDT 24
Finished Jul 24 05:17:04 PM PDT 24
Peak memory 198452 kb
Host smart-f0e1b9e3-699b-4f76-979e-235b8bb8de72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014682349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.4014682349
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.927014295
Short name T15
Test name
Test status
Simulation time 51852764 ps
CPU time 1.31 seconds
Started Jul 24 05:16:38 PM PDT 24
Finished Jul 24 05:16:39 PM PDT 24
Peak memory 197236 kb
Host smart-6d5313f6-a687-4f96-9f97-7b43a413b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927014295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.927014295
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1835624647
Short name T518
Test name
Test status
Simulation time 47135963 ps
CPU time 1.25 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:54 PM PDT 24
Peak memory 196788 kb
Host smart-5c1415f4-10c7-4ac6-b72b-b86a2936dea9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835624647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1835624647
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.52144515
Short name T683
Test name
Test status
Simulation time 16545698213 ps
CPU time 95.17 seconds
Started Jul 24 05:17:04 PM PDT 24
Finished Jul 24 05:18:39 PM PDT 24
Peak memory 198500 kb
Host smart-70c25b3e-0155-44de-865f-0d70e1577857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52144515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gp
io_stress_all.52144515
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3339147394
Short name T474
Test name
Test status
Simulation time 18903733 ps
CPU time 0.57 seconds
Started Jul 24 05:16:45 PM PDT 24
Finished Jul 24 05:16:45 PM PDT 24
Peak memory 195040 kb
Host smart-29f8b2af-6df9-4962-b188-53536d1e64a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339147394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3339147394
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.4003594279
Short name T350
Test name
Test status
Simulation time 29985595 ps
CPU time 0.72 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 195684 kb
Host smart-264a9e01-a922-4e1a-b0e4-150635d41336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003594279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.4003594279
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.381232457
Short name T536
Test name
Test status
Simulation time 1270662345 ps
CPU time 13.57 seconds
Started Jul 24 05:16:54 PM PDT 24
Finished Jul 24 05:17:07 PM PDT 24
Peak memory 198400 kb
Host smart-c50ff719-5373-4d47-8ac9-6e9559bd4cf3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381232457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.381232457
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2833738588
Short name T377
Test name
Test status
Simulation time 43436044 ps
CPU time 0.81 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:06 PM PDT 24
Peak memory 197156 kb
Host smart-420d6213-a49e-463d-8646-c042b3a6ca47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833738588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2833738588
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2690874916
Short name T375
Test name
Test status
Simulation time 522137552 ps
CPU time 1.16 seconds
Started Jul 24 05:16:50 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 197420 kb
Host smart-ba4eeb99-72be-4869-b975-2938ecbfdf5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690874916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2690874916
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.876008317
Short name T523
Test name
Test status
Simulation time 46934143 ps
CPU time 1.8 seconds
Started Jul 24 05:16:38 PM PDT 24
Finished Jul 24 05:16:40 PM PDT 24
Peak memory 198372 kb
Host smart-ad007b19-ad59-491a-b093-a469cef0b47c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876008317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.876008317
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2852783726
Short name T180
Test name
Test status
Simulation time 835878516 ps
CPU time 2.45 seconds
Started Jul 24 05:16:40 PM PDT 24
Finished Jul 24 05:16:43 PM PDT 24
Peak memory 197636 kb
Host smart-4e970d35-8f06-4779-92d0-b9c9d0fa41b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852783726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2852783726
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1795421315
Short name T689
Test name
Test status
Simulation time 105748462 ps
CPU time 0.66 seconds
Started Jul 24 05:16:53 PM PDT 24
Finished Jul 24 05:16:54 PM PDT 24
Peak memory 194660 kb
Host smart-bd7344a8-5efe-4897-a6f5-fc1ac898572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795421315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1795421315
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2003805605
Short name T454
Test name
Test status
Simulation time 62814452 ps
CPU time 0.79 seconds
Started Jul 24 05:16:45 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 196888 kb
Host smart-63d6d436-d413-489a-85b2-9e4df4615615
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003805605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2003805605
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3651024277
Short name T149
Test name
Test status
Simulation time 1358492040 ps
CPU time 4.73 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:53 PM PDT 24
Peak memory 198452 kb
Host smart-f02008c0-c971-40b8-b946-24f3486b0028
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651024277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3651024277
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1867367469
Short name T334
Test name
Test status
Simulation time 69610775 ps
CPU time 1.27 seconds
Started Jul 24 05:16:54 PM PDT 24
Finished Jul 24 05:16:55 PM PDT 24
Peak memory 197124 kb
Host smart-5cb56b84-6072-422a-b2c4-47391b0e7514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867367469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1867367469
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1263063167
Short name T393
Test name
Test status
Simulation time 259945516 ps
CPU time 1.01 seconds
Started Jul 24 05:16:46 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 197036 kb
Host smart-87de10a4-35bf-4d03-a83d-05bada05e68b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263063167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1263063167
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1284743317
Short name T554
Test name
Test status
Simulation time 17596461391 ps
CPU time 139.56 seconds
Started Jul 24 05:16:43 PM PDT 24
Finished Jul 24 05:19:03 PM PDT 24
Peak memory 198496 kb
Host smart-c2020714-5b17-4a6e-96eb-11147dabe547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284743317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1284743317
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.623789655
Short name T346
Test name
Test status
Simulation time 156316066617 ps
CPU time 641.52 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:27:47 PM PDT 24
Peak memory 198728 kb
Host smart-12adc918-8169-4f61-a16e-4b544e109207
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=623789655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.623789655
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2659816319
Short name T584
Test name
Test status
Simulation time 38162513 ps
CPU time 0.54 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:49 PM PDT 24
Peak memory 194276 kb
Host smart-4fd15545-5ed7-4edb-9f34-d196c5211a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659816319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2659816319
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3105648861
Short name T541
Test name
Test status
Simulation time 72978686 ps
CPU time 0.79 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:06 PM PDT 24
Peak memory 195860 kb
Host smart-1a91ae0b-4d13-4c92-b282-bc380b8bb93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105648861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3105648861
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.191927552
Short name T124
Test name
Test status
Simulation time 456605450 ps
CPU time 15.25 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:21 PM PDT 24
Peak memory 197284 kb
Host smart-3bd638c6-d056-4fef-b876-213cfec1af72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191927552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.191927552
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.597723735
Short name T463
Test name
Test status
Simulation time 181284602 ps
CPU time 1.05 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:45 PM PDT 24
Peak memory 197168 kb
Host smart-a1647511-cfce-4a74-b04e-f9709a9e6c88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597723735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.597723735
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1338074975
Short name T532
Test name
Test status
Simulation time 40953033 ps
CPU time 0.8 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:49 PM PDT 24
Peak memory 196148 kb
Host smart-0869660c-6a71-4fb5-8183-3f96d1b78d13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338074975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1338074975
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2897938202
Short name T437
Test name
Test status
Simulation time 90035656 ps
CPU time 1.59 seconds
Started Jul 24 05:16:59 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 197332 kb
Host smart-7230c144-d7ba-427a-99d3-60b22801e043
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897938202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2897938202
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.969089868
Short name T682
Test name
Test status
Simulation time 121670056 ps
CPU time 2.54 seconds
Started Jul 24 05:16:55 PM PDT 24
Finished Jul 24 05:16:58 PM PDT 24
Peak memory 197012 kb
Host smart-f57ed5cc-8811-4824-a03e-0ed0f2915bbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969089868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
969089868
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.768854499
Short name T144
Test name
Test status
Simulation time 41103087 ps
CPU time 0.99 seconds
Started Jul 24 05:16:40 PM PDT 24
Finished Jul 24 05:16:41 PM PDT 24
Peak memory 196424 kb
Host smart-6e0fec08-ed1b-4eb4-89fd-de9c4681c154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768854499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.768854499
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.4294348063
Short name T112
Test name
Test status
Simulation time 54786843 ps
CPU time 0.79 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 196724 kb
Host smart-686cb62a-9050-4107-af38-5e6c3b5e724e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294348063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.4294348063
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.124974581
Short name T276
Test name
Test status
Simulation time 367865761 ps
CPU time 3.21 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:52 PM PDT 24
Peak memory 198448 kb
Host smart-5ea23c95-949f-4d90-a8d2-fce8354e76f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124974581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.124974581
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.757192204
Short name T198
Test name
Test status
Simulation time 239241769 ps
CPU time 1.08 seconds
Started Jul 24 05:16:38 PM PDT 24
Finished Jul 24 05:16:39 PM PDT 24
Peak memory 196352 kb
Host smart-f19c0ffe-a572-4a6b-94ac-2faa035b48d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757192204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.757192204
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.606377538
Short name T590
Test name
Test status
Simulation time 136310573 ps
CPU time 1.21 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:49 PM PDT 24
Peak memory 196232 kb
Host smart-65cbf1a7-d6c7-469c-b094-c95ab4e0af91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606377538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.606377538
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4112171804
Short name T139
Test name
Test status
Simulation time 7779652447 ps
CPU time 124.32 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:19:50 PM PDT 24
Peak memory 197564 kb
Host smart-07acb791-167d-42c5-849b-355f47be5d42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112171804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4112171804
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.319392260
Short name T623
Test name
Test status
Simulation time 32092122 ps
CPU time 0.56 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 195104 kb
Host smart-ae60bb66-75b0-4cb6-ae5c-541ba301479f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319392260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.319392260
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1177111328
Short name T210
Test name
Test status
Simulation time 320551698 ps
CPU time 0.66 seconds
Started Jul 24 05:16:58 PM PDT 24
Finished Jul 24 05:16:59 PM PDT 24
Peak memory 194524 kb
Host smart-7a957393-8664-42be-a572-8a7fd76fb26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177111328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1177111328
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3001518368
Short name T423
Test name
Test status
Simulation time 310661617 ps
CPU time 5.57 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:52 PM PDT 24
Peak memory 197192 kb
Host smart-428376d4-11fb-4b75-908f-621416dc06b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001518368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3001518368
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2338775699
Short name T587
Test name
Test status
Simulation time 54186873 ps
CPU time 0.92 seconds
Started Jul 24 05:17:06 PM PDT 24
Finished Jul 24 05:17:07 PM PDT 24
Peak memory 197628 kb
Host smart-91371e57-fba6-4eca-b5f7-338981969ef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338775699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2338775699
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3743218618
Short name T699
Test name
Test status
Simulation time 61487588 ps
CPU time 0.69 seconds
Started Jul 24 05:17:04 PM PDT 24
Finished Jul 24 05:17:05 PM PDT 24
Peak memory 194748 kb
Host smart-ffc500b7-e19b-46c4-94b5-30e4830112a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743218618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3743218618
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1474342368
Short name T667
Test name
Test status
Simulation time 365880503 ps
CPU time 2.83 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:08 PM PDT 24
Peak memory 196784 kb
Host smart-eaab93c4-61b7-464e-b228-db7200e7aa04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474342368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1474342368
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.4044222370
Short name T121
Test name
Test status
Simulation time 41491859 ps
CPU time 0.86 seconds
Started Jul 24 05:16:51 PM PDT 24
Finished Jul 24 05:16:52 PM PDT 24
Peak memory 195952 kb
Host smart-51d9e564-c647-4568-a15c-0e52625b4112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044222370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.4044222370
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.989569367
Short name T212
Test name
Test status
Simulation time 260760936 ps
CPU time 0.86 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 196508 kb
Host smart-b60324fc-d3d8-41df-a37b-a12d900df2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989569367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.989569367
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2647266214
Short name T540
Test name
Test status
Simulation time 18677449 ps
CPU time 0.78 seconds
Started Jul 24 05:16:59 PM PDT 24
Finished Jul 24 05:17:00 PM PDT 24
Peak memory 195992 kb
Host smart-3c233a02-d9a3-4ea6-8ee0-a0955759e6df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647266214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2647266214
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.148940862
Short name T232
Test name
Test status
Simulation time 311726960 ps
CPU time 3.58 seconds
Started Jul 24 05:16:58 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 198480 kb
Host smart-abe64e9c-2283-4631-8c4a-48c2d9479f42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148940862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.148940862
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.4277446205
Short name T347
Test name
Test status
Simulation time 87690462 ps
CPU time 1.09 seconds
Started Jul 24 05:17:02 PM PDT 24
Finished Jul 24 05:17:03 PM PDT 24
Peak memory 196020 kb
Host smart-5e4a7169-ac02-490a-886b-c39e3df4225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277446205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.4277446205
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1527986193
Short name T283
Test name
Test status
Simulation time 23033470 ps
CPU time 0.76 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 195968 kb
Host smart-5b35e0d5-26f4-485f-9cf3-cf4f90e977ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527986193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1527986193
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1540956991
Short name T157
Test name
Test status
Simulation time 25273025089 ps
CPU time 183.02 seconds
Started Jul 24 05:16:51 PM PDT 24
Finished Jul 24 05:19:54 PM PDT 24
Peak memory 198608 kb
Host smart-06a284ec-02e6-4a39-9789-d3f144c2647f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540956991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1540956991
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.178870803
Short name T607
Test name
Test status
Simulation time 68571338 ps
CPU time 0.65 seconds
Started Jul 24 05:17:00 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 195216 kb
Host smart-cdbbfe68-f71d-4c28-8aae-472499ef59ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178870803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.178870803
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.4096509191
Short name T713
Test name
Test status
Simulation time 1556012119 ps
CPU time 25.67 seconds
Started Jul 24 05:16:57 PM PDT 24
Finished Jul 24 05:17:23 PM PDT 24
Peak memory 197312 kb
Host smart-59d86543-bb35-431d-86d6-4e0e6076ebc6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096509191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.4096509191
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3650434353
Short name T694
Test name
Test status
Simulation time 101393404 ps
CPU time 0.63 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:49 PM PDT 24
Peak memory 194892 kb
Host smart-0ef8194e-426a-4699-a12a-022e8c8a18e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650434353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3650434353
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2731720012
Short name T654
Test name
Test status
Simulation time 76976868 ps
CPU time 1.3 seconds
Started Jul 24 05:16:57 PM PDT 24
Finished Jul 24 05:16:58 PM PDT 24
Peak memory 197140 kb
Host smart-e662b434-c79c-4ab8-b2ec-ffc554a0b0bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731720012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2731720012
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.57997922
Short name T711
Test name
Test status
Simulation time 150606348 ps
CPU time 3.11 seconds
Started Jul 24 05:16:51 PM PDT 24
Finished Jul 24 05:16:54 PM PDT 24
Peak memory 198544 kb
Host smart-12760b88-7738-423e-a677-bd87fcecbb9b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57997922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.gpio_intr_with_filter_rand_intr_event.57997922
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.599864974
Short name T522
Test name
Test status
Simulation time 95527686 ps
CPU time 1.11 seconds
Started Jul 24 05:16:51 PM PDT 24
Finished Jul 24 05:16:52 PM PDT 24
Peak memory 196892 kb
Host smart-1b336ff2-3314-4b02-9fa8-dc95d8f1003e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599864974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
599864974
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2761519691
Short name T247
Test name
Test status
Simulation time 85929584 ps
CPU time 0.72 seconds
Started Jul 24 05:17:00 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 195968 kb
Host smart-05ee04a0-b983-4a1a-a71f-af7871bdbc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761519691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2761519691
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.82320070
Short name T561
Test name
Test status
Simulation time 211004460 ps
CPU time 1.23 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 198580 kb
Host smart-9b66ce88-3890-4f18-8e3f-715986080a1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82320070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup_
pulldown.82320070
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4134744478
Short name T105
Test name
Test status
Simulation time 1207025834 ps
CPU time 5.85 seconds
Started Jul 24 05:16:55 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 198420 kb
Host smart-b49928c1-0b2a-44dc-b918-6153aa724584
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134744478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4134744478
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.4194993484
Short name T26
Test name
Test status
Simulation time 165867229 ps
CPU time 1.45 seconds
Started Jul 24 05:16:50 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 198468 kb
Host smart-4d0eb2dd-6dc6-41f1-8744-eab8221acd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194993484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.4194993484
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3289377949
Short name T512
Test name
Test status
Simulation time 224867867 ps
CPU time 0.99 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:06 PM PDT 24
Peak memory 197528 kb
Host smart-1f468be6-6806-45ca-b49b-2df032c09ad6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289377949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3289377949
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2747432476
Short name T391
Test name
Test status
Simulation time 7536644439 ps
CPU time 44.61 seconds
Started Jul 24 05:17:02 PM PDT 24
Finished Jul 24 05:17:46 PM PDT 24
Peak memory 198584 kb
Host smart-40f40993-c2ae-4399-a397-12565bc4b666
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747432476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2747432476
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3306514754
Short name T47
Test name
Test status
Simulation time 39512708704 ps
CPU time 643.09 seconds
Started Jul 24 05:17:00 PM PDT 24
Finished Jul 24 05:27:44 PM PDT 24
Peak memory 198708 kb
Host smart-168cd972-86fa-4480-bb7b-802b33ef00de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3306514754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3306514754
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.233262974
Short name T257
Test name
Test status
Simulation time 18047883 ps
CPU time 0.55 seconds
Started Jul 24 05:16:41 PM PDT 24
Finished Jul 24 05:16:42 PM PDT 24
Peak memory 194316 kb
Host smart-f4920bc4-0429-4481-bbeb-fe1fb9c3be94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233262974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.233262974
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2310107673
Short name T490
Test name
Test status
Simulation time 14656292 ps
CPU time 0.63 seconds
Started Jul 24 05:17:15 PM PDT 24
Finished Jul 24 05:17:16 PM PDT 24
Peak memory 194420 kb
Host smart-973a7f19-32fe-4c65-9e6f-ee01076ed728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310107673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2310107673
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1917565673
Short name T381
Test name
Test status
Simulation time 310753590 ps
CPU time 10.98 seconds
Started Jul 24 05:17:10 PM PDT 24
Finished Jul 24 05:17:21 PM PDT 24
Peak memory 198452 kb
Host smart-458008f4-9a66-4daa-a7c9-f9164971db8d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917565673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1917565673
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3434370455
Short name T543
Test name
Test status
Simulation time 124989473 ps
CPU time 0.87 seconds
Started Jul 24 05:16:42 PM PDT 24
Finished Jul 24 05:16:43 PM PDT 24
Peak memory 197624 kb
Host smart-be91a41c-2679-4f5b-85ee-019d4526a1de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434370455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3434370455
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.4150698229
Short name T455
Test name
Test status
Simulation time 45000239 ps
CPU time 0.89 seconds
Started Jul 24 05:16:54 PM PDT 24
Finished Jul 24 05:16:55 PM PDT 24
Peak memory 196520 kb
Host smart-4c61caf2-8510-4e6f-be2f-83b1c6f645ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150698229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.4150698229
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2938917667
Short name T615
Test name
Test status
Simulation time 747927118 ps
CPU time 2.76 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:08 PM PDT 24
Peak memory 198648 kb
Host smart-2df5ad65-971f-4ada-9b91-f0eaf1f76679
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938917667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2938917667
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2939572660
Short name T224
Test name
Test status
Simulation time 111235879 ps
CPU time 1.42 seconds
Started Jul 24 05:17:13 PM PDT 24
Finished Jul 24 05:17:14 PM PDT 24
Peak memory 196608 kb
Host smart-9cb23647-e379-400a-a3c9-05491d392831
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939572660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2939572660
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3883602244
Short name T316
Test name
Test status
Simulation time 33682086 ps
CPU time 1.28 seconds
Started Jul 24 05:16:59 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 196352 kb
Host smart-cc024464-1b3b-4f33-ba2e-da2d69fceb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883602244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3883602244
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.4197198889
Short name T565
Test name
Test status
Simulation time 115614830 ps
CPU time 1.27 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 197608 kb
Host smart-87d42d11-8ff0-4d39-b38e-7ef21963ed3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197198889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.4197198889
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2935957564
Short name T390
Test name
Test status
Simulation time 573537258 ps
CPU time 4.58 seconds
Started Jul 24 05:17:01 PM PDT 24
Finished Jul 24 05:17:05 PM PDT 24
Peak memory 198516 kb
Host smart-1428e699-d068-4357-8498-19ce6dad1ecb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935957564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2935957564
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2918326563
Short name T166
Test name
Test status
Simulation time 993903175 ps
CPU time 1.2 seconds
Started Jul 24 05:16:54 PM PDT 24
Finished Jul 24 05:16:56 PM PDT 24
Peak memory 196212 kb
Host smart-69b9b6ef-d765-4ccf-86d3-990592332e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918326563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2918326563
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1846895358
Short name T201
Test name
Test status
Simulation time 101552309 ps
CPU time 0.97 seconds
Started Jul 24 05:16:59 PM PDT 24
Finished Jul 24 05:17:00 PM PDT 24
Peak memory 195980 kb
Host smart-4f49ecd8-2614-4970-baca-408e773f5ec9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846895358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1846895358
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1563818977
Short name T10
Test name
Test status
Simulation time 34390240172 ps
CPU time 181.47 seconds
Started Jul 24 05:16:53 PM PDT 24
Finished Jul 24 05:19:54 PM PDT 24
Peak memory 198584 kb
Host smart-f23d559d-baf3-47fc-8636-211eb837b4ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563818977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1563818977
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.4124374704
Short name T176
Test name
Test status
Simulation time 206133395192 ps
CPU time 2603.89 seconds
Started Jul 24 05:16:57 PM PDT 24
Finished Jul 24 06:00:21 PM PDT 24
Peak memory 198744 kb
Host smart-4bab6cc9-4b48-4397-a527-04f998e71d34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4124374704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.4124374704
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.468787898
Short name T392
Test name
Test status
Simulation time 42695418 ps
CPU time 0.56 seconds
Started Jul 24 05:17:06 PM PDT 24
Finished Jul 24 05:17:07 PM PDT 24
Peak memory 194348 kb
Host smart-b46e06ab-8233-4a6d-bd14-c1ea707b52f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468787898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.468787898
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1286171919
Short name T461
Test name
Test status
Simulation time 56538232 ps
CPU time 0.62 seconds
Started Jul 24 05:17:04 PM PDT 24
Finished Jul 24 05:17:05 PM PDT 24
Peak memory 194460 kb
Host smart-ad1552fd-9649-447c-95bc-3d9b656e2b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286171919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1286171919
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1495765240
Short name T641
Test name
Test status
Simulation time 258811041 ps
CPU time 12.68 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:17 PM PDT 24
Peak memory 198532 kb
Host smart-09d5f9fd-378c-464e-a9c7-ecb7539e64a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495765240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1495765240
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1784491497
Short name T22
Test name
Test status
Simulation time 933391268 ps
CPU time 1 seconds
Started Jul 24 05:17:06 PM PDT 24
Finished Jul 24 05:17:08 PM PDT 24
Peak memory 196924 kb
Host smart-e2425e53-d4e6-479e-936d-4e0bc42d63c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784491497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1784491497
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2343957124
Short name T255
Test name
Test status
Simulation time 92010337 ps
CPU time 1.2 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:07 PM PDT 24
Peak memory 197128 kb
Host smart-7a5550c4-8135-4c46-b7d7-587f41680f3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343957124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2343957124
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2713953542
Short name T333
Test name
Test status
Simulation time 134346545 ps
CPU time 3.15 seconds
Started Jul 24 05:16:50 PM PDT 24
Finished Jul 24 05:16:54 PM PDT 24
Peak memory 198584 kb
Host smart-e3dab7c0-2239-48cb-8151-cdc50db5b43d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713953542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2713953542
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2822237451
Short name T446
Test name
Test status
Simulation time 220785712 ps
CPU time 1.74 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 196676 kb
Host smart-eb116d9f-9941-43fe-b879-0ab752ff86b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822237451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2822237451
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2146296025
Short name T398
Test name
Test status
Simulation time 44759557 ps
CPU time 1.02 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:06 PM PDT 24
Peak memory 197196 kb
Host smart-79aac94b-a4e2-4e11-92a3-88dd79743ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146296025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2146296025
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3616944487
Short name T56
Test name
Test status
Simulation time 27814118 ps
CPU time 0.95 seconds
Started Jul 24 05:16:57 PM PDT 24
Finished Jul 24 05:16:58 PM PDT 24
Peak memory 196408 kb
Host smart-ee027f3a-5d72-4f7c-a66e-acc4277b277f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616944487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3616944487
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2632391294
Short name T7
Test name
Test status
Simulation time 156319600 ps
CPU time 1.33 seconds
Started Jul 24 05:17:02 PM PDT 24
Finished Jul 24 05:17:04 PM PDT 24
Peak memory 198436 kb
Host smart-240f8005-3a16-4e9c-9e65-8113cdb7852a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632391294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2632391294
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.392860033
Short name T323
Test name
Test status
Simulation time 66214005 ps
CPU time 1.06 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 196940 kb
Host smart-887cca32-0e16-4964-9741-f91b4d77e689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392860033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.392860033
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4111346359
Short name T107
Test name
Test status
Simulation time 208468533 ps
CPU time 0.97 seconds
Started Jul 24 05:16:50 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 196020 kb
Host smart-361e0dc4-bc74-4ab4-9dee-dc1602acc923
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111346359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4111346359
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.356956458
Short name T348
Test name
Test status
Simulation time 6621924693 ps
CPU time 159.4 seconds
Started Jul 24 05:16:54 PM PDT 24
Finished Jul 24 05:19:33 PM PDT 24
Peak memory 198600 kb
Host smart-f5be3166-ee1c-4879-b312-dc0fe4a31516
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356956458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.356956458
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2515572901
Short name T49
Test name
Test status
Simulation time 64486148194 ps
CPU time 1114.78 seconds
Started Jul 24 05:16:55 PM PDT 24
Finished Jul 24 05:35:30 PM PDT 24
Peak memory 198740 kb
Host smart-734127d3-fdc5-4f8d-9d66-d6df64033e70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2515572901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2515572901
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1049466740
Short name T611
Test name
Test status
Simulation time 42906415 ps
CPU time 0.57 seconds
Started Jul 24 05:16:56 PM PDT 24
Finished Jul 24 05:16:56 PM PDT 24
Peak memory 194436 kb
Host smart-bc29f411-5293-4312-b2d9-1d0eec18847e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049466740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1049466740
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3540310735
Short name T364
Test name
Test status
Simulation time 17246719 ps
CPU time 0.6 seconds
Started Jul 24 05:16:56 PM PDT 24
Finished Jul 24 05:16:56 PM PDT 24
Peak memory 194320 kb
Host smart-107cceaf-3951-4e8b-a9ea-9ef038088928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540310735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3540310735
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.513323255
Short name T285
Test name
Test status
Simulation time 3276550970 ps
CPU time 25.97 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:17:15 PM PDT 24
Peak memory 197532 kb
Host smart-fc6b86bb-c96b-40ca-af12-18587976aa7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513323255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.513323255
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3704984191
Short name T435
Test name
Test status
Simulation time 66741444 ps
CPU time 0.83 seconds
Started Jul 24 05:17:08 PM PDT 24
Finished Jul 24 05:17:09 PM PDT 24
Peak memory 196304 kb
Host smart-7ec5809f-1900-474f-9da1-d2e8c6bf72ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704984191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3704984191
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2942916819
Short name T361
Test name
Test status
Simulation time 52424208 ps
CPU time 1.05 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 196404 kb
Host smart-d6fe17c7-3596-446c-a2ed-75a7e620e7cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942916819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2942916819
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.4184342133
Short name T551
Test name
Test status
Simulation time 262619275 ps
CPU time 2.75 seconds
Started Jul 24 05:17:01 PM PDT 24
Finished Jul 24 05:17:04 PM PDT 24
Peak memory 196944 kb
Host smart-3d053c87-598d-49ef-ab2b-8c0dc3ab9f9c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184342133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.4184342133
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3281805549
Short name T618
Test name
Test status
Simulation time 582600520 ps
CPU time 2.83 seconds
Started Jul 24 05:16:52 PM PDT 24
Finished Jul 24 05:16:55 PM PDT 24
Peak memory 197672 kb
Host smart-a0724829-e53e-4a26-b215-5361e1df9275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281805549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3281805549
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.300563176
Short name T253
Test name
Test status
Simulation time 78224672 ps
CPU time 0.97 seconds
Started Jul 24 05:17:09 PM PDT 24
Finished Jul 24 05:17:10 PM PDT 24
Peak memory 197264 kb
Host smart-a68669e3-5b47-41f1-89f8-b2bd9b7f0bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300563176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.300563176
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3055827484
Short name T360
Test name
Test status
Simulation time 26178341 ps
CPU time 1.04 seconds
Started Jul 24 05:17:03 PM PDT 24
Finished Jul 24 05:17:04 PM PDT 24
Peak memory 196468 kb
Host smart-8c003352-eeec-4123-a282-16689df4a74b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055827484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3055827484
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2788696928
Short name T133
Test name
Test status
Simulation time 154976753 ps
CPU time 2.55 seconds
Started Jul 24 05:17:11 PM PDT 24
Finished Jul 24 05:17:14 PM PDT 24
Peak memory 198484 kb
Host smart-7f2a1bb0-dff2-4c74-b0cd-0f6d9f93f304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788696928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2788696928
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1959530429
Short name T706
Test name
Test status
Simulation time 28966273 ps
CPU time 0.93 seconds
Started Jul 24 05:16:56 PM PDT 24
Finished Jul 24 05:16:57 PM PDT 24
Peak memory 196072 kb
Host smart-9a5cb308-352c-4662-81e8-dfef8dcf9861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959530429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1959530429
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2733304395
Short name T111
Test name
Test status
Simulation time 71816921 ps
CPU time 1.01 seconds
Started Jul 24 05:17:13 PM PDT 24
Finished Jul 24 05:17:14 PM PDT 24
Peak memory 196052 kb
Host smart-455b64be-6084-4880-979d-9f34a1a2dea8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733304395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2733304395
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.722019098
Short name T476
Test name
Test status
Simulation time 55682367466 ps
CPU time 236.88 seconds
Started Jul 24 05:16:54 PM PDT 24
Finished Jul 24 05:20:51 PM PDT 24
Peak memory 198576 kb
Host smart-6fdd00b0-0233-41d6-8d6a-f7129390f088
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722019098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.722019098
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3386984119
Short name T401
Test name
Test status
Simulation time 301104705272 ps
CPU time 1452.48 seconds
Started Jul 24 05:16:53 PM PDT 24
Finished Jul 24 05:41:06 PM PDT 24
Peak memory 198672 kb
Host smart-86794e99-40b0-4495-acbd-30c27bc8956a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3386984119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3386984119
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.61458830
Short name T605
Test name
Test status
Simulation time 45380317 ps
CPU time 0.56 seconds
Started Jul 24 05:17:01 PM PDT 24
Finished Jul 24 05:17:02 PM PDT 24
Peak memory 194424 kb
Host smart-a5ae147b-c058-4738-8f6b-23e031e4fc68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61458830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.61458830
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2170380503
Short name T167
Test name
Test status
Simulation time 109921864 ps
CPU time 0.75 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 194912 kb
Host smart-4a58ebe1-6e09-450d-be6f-03954f41859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170380503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2170380503
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3846379483
Short name T628
Test name
Test status
Simulation time 916681441 ps
CPU time 15.76 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 195920 kb
Host smart-36e974bb-76b3-4d04-821d-4d903cde5dbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846379483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3846379483
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3908447365
Short name T312
Test name
Test status
Simulation time 220733720 ps
CPU time 0.93 seconds
Started Jul 24 05:17:05 PM PDT 24
Finished Jul 24 05:17:06 PM PDT 24
Peak memory 198172 kb
Host smart-c948e804-afa3-4e0e-96c3-cbb84ed2dee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908447365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3908447365
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2554719118
Short name T622
Test name
Test status
Simulation time 53867797 ps
CPU time 0.75 seconds
Started Jul 24 05:16:53 PM PDT 24
Finished Jul 24 05:16:54 PM PDT 24
Peak memory 194836 kb
Host smart-7660107b-1105-4c98-ac77-ed585fb5b528
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554719118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2554719118
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2606232524
Short name T629
Test name
Test status
Simulation time 224793807 ps
CPU time 2.25 seconds
Started Jul 24 05:16:57 PM PDT 24
Finished Jul 24 05:17:00 PM PDT 24
Peak memory 198600 kb
Host smart-cd58a19b-b7e2-4014-8bd9-d7a772c479c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606232524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2606232524
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3175396833
Short name T557
Test name
Test status
Simulation time 54945130 ps
CPU time 1.02 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 196760 kb
Host smart-f47d4a41-8740-48e6-a1c0-1643809df268
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175396833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3175396833
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1455344460
Short name T438
Test name
Test status
Simulation time 28884666 ps
CPU time 1.05 seconds
Started Jul 24 05:17:02 PM PDT 24
Finished Jul 24 05:17:03 PM PDT 24
Peak memory 196624 kb
Host smart-f0edce05-fd72-4319-b08a-77295498b6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455344460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1455344460
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2127249430
Short name T428
Test name
Test status
Simulation time 70376522 ps
CPU time 0.85 seconds
Started Jul 24 05:16:58 PM PDT 24
Finished Jul 24 05:16:59 PM PDT 24
Peak memory 196496 kb
Host smart-846de0ea-5be8-4f23-9f63-4b314cd74df1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127249430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2127249430
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.4148698720
Short name T653
Test name
Test status
Simulation time 36729520 ps
CPU time 1.74 seconds
Started Jul 24 05:16:53 PM PDT 24
Finished Jul 24 05:16:55 PM PDT 24
Peak memory 198488 kb
Host smart-9c0dbcd2-69d1-4d16-86f2-71b22de4da42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148698720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.4148698720
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.4071366537
Short name T499
Test name
Test status
Simulation time 67849136 ps
CPU time 0.99 seconds
Started Jul 24 05:17:04 PM PDT 24
Finished Jul 24 05:17:05 PM PDT 24
Peak memory 196088 kb
Host smart-7b6260c9-7c65-4af5-b8c6-1129e5fd0ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071366537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.4071366537
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1933992657
Short name T242
Test name
Test status
Simulation time 138715618 ps
CPU time 1.24 seconds
Started Jul 24 05:16:55 PM PDT 24
Finished Jul 24 05:16:56 PM PDT 24
Peak memory 197088 kb
Host smart-eb024b4e-4455-4fdd-a246-243d4644022f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933992657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1933992657
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.199177252
Short name T515
Test name
Test status
Simulation time 7062971220 ps
CPU time 25.98 seconds
Started Jul 24 05:17:11 PM PDT 24
Finished Jul 24 05:17:38 PM PDT 24
Peak memory 198628 kb
Host smart-876558d6-6d7a-4bff-936d-b2bbb6e66436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199177252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.199177252
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.715221765
Short name T269
Test name
Test status
Simulation time 49278326874 ps
CPU time 1239.5 seconds
Started Jul 24 05:16:54 PM PDT 24
Finished Jul 24 05:37:34 PM PDT 24
Peak memory 198784 kb
Host smart-5e9a06ef-357e-467f-93cd-f657de246002
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=715221765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.715221765
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1212414744
Short name T566
Test name
Test status
Simulation time 14210683 ps
CPU time 0.56 seconds
Started Jul 24 05:17:13 PM PDT 24
Finished Jul 24 05:17:13 PM PDT 24
Peak memory 195136 kb
Host smart-54b5aab0-eade-42ef-a9ff-fc5ebc577851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212414744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1212414744
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.54169302
Short name T684
Test name
Test status
Simulation time 15910299 ps
CPU time 0.62 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 193440 kb
Host smart-853e3323-b462-404a-a52c-6801be5d244a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54169302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.54169302
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1201875244
Short name T250
Test name
Test status
Simulation time 4096419292 ps
CPU time 24.63 seconds
Started Jul 24 05:16:51 PM PDT 24
Finished Jul 24 05:17:15 PM PDT 24
Peak memory 198548 kb
Host smart-b90980a1-0920-41d0-aa43-ead05f5aece4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201875244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1201875244
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3647721982
Short name T304
Test name
Test status
Simulation time 33278323 ps
CPU time 0.71 seconds
Started Jul 24 05:17:13 PM PDT 24
Finished Jul 24 05:17:14 PM PDT 24
Peak memory 195016 kb
Host smart-fae680b4-e4e5-49a7-8a57-77c21471c766
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647721982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3647721982
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2260267917
Short name T44
Test name
Test status
Simulation time 149469090 ps
CPU time 1.29 seconds
Started Jul 24 05:17:08 PM PDT 24
Finished Jul 24 05:17:09 PM PDT 24
Peak memory 197068 kb
Host smart-40a07138-7988-4872-9313-5d7cb887c75f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260267917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2260267917
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3837790638
Short name T452
Test name
Test status
Simulation time 47532904 ps
CPU time 1.94 seconds
Started Jul 24 05:17:02 PM PDT 24
Finished Jul 24 05:17:04 PM PDT 24
Peak memory 198628 kb
Host smart-8af13395-be5f-4ae7-a8e8-9de3f6c2ec69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837790638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3837790638
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1859456513
Short name T570
Test name
Test status
Simulation time 651024026 ps
CPU time 1.47 seconds
Started Jul 24 05:17:00 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 196368 kb
Host smart-ffe7a743-e41a-4d8a-9968-cfd56ca66df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859456513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1859456513
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.911699267
Short name T311
Test name
Test status
Simulation time 18259839 ps
CPU time 0.7 seconds
Started Jul 24 05:16:58 PM PDT 24
Finished Jul 24 05:16:58 PM PDT 24
Peak memory 195736 kb
Host smart-5e18b2c6-b257-4aa3-8968-abc3a9a7a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911699267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.911699267
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3429112216
Short name T100
Test name
Test status
Simulation time 167809740 ps
CPU time 1.04 seconds
Started Jul 24 05:16:55 PM PDT 24
Finished Jul 24 05:16:56 PM PDT 24
Peak memory 196360 kb
Host smart-71e575af-750e-4f71-8711-31db2d64ffeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429112216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3429112216
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.569142143
Short name T404
Test name
Test status
Simulation time 397885748 ps
CPU time 6.26 seconds
Started Jul 24 05:16:55 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 198484 kb
Host smart-c8ba4c02-36de-409a-aa91-3c0a262b478c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569142143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.569142143
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2514102334
Short name T132
Test name
Test status
Simulation time 50201936 ps
CPU time 1.14 seconds
Started Jul 24 05:17:00 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 197352 kb
Host smart-993f22bc-81f8-43b9-ad58-b98b09a0c39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514102334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2514102334
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1973393994
Short name T114
Test name
Test status
Simulation time 83671566 ps
CPU time 0.81 seconds
Started Jul 24 05:16:50 PM PDT 24
Finished Jul 24 05:16:52 PM PDT 24
Peak memory 195740 kb
Host smart-3f6ab1ad-0882-48d8-95b2-30f2a1081a73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973393994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1973393994
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.912853804
Short name T642
Test name
Test status
Simulation time 11728464702 ps
CPU time 135.54 seconds
Started Jul 24 05:17:07 PM PDT 24
Finished Jul 24 05:19:23 PM PDT 24
Peak memory 198636 kb
Host smart-62923692-507c-4c1e-b4bd-5f2e10026853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912853804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.912853804
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3148267256
Short name T158
Test name
Test status
Simulation time 18513012 ps
CPU time 0.57 seconds
Started Jul 24 05:16:38 PM PDT 24
Finished Jul 24 05:16:39 PM PDT 24
Peak memory 194596 kb
Host smart-56f722d0-f740-4acb-830a-1d5064461823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148267256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3148267256
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1363745040
Short name T582
Test name
Test status
Simulation time 50869586 ps
CPU time 0.84 seconds
Started Jul 24 05:16:32 PM PDT 24
Finished Jul 24 05:16:33 PM PDT 24
Peak memory 196984 kb
Host smart-4e55b9d2-2382-429a-bcd2-d4ea707ba689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363745040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1363745040
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2182653637
Short name T481
Test name
Test status
Simulation time 3704032222 ps
CPU time 25.21 seconds
Started Jul 24 05:16:39 PM PDT 24
Finished Jul 24 05:17:05 PM PDT 24
Peak memory 197876 kb
Host smart-26bcc17c-5c17-4bba-88d4-6b69a06e8d04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182653637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2182653637
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2682311365
Short name T351
Test name
Test status
Simulation time 730933369 ps
CPU time 0.98 seconds
Started Jul 24 05:16:32 PM PDT 24
Finished Jul 24 05:16:33 PM PDT 24
Peak memory 198072 kb
Host smart-1ec56a6d-04f4-4c4e-9a73-ce96ddbde441
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682311365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2682311365
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.639512819
Short name T152
Test name
Test status
Simulation time 57190501 ps
CPU time 1.48 seconds
Started Jul 24 05:16:39 PM PDT 24
Finished Jul 24 05:16:40 PM PDT 24
Peak memory 198504 kb
Host smart-125ccb08-7630-488e-a708-d8b4a3db3c27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639512819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.639512819
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.211015185
Short name T583
Test name
Test status
Simulation time 189857893 ps
CPU time 1.76 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:16:43 PM PDT 24
Peak memory 197000 kb
Host smart-9cfc702e-3745-4342-840a-d95a614db6e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211015185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.211015185
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.4095178164
Short name T134
Test name
Test status
Simulation time 406314196 ps
CPU time 3.34 seconds
Started Jul 24 05:16:28 PM PDT 24
Finished Jul 24 05:16:32 PM PDT 24
Peak memory 198544 kb
Host smart-e4daa17e-1e81-4ed3-b339-54ac851636d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095178164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
4095178164
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2345333486
Short name T231
Test name
Test status
Simulation time 89137557 ps
CPU time 1.12 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 196572 kb
Host smart-5126b2fe-93be-46f6-ab35-ec80e721590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345333486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2345333486
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3302275986
Short name T61
Test name
Test status
Simulation time 21839169 ps
CPU time 0.83 seconds
Started Jul 24 05:16:25 PM PDT 24
Finished Jul 24 05:16:26 PM PDT 24
Peak memory 196804 kb
Host smart-e4844d5a-f5d3-400d-81a8-76d1f4009563
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302275986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3302275986
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2067225771
Short name T127
Test name
Test status
Simulation time 518728436 ps
CPU time 4.2 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:49 PM PDT 24
Peak memory 198464 kb
Host smart-d95734fb-6ea6-4e30-8469-f36a2f90c557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067225771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2067225771
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.40037059
Short name T332
Test name
Test status
Simulation time 22648373 ps
CPU time 0.68 seconds
Started Jul 24 05:16:29 PM PDT 24
Finished Jul 24 05:16:30 PM PDT 24
Peak memory 195264 kb
Host smart-d2042077-14ca-4ce1-ad4b-8ed7b57415a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40037059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.40037059
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1267355845
Short name T165
Test name
Test status
Simulation time 59570123 ps
CPU time 1.06 seconds
Started Jul 24 05:16:25 PM PDT 24
Finished Jul 24 05:16:26 PM PDT 24
Peak memory 196260 kb
Host smart-1a528732-1839-43bc-8530-08a80a6fbd9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267355845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1267355845
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3656674477
Short name T602
Test name
Test status
Simulation time 56089172866 ps
CPU time 192.59 seconds
Started Jul 24 05:16:24 PM PDT 24
Finished Jul 24 05:19:37 PM PDT 24
Peak memory 198524 kb
Host smart-a454bdc9-be69-455a-87d4-32c55c33a36a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656674477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3656674477
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2129410080
Short name T625
Test name
Test status
Simulation time 769336670471 ps
CPU time 2163.66 seconds
Started Jul 24 05:16:31 PM PDT 24
Finished Jul 24 05:52:40 PM PDT 24
Peak memory 198884 kb
Host smart-e2afbc72-2945-4995-93f1-93684337e0b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2129410080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2129410080
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2669183961
Short name T592
Test name
Test status
Simulation time 57126112 ps
CPU time 0.59 seconds
Started Jul 24 05:17:12 PM PDT 24
Finished Jul 24 05:17:13 PM PDT 24
Peak memory 195084 kb
Host smart-d380c345-27e0-4d51-b6fe-d9fc9a1a0276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669183961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2669183961
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.722033702
Short name T606
Test name
Test status
Simulation time 20688530 ps
CPU time 0.65 seconds
Started Jul 24 05:16:59 PM PDT 24
Finished Jul 24 05:17:00 PM PDT 24
Peak memory 194572 kb
Host smart-992c3987-836f-4908-b3ae-4971e69d65fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722033702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.722033702
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1064156953
Short name T620
Test name
Test status
Simulation time 595596873 ps
CPU time 14.2 seconds
Started Jul 24 05:16:52 PM PDT 24
Finished Jul 24 05:17:06 PM PDT 24
Peak memory 197264 kb
Host smart-9d7ecd39-856f-4ffe-b33a-0a0a469f6913
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064156953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1064156953
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.346182296
Short name T380
Test name
Test status
Simulation time 218657220 ps
CPU time 0.76 seconds
Started Jul 24 05:17:16 PM PDT 24
Finished Jul 24 05:17:17 PM PDT 24
Peak memory 196392 kb
Host smart-05acfca6-479e-4ce6-8eab-342eec2ecfdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346182296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.346182296
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.324973342
Short name T376
Test name
Test status
Simulation time 81607184 ps
CPU time 1.22 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:50 PM PDT 24
Peak memory 197552 kb
Host smart-f8c1ab37-a901-4663-9bce-81dc3b6fe3b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324973342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.324973342
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1736233677
Short name T293
Test name
Test status
Simulation time 356251177 ps
CPU time 3.82 seconds
Started Jul 24 05:17:04 PM PDT 24
Finished Jul 24 05:17:08 PM PDT 24
Peak memory 198516 kb
Host smart-2b5b42e8-ee96-4c8b-b3af-ed47ea0b128c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736233677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1736233677
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1282458570
Short name T119
Test name
Test status
Simulation time 663255520 ps
CPU time 3.32 seconds
Started Jul 24 05:17:06 PM PDT 24
Finished Jul 24 05:17:09 PM PDT 24
Peak memory 197736 kb
Host smart-6537173d-38ca-4cbb-8a5b-a97d117a68d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282458570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1282458570
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1763608781
Short name T661
Test name
Test status
Simulation time 85941158 ps
CPU time 0.93 seconds
Started Jul 24 05:17:01 PM PDT 24
Finished Jul 24 05:17:02 PM PDT 24
Peak memory 197180 kb
Host smart-8893adb9-78d2-41b9-a85d-c65467a51a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763608781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1763608781
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.255523580
Short name T163
Test name
Test status
Simulation time 21618732 ps
CPU time 0.77 seconds
Started Jul 24 05:17:12 PM PDT 24
Finished Jul 24 05:17:12 PM PDT 24
Peak memory 195880 kb
Host smart-126f5ba8-2894-41ab-9e88-017d15ec9910
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255523580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.255523580
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3322491038
Short name T619
Test name
Test status
Simulation time 346172300 ps
CPU time 1.7 seconds
Started Jul 24 05:17:08 PM PDT 24
Finished Jul 24 05:17:10 PM PDT 24
Peak memory 198496 kb
Host smart-a5fe2e89-3232-4b45-bde3-8ac9955aff63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322491038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3322491038
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2686288832
Short name T13
Test name
Test status
Simulation time 144383991 ps
CPU time 1.06 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 195888 kb
Host smart-9acce57b-0917-4dea-86d8-dce3df76d30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686288832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2686288832
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3440603077
Short name T200
Test name
Test status
Simulation time 21351954 ps
CPU time 0.75 seconds
Started Jul 24 05:16:52 PM PDT 24
Finished Jul 24 05:16:53 PM PDT 24
Peak memory 195640 kb
Host smart-cbc14243-2bca-45fc-b0a1-27eb9ebc27ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440603077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3440603077
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2784087641
Short name T19
Test name
Test status
Simulation time 9242971484 ps
CPU time 53.98 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:17:43 PM PDT 24
Peak memory 198640 kb
Host smart-a53b532b-9c3c-4c85-abd9-413fee6bf935
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784087641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2784087641
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2509108895
Short name T28
Test name
Test status
Simulation time 96517357324 ps
CPU time 994.59 seconds
Started Jul 24 05:17:06 PM PDT 24
Finished Jul 24 05:33:41 PM PDT 24
Peak memory 198740 kb
Host smart-18c3a914-382b-4410-9526-517b11edfb47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2509108895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2509108895
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2914918591
Short name T199
Test name
Test status
Simulation time 35066978 ps
CPU time 0.58 seconds
Started Jul 24 05:16:56 PM PDT 24
Finished Jul 24 05:16:57 PM PDT 24
Peak memory 194396 kb
Host smart-1629e427-2fe1-431b-b6aa-e8bc491d1237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914918591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2914918591
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1138210875
Short name T358
Test name
Test status
Simulation time 188582945 ps
CPU time 0.87 seconds
Started Jul 24 05:16:50 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 197148 kb
Host smart-0ccdfb20-073f-4650-a610-143bb571f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138210875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1138210875
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1112028455
Short name T624
Test name
Test status
Simulation time 589094733 ps
CPU time 9.71 seconds
Started Jul 24 05:16:53 PM PDT 24
Finished Jul 24 05:17:03 PM PDT 24
Peak memory 197416 kb
Host smart-bd06060b-102b-4603-9ee8-cdc12e0d8ffa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112028455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1112028455
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2425435207
Short name T644
Test name
Test status
Simulation time 104996119 ps
CPU time 0.74 seconds
Started Jul 24 05:17:08 PM PDT 24
Finished Jul 24 05:17:09 PM PDT 24
Peak memory 196216 kb
Host smart-4d7a35cb-b957-493c-96a0-68ff6c0801c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425435207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2425435207
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2274721464
Short name T529
Test name
Test status
Simulation time 80162809 ps
CPU time 0.7 seconds
Started Jul 24 05:17:19 PM PDT 24
Finished Jul 24 05:17:20 PM PDT 24
Peak memory 194820 kb
Host smart-a86455fc-e8c9-4e8d-8523-5fc6160925a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274721464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2274721464
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2740831893
Short name T708
Test name
Test status
Simulation time 26344762 ps
CPU time 1.08 seconds
Started Jul 24 05:17:11 PM PDT 24
Finished Jul 24 05:17:12 PM PDT 24
Peak memory 196848 kb
Host smart-b22c7a39-e65d-408e-a55c-9ce4d2176db1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740831893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2740831893
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3014432110
Short name T249
Test name
Test status
Simulation time 194257722 ps
CPU time 2.24 seconds
Started Jul 24 05:16:52 PM PDT 24
Finished Jul 24 05:16:54 PM PDT 24
Peak memory 197728 kb
Host smart-b348860b-1392-4e71-96d9-a78d85483193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014432110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3014432110
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.875951589
Short name T647
Test name
Test status
Simulation time 41528332 ps
CPU time 0.89 seconds
Started Jul 24 05:16:50 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 196612 kb
Host smart-76911906-32b7-4df8-af0f-dec9187c3e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875951589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.875951589
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3142006030
Short name T399
Test name
Test status
Simulation time 36857941 ps
CPU time 0.88 seconds
Started Jul 24 05:17:04 PM PDT 24
Finished Jul 24 05:17:05 PM PDT 24
Peak memory 195928 kb
Host smart-5dc90678-9d3d-4514-89cc-416041fcc02c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142006030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3142006030
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2834356651
Short name T531
Test name
Test status
Simulation time 267504766 ps
CPU time 3.21 seconds
Started Jul 24 05:16:52 PM PDT 24
Finished Jul 24 05:16:55 PM PDT 24
Peak memory 198476 kb
Host smart-71db6797-5591-4210-ae17-b27cdc243ff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834356651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2834356651
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3113861171
Short name T480
Test name
Test status
Simulation time 346906141 ps
CPU time 0.92 seconds
Started Jul 24 05:17:13 PM PDT 24
Finished Jul 24 05:17:14 PM PDT 24
Peak memory 195976 kb
Host smart-d781f5fe-6329-4cab-b7b9-c34a76d93f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113861171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3113861171
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2436297806
Short name T426
Test name
Test status
Simulation time 97967687 ps
CPU time 1.03 seconds
Started Jul 24 05:17:08 PM PDT 24
Finished Jul 24 05:17:09 PM PDT 24
Peak memory 197024 kb
Host smart-3cec2c36-5914-4704-b23a-a07c5899aaa8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436297806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2436297806
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2248909092
Short name T484
Test name
Test status
Simulation time 30295060046 ps
CPU time 192.51 seconds
Started Jul 24 05:17:07 PM PDT 24
Finished Jul 24 05:20:20 PM PDT 24
Peak memory 198604 kb
Host smart-a917e36e-2a3e-4039-b32a-7dac04cad7da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248909092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2248909092
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3932998590
Short name T362
Test name
Test status
Simulation time 13916506 ps
CPU time 0.56 seconds
Started Jul 24 05:17:15 PM PDT 24
Finished Jul 24 05:17:16 PM PDT 24
Peak memory 195104 kb
Host smart-0438d17b-871c-409f-96ca-5aaf4b5d40df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932998590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3932998590
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.4203160252
Short name T60
Test name
Test status
Simulation time 54954838 ps
CPU time 0.64 seconds
Started Jul 24 05:17:01 PM PDT 24
Finished Jul 24 05:17:02 PM PDT 24
Peak memory 194512 kb
Host smart-5d0e72ef-ab10-49b0-8ee2-27f18c7a48ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203160252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.4203160252
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3095539840
Short name T161
Test name
Test status
Simulation time 1339256559 ps
CPU time 15.3 seconds
Started Jul 24 05:17:08 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 196912 kb
Host smart-1cc94fb9-e5c0-4e07-928b-81de629e3f3f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095539840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3095539840
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.67768409
Short name T143
Test name
Test status
Simulation time 48074053 ps
CPU time 0.78 seconds
Started Jul 24 05:17:16 PM PDT 24
Finished Jul 24 05:17:16 PM PDT 24
Peak memory 196348 kb
Host smart-16ed2d52-a2ca-4040-8a3a-15cc5da83588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67768409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.67768409
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2855590132
Short name T716
Test name
Test status
Simulation time 29989891 ps
CPU time 0.9 seconds
Started Jul 24 05:17:17 PM PDT 24
Finished Jul 24 05:17:18 PM PDT 24
Peak memory 196472 kb
Host smart-147bf329-b4b1-4d1c-8812-8386c0febabc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855590132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2855590132
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1965279663
Short name T698
Test name
Test status
Simulation time 56958053 ps
CPU time 2.29 seconds
Started Jul 24 05:17:17 PM PDT 24
Finished Jul 24 05:17:20 PM PDT 24
Peak memory 196740 kb
Host smart-84843e10-65fa-46de-889e-535e9afd7055
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965279663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1965279663
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1712524984
Short name T272
Test name
Test status
Simulation time 105624171 ps
CPU time 3.14 seconds
Started Jul 24 05:17:18 PM PDT 24
Finished Jul 24 05:17:21 PM PDT 24
Peak memory 197660 kb
Host smart-efa0a404-e214-49a5-9eb0-4015ed41fcc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712524984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1712524984
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.774646370
Short name T562
Test name
Test status
Simulation time 135036800 ps
CPU time 1.14 seconds
Started Jul 24 05:17:14 PM PDT 24
Finished Jul 24 05:17:15 PM PDT 24
Peak memory 196584 kb
Host smart-87791f26-ef01-4e37-83de-17b82c08c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774646370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.774646370
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1362042284
Short name T598
Test name
Test status
Simulation time 41998245 ps
CPU time 0.98 seconds
Started Jul 24 05:17:06 PM PDT 24
Finished Jul 24 05:17:08 PM PDT 24
Peak memory 197192 kb
Host smart-03559ae4-f668-4638-be9e-d2f542a7da37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362042284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1362042284
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_smoke.1792754639
Short name T382
Test name
Test status
Simulation time 128103216 ps
CPU time 1.23 seconds
Started Jul 24 05:17:03 PM PDT 24
Finished Jul 24 05:17:05 PM PDT 24
Peak memory 196976 kb
Host smart-57088f2b-822f-422e-8d1e-ac8a0e257f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792754639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1792754639
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3379041906
Short name T295
Test name
Test status
Simulation time 148272566 ps
CPU time 1.44 seconds
Started Jul 24 05:16:51 PM PDT 24
Finished Jul 24 05:16:52 PM PDT 24
Peak memory 198456 kb
Host smart-73724003-2cf9-41a7-a820-2dc2c9cec092
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379041906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3379041906
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.629596278
Short name T27
Test name
Test status
Simulation time 20187826195 ps
CPU time 150.74 seconds
Started Jul 24 05:17:14 PM PDT 24
Finished Jul 24 05:19:44 PM PDT 24
Peak memory 198608 kb
Host smart-3ae82d6c-bf78-4e9a-8e39-218135949510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629596278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.629596278
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.4096460586
Short name T668
Test name
Test status
Simulation time 21642746 ps
CPU time 0.56 seconds
Started Jul 24 05:17:12 PM PDT 24
Finished Jul 24 05:17:13 PM PDT 24
Peak memory 194432 kb
Host smart-d7a4de3f-87b0-4dd8-9e7e-3dbe9d285fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096460586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.4096460586
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3191660866
Short name T596
Test name
Test status
Simulation time 29319531 ps
CPU time 0.6 seconds
Started Jul 24 05:17:11 PM PDT 24
Finished Jul 24 05:17:12 PM PDT 24
Peak memory 194328 kb
Host smart-74a0699f-dbbe-4fe1-8bb4-c01977e53bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191660866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3191660866
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3351840323
Short name T696
Test name
Test status
Simulation time 80854998 ps
CPU time 3.7 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 196996 kb
Host smart-f8d7cbdc-af74-467a-ac35-da686cc72b0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351840323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3351840323
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2902174317
Short name T640
Test name
Test status
Simulation time 89945435 ps
CPU time 0.72 seconds
Started Jul 24 05:17:15 PM PDT 24
Finished Jul 24 05:17:16 PM PDT 24
Peak memory 196296 kb
Host smart-f15454c1-7d57-4b23-a60e-193dd71c0e8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902174317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2902174317
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.274032703
Short name T406
Test name
Test status
Simulation time 37424529 ps
CPU time 0.72 seconds
Started Jul 24 05:17:17 PM PDT 24
Finished Jul 24 05:17:18 PM PDT 24
Peak memory 195976 kb
Host smart-60d9de48-07ab-4715-8ca0-8651e31f20bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274032703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.274032703
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2361074455
Short name T678
Test name
Test status
Simulation time 36276178 ps
CPU time 1.37 seconds
Started Jul 24 05:17:22 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 198420 kb
Host smart-f7c6712d-0697-4dde-b6ec-e71df176d8c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361074455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2361074455
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1397048836
Short name T258
Test name
Test status
Simulation time 234700018 ps
CPU time 3.37 seconds
Started Jul 24 05:17:12 PM PDT 24
Finished Jul 24 05:17:15 PM PDT 24
Peak memory 197776 kb
Host smart-5cd8489f-a9bf-429e-a75a-e9a0835bf2ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397048836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1397048836
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1530843235
Short name T418
Test name
Test status
Simulation time 26879538 ps
CPU time 0.73 seconds
Started Jul 24 05:17:06 PM PDT 24
Finished Jul 24 05:17:07 PM PDT 24
Peak memory 195780 kb
Host smart-6190403d-b976-443b-9de1-0d86047196bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530843235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1530843235
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4191374978
Short name T102
Test name
Test status
Simulation time 34054508 ps
CPU time 1.22 seconds
Started Jul 24 05:17:12 PM PDT 24
Finished Jul 24 05:17:13 PM PDT 24
Peak memory 196328 kb
Host smart-3da3c457-363f-42b0-9dc6-759b787d9d11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191374978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.4191374978
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3141325949
Short name T397
Test name
Test status
Simulation time 61366314 ps
CPU time 1.33 seconds
Started Jul 24 05:17:20 PM PDT 24
Finished Jul 24 05:17:22 PM PDT 24
Peak memory 198452 kb
Host smart-b79a4c49-f8b7-4937-85f6-fdef461130c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141325949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3141325949
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.245470183
Short name T506
Test name
Test status
Simulation time 81081746 ps
CPU time 1.05 seconds
Started Jul 24 05:17:12 PM PDT 24
Finished Jul 24 05:17:13 PM PDT 24
Peak memory 196760 kb
Host smart-efe97b45-0bac-4ee8-bfc6-f2190e1768bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245470183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.245470183
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1586342514
Short name T505
Test name
Test status
Simulation time 142706921 ps
CPU time 0.78 seconds
Started Jul 24 05:17:17 PM PDT 24
Finished Jul 24 05:17:18 PM PDT 24
Peak memory 195684 kb
Host smart-4d4876e8-bb9f-4ccb-bf07-983cf3f65f38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586342514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1586342514
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3478240758
Short name T3
Test name
Test status
Simulation time 15739587087 ps
CPU time 83.54 seconds
Started Jul 24 05:17:17 PM PDT 24
Finished Jul 24 05:18:41 PM PDT 24
Peak memory 198676 kb
Host smart-e2de530a-a11a-425a-bdf6-72c822d2364e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478240758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3478240758
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.599710678
Short name T237
Test name
Test status
Simulation time 208464686834 ps
CPU time 2879.82 seconds
Started Jul 24 05:17:10 PM PDT 24
Finished Jul 24 06:05:10 PM PDT 24
Peak memory 198796 kb
Host smart-b34dfe03-956d-4527-b019-63358b7b10cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=599710678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.599710678
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2794417014
Short name T374
Test name
Test status
Simulation time 19532324 ps
CPU time 0.59 seconds
Started Jul 24 05:17:10 PM PDT 24
Finished Jul 24 05:17:11 PM PDT 24
Peak memory 195284 kb
Host smart-0317414d-da68-4878-a9f5-5303194dddd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794417014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2794417014
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.490264968
Short name T153
Test name
Test status
Simulation time 48860152 ps
CPU time 1.01 seconds
Started Jul 24 05:17:20 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 196960 kb
Host smart-eaa840e5-24f4-4195-875f-a58b7140ae73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490264968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.490264968
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.91002482
Short name T117
Test name
Test status
Simulation time 724794886 ps
CPU time 23.93 seconds
Started Jul 24 05:17:15 PM PDT 24
Finished Jul 24 05:17:39 PM PDT 24
Peak memory 197396 kb
Host smart-16a12a16-37c9-41b8-a678-581714c65d46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91002482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stress
.91002482
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1808686555
Short name T57
Test name
Test status
Simulation time 891084540 ps
CPU time 0.96 seconds
Started Jul 24 05:17:07 PM PDT 24
Finished Jul 24 05:17:08 PM PDT 24
Peak memory 198400 kb
Host smart-11494d40-4c41-475e-9c77-3c4237d7e77a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808686555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1808686555
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1595813141
Short name T409
Test name
Test status
Simulation time 173169437 ps
CPU time 1.35 seconds
Started Jul 24 05:17:09 PM PDT 24
Finished Jul 24 05:17:10 PM PDT 24
Peak memory 198436 kb
Host smart-4bcbd798-6f60-48c9-b7b0-51786ec69088
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595813141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1595813141
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3593572441
Short name T97
Test name
Test status
Simulation time 249340090 ps
CPU time 2.99 seconds
Started Jul 24 05:17:19 PM PDT 24
Finished Jul 24 05:17:22 PM PDT 24
Peak memory 198404 kb
Host smart-d0218409-633c-45c9-959e-a980bcc8fb7a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593572441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3593572441
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.254495993
Short name T183
Test name
Test status
Simulation time 163246621 ps
CPU time 3.13 seconds
Started Jul 24 05:17:07 PM PDT 24
Finished Jul 24 05:17:11 PM PDT 24
Peak memory 197432 kb
Host smart-369a8e87-8e78-4b30-b0b6-7be3c895b2c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254495993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
254495993
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2537599320
Short name T110
Test name
Test status
Simulation time 102599922 ps
CPU time 0.76 seconds
Started Jul 24 05:17:08 PM PDT 24
Finished Jul 24 05:17:09 PM PDT 24
Peak memory 195804 kb
Host smart-3aae2d77-bbd9-4b2f-91c2-714334f9b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537599320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2537599320
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3870132684
Short name T603
Test name
Test status
Simulation time 40989402 ps
CPU time 0.98 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:25 PM PDT 24
Peak memory 196380 kb
Host smart-c7f097c8-1e03-4b72-886e-69da4079a6c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870132684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3870132684
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3466593432
Short name T680
Test name
Test status
Simulation time 153015043 ps
CPU time 3.72 seconds
Started Jul 24 05:17:11 PM PDT 24
Finished Jul 24 05:17:15 PM PDT 24
Peak memory 198452 kb
Host smart-d490ce71-bb89-49fc-a0d7-29e0b72bc9fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466593432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3466593432
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1159095582
Short name T109
Test name
Test status
Simulation time 166369310 ps
CPU time 1.36 seconds
Started Jul 24 05:17:09 PM PDT 24
Finished Jul 24 05:17:11 PM PDT 24
Peak memory 197192 kb
Host smart-2c9e32d6-d428-4511-bc11-18458ed8b07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159095582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1159095582
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.302221708
Short name T549
Test name
Test status
Simulation time 41799867 ps
CPU time 1.25 seconds
Started Jul 24 05:17:09 PM PDT 24
Finished Jul 24 05:17:10 PM PDT 24
Peak memory 197128 kb
Host smart-0dac811b-b21f-4a95-adce-e3021522dafc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302221708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.302221708
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1210300792
Short name T371
Test name
Test status
Simulation time 21330305667 ps
CPU time 105.58 seconds
Started Jul 24 05:17:13 PM PDT 24
Finished Jul 24 05:18:59 PM PDT 24
Peak memory 198660 kb
Host smart-d5bb4f86-685c-4087-af27-760cc5223bee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210300792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1210300792
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3183764498
Short name T686
Test name
Test status
Simulation time 183837433308 ps
CPU time 822.06 seconds
Started Jul 24 05:17:08 PM PDT 24
Finished Jul 24 05:30:50 PM PDT 24
Peak memory 198764 kb
Host smart-115dfb49-7eb9-4c1d-af33-2afe2ca7e8e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3183764498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3183764498
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2541581574
Short name T344
Test name
Test status
Simulation time 12357214 ps
CPU time 0.55 seconds
Started Jul 24 05:17:21 PM PDT 24
Finished Jul 24 05:17:22 PM PDT 24
Peak memory 194272 kb
Host smart-e07306e9-4dec-4e41-ac86-c4759f70dcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541581574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2541581574
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3979278681
Short name T548
Test name
Test status
Simulation time 24231084 ps
CPU time 0.71 seconds
Started Jul 24 05:17:21 PM PDT 24
Finished Jul 24 05:17:22 PM PDT 24
Peak memory 194548 kb
Host smart-48069ab1-ffc2-46be-9eef-7eae1967a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979278681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3979278681
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.858609571
Short name T353
Test name
Test status
Simulation time 425484526 ps
CPU time 22.07 seconds
Started Jul 24 05:17:09 PM PDT 24
Finished Jul 24 05:17:32 PM PDT 24
Peak memory 198484 kb
Host smart-d63d6639-b133-4897-954a-c075bd5507d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858609571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.858609571
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3653060948
Short name T173
Test name
Test status
Simulation time 47703895 ps
CPU time 0.81 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 196452 kb
Host smart-ecfb2cd3-7a1c-416c-8b1e-bfd0cf07b1b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653060948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3653060948
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3849655397
Short name T669
Test name
Test status
Simulation time 105519549 ps
CPU time 1.41 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 197720 kb
Host smart-69ab4be8-4154-4906-aca2-5239dfa4ad56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849655397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3849655397
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1426319729
Short name T194
Test name
Test status
Simulation time 165938104 ps
CPU time 3.93 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 198652 kb
Host smart-b83d0e90-12d1-4ea6-ab7e-12ebd1127f7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426319729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1426319729
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1816432412
Short name T608
Test name
Test status
Simulation time 337904327 ps
CPU time 1.86 seconds
Started Jul 24 05:17:29 PM PDT 24
Finished Jul 24 05:17:31 PM PDT 24
Peak memory 197388 kb
Host smart-e3a486d3-2562-4326-b4f2-f23b62ec8f8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816432412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1816432412
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.392704818
Short name T305
Test name
Test status
Simulation time 57076204 ps
CPU time 1.25 seconds
Started Jul 24 05:17:17 PM PDT 24
Finished Jul 24 05:17:19 PM PDT 24
Peak memory 197544 kb
Host smart-a7c8e81e-9ecc-4496-8527-d78af658ac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392704818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.392704818
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.120299444
Short name T502
Test name
Test status
Simulation time 31825280 ps
CPU time 0.83 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 197576 kb
Host smart-39461ee7-863b-4824-b2ae-926d743b21da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120299444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.120299444
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2492324026
Short name T159
Test name
Test status
Simulation time 321909010 ps
CPU time 5.16 seconds
Started Jul 24 05:17:21 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 198512 kb
Host smart-4e24f197-e102-4c81-bc7e-1fa1fd29e2c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492324026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2492324026
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3502994814
Short name T55
Test name
Test status
Simulation time 72334181 ps
CPU time 0.9 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:25 PM PDT 24
Peak memory 196868 kb
Host smart-0c8f644d-e723-4c85-8d6f-9823ecac8475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502994814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3502994814
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3153569104
Short name T213
Test name
Test status
Simulation time 379601884 ps
CPU time 1.47 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:25 PM PDT 24
Peak memory 197348 kb
Host smart-13abe914-a4b2-46a4-93a2-ae539462bc13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153569104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3153569104
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1500477643
Short name T277
Test name
Test status
Simulation time 20620809893 ps
CPU time 117.65 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:19:22 PM PDT 24
Peak memory 198608 kb
Host smart-14f44bf8-a32b-4edf-8c7f-10d297c933cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500477643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1500477643
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3387598933
Short name T175
Test name
Test status
Simulation time 101917368 ps
CPU time 0.55 seconds
Started Jul 24 05:17:11 PM PDT 24
Finished Jul 24 05:17:12 PM PDT 24
Peak memory 195080 kb
Host smart-e7eeebf2-b7c6-40fa-80ec-757631798bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387598933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3387598933
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.81741256
Short name T564
Test name
Test status
Simulation time 40506265 ps
CPU time 0.83 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 195884 kb
Host smart-7fd22037-5355-4117-9e81-2e3e369b5871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81741256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.81741256
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3661838785
Short name T162
Test name
Test status
Simulation time 2454666338 ps
CPU time 17.97 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:59 PM PDT 24
Peak memory 197172 kb
Host smart-8d6dbda7-c544-413d-97ac-be5ece56f834
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661838785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3661838785
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.4192770782
Short name T345
Test name
Test status
Simulation time 89157884 ps
CPU time 1.07 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 196868 kb
Host smart-9eb8f69c-edc2-445d-9502-a95b94742fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192770782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.4192770782
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3399821571
Short name T535
Test name
Test status
Simulation time 311926806 ps
CPU time 1.37 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 197488 kb
Host smart-3a0af477-f077-45ad-a517-90b86721f214
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399821571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3399821571
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2111117407
Short name T307
Test name
Test status
Simulation time 95978045 ps
CPU time 2.04 seconds
Started Jul 24 05:17:19 PM PDT 24
Finished Jul 24 05:17:21 PM PDT 24
Peak memory 198500 kb
Host smart-26b5ac6e-e941-4e80-a762-48f231812eac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111117407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2111117407
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.173113547
Short name T475
Test name
Test status
Simulation time 44774765 ps
CPU time 1.06 seconds
Started Jul 24 05:17:31 PM PDT 24
Finished Jul 24 05:17:32 PM PDT 24
Peak memory 196096 kb
Host smart-7cce08a8-1434-40f3-9533-d37af5bbf014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173113547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
173113547
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3297597482
Short name T651
Test name
Test status
Simulation time 46401166 ps
CPU time 1.12 seconds
Started Jul 24 05:17:18 PM PDT 24
Finished Jul 24 05:17:20 PM PDT 24
Peak memory 197188 kb
Host smart-d0f0ebc6-c6ff-4718-9fa3-760d1d298f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297597482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3297597482
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2607609151
Short name T385
Test name
Test status
Simulation time 112857548 ps
CPU time 0.75 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 195928 kb
Host smart-a3959021-38a3-4e02-a717-a354c85d2458
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607609151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2607609151
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1908533176
Short name T45
Test name
Test status
Simulation time 40719034 ps
CPU time 1.75 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:25 PM PDT 24
Peak memory 198444 kb
Host smart-f310a89c-8c39-4b21-9480-bd4e0c797aae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908533176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1908533176
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3507610210
Short name T184
Test name
Test status
Simulation time 32494267 ps
CPU time 0.77 seconds
Started Jul 24 05:17:22 PM PDT 24
Finished Jul 24 05:17:23 PM PDT 24
Peak memory 195620 kb
Host smart-f046ea31-ebc2-4231-967b-4a24641d8228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507610210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3507610210
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3780315246
Short name T495
Test name
Test status
Simulation time 87432703 ps
CPU time 0.98 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 196340 kb
Host smart-dfb49ad2-e0f6-4168-9c08-1cb930eaa61f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780315246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3780315246
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.16751180
Short name T301
Test name
Test status
Simulation time 35849540796 ps
CPU time 118.59 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:19:26 PM PDT 24
Peak memory 198640 kb
Host smart-65f10824-f8ca-49ea-a22b-405e93f9e0a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16751180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gp
io_stress_all.16751180
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1949979042
Short name T575
Test name
Test status
Simulation time 26104650 ps
CPU time 0.57 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:39 PM PDT 24
Peak memory 194540 kb
Host smart-427b483a-606c-4b67-96d7-0f99dcd3b2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949979042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1949979042
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.4277946796
Short name T354
Test name
Test status
Simulation time 26731778 ps
CPU time 0.72 seconds
Started Jul 24 05:17:28 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 195688 kb
Host smart-80924b35-f3d4-4183-9fc6-b71cdcf72a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277946796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.4277946796
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1808423317
Short name T660
Test name
Test status
Simulation time 335027385 ps
CPU time 5.01 seconds
Started Jul 24 05:17:22 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 198528 kb
Host smart-d021f618-6b7d-4eda-b088-c66bf6d9554a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808423317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1808423317
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.440476511
Short name T524
Test name
Test status
Simulation time 588417070 ps
CPU time 1.12 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 197000 kb
Host smart-9290c9f3-c30e-4eeb-80b8-afbe5262d1e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440476511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.440476511
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.4087887745
Short name T574
Test name
Test status
Simulation time 23577570 ps
CPU time 0.81 seconds
Started Jul 24 05:17:21 PM PDT 24
Finished Jul 24 05:17:22 PM PDT 24
Peak memory 195940 kb
Host smart-9fac72ad-de87-4cfb-ba32-4165d692777a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087887745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.4087887745
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.307439403
Short name T313
Test name
Test status
Simulation time 47813800 ps
CPU time 1.91 seconds
Started Jul 24 05:17:19 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 197024 kb
Host smart-bf9a3591-69d3-4009-9308-49b9ce172e01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307439403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.307439403
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.989847658
Short name T427
Test name
Test status
Simulation time 300369617 ps
CPU time 3.27 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 196368 kb
Host smart-082508d1-36c6-4bec-88cb-15faff78e027
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989847658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
989847658
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3259871034
Short name T425
Test name
Test status
Simulation time 27739429 ps
CPU time 1.02 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:25 PM PDT 24
Peak memory 196472 kb
Host smart-997fb252-a4da-42ca-a720-67d8b17ad28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259871034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3259871034
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1385859759
Short name T129
Test name
Test status
Simulation time 67401576 ps
CPU time 1.3 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 198548 kb
Host smart-57e81618-21a0-4016-83a1-ce6cc0098dcb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385859759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1385859759
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2759022903
Short name T62
Test name
Test status
Simulation time 61638613 ps
CPU time 1.34 seconds
Started Jul 24 05:17:07 PM PDT 24
Finished Jul 24 05:17:08 PM PDT 24
Peak memory 198484 kb
Host smart-873c2ec6-ca38-4688-bf80-e148edcc9432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759022903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2759022903
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.749706786
Short name T614
Test name
Test status
Simulation time 90021219 ps
CPU time 1.27 seconds
Started Jul 24 05:17:22 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 197560 kb
Host smart-4d0c0711-7f81-493a-907f-24bf84af6fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749706786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.749706786
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2496298802
Short name T191
Test name
Test status
Simulation time 218897867 ps
CPU time 1.44 seconds
Started Jul 24 05:17:12 PM PDT 24
Finished Jul 24 05:17:14 PM PDT 24
Peak memory 197324 kb
Host smart-db74a363-9f52-42c2-9c1d-883f30153b72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496298802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2496298802
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.919433419
Short name T99
Test name
Test status
Simulation time 50926357438 ps
CPU time 62.14 seconds
Started Jul 24 05:17:20 PM PDT 24
Finished Jul 24 05:18:22 PM PDT 24
Peak memory 198636 kb
Host smart-6c7f775c-e9c8-4eb7-a5c6-e2f0dd156c0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919433419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.919433419
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.4087528266
Short name T663
Test name
Test status
Simulation time 19439969 ps
CPU time 0.57 seconds
Started Jul 24 05:17:28 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 195080 kb
Host smart-151e24fd-43cf-4da5-96c3-4222ac90c325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087528266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.4087528266
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.441187059
Short name T309
Test name
Test status
Simulation time 52459031 ps
CPU time 0.57 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 194272 kb
Host smart-b1ac233f-3340-4d53-97a3-15bf11eadbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441187059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.441187059
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2578897390
Short name T365
Test name
Test status
Simulation time 1006082777 ps
CPU time 10.23 seconds
Started Jul 24 05:19:12 PM PDT 24
Finished Jul 24 05:19:23 PM PDT 24
Peak memory 196972 kb
Host smart-18b4b0ad-680d-4f84-a0f6-b7d4a2035665
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578897390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2578897390
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2963917690
Short name T430
Test name
Test status
Simulation time 172299195 ps
CPU time 0.8 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 196200 kb
Host smart-063a939c-5600-42d4-a7be-606c36633fc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963917690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2963917690
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2263175335
Short name T578
Test name
Test status
Simulation time 387035346 ps
CPU time 1.28 seconds
Started Jul 24 05:17:35 PM PDT 24
Finished Jul 24 05:17:36 PM PDT 24
Peak memory 197560 kb
Host smart-17f0504c-0de3-4df2-bd1e-6739b66a1389
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263175335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2263175335
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1829058870
Short name T16
Test name
Test status
Simulation time 285517699 ps
CPU time 2.16 seconds
Started Jul 24 05:17:37 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 196268 kb
Host smart-23494e0c-6740-445d-bd3e-f9cc358ed961
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829058870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1829058870
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3863848160
Short name T717
Test name
Test status
Simulation time 13898221 ps
CPU time 0.67 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 195364 kb
Host smart-5268a931-8b8a-48d5-a35e-8dbaddf093bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863848160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3863848160
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2642129261
Short name T321
Test name
Test status
Simulation time 52089659 ps
CPU time 1.09 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 196424 kb
Host smart-47e829bb-3bff-44ce-aa34-3e60638810fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642129261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2642129261
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2001044008
Short name T447
Test name
Test status
Simulation time 57649240 ps
CPU time 1.43 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:30 PM PDT 24
Peak memory 198344 kb
Host smart-4a1fd387-4f8e-4c2f-9b14-0f9376c1e61a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001044008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2001044008
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2144314760
Short name T308
Test name
Test status
Simulation time 60402760 ps
CPU time 1 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 196192 kb
Host smart-88daf4be-a617-410f-b8b6-86304e052732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144314760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2144314760
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.392583949
Short name T473
Test name
Test status
Simulation time 323811371 ps
CPU time 0.97 seconds
Started Jul 24 05:17:22 PM PDT 24
Finished Jul 24 05:17:23 PM PDT 24
Peak memory 196016 kb
Host smart-4a04d8bb-22e2-4661-9fd0-2fe492e2f61c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392583949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.392583949
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3428911315
Short name T318
Test name
Test status
Simulation time 5454887460 ps
CPU time 77.94 seconds
Started Jul 24 05:17:35 PM PDT 24
Finished Jul 24 05:18:53 PM PDT 24
Peak memory 198636 kb
Host smart-3c4e8343-f210-4c03-8996-f1a32b8908f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428911315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3428911315
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3428614726
Short name T338
Test name
Test status
Simulation time 111823838927 ps
CPU time 1277.62 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:38:58 PM PDT 24
Peak memory 198740 kb
Host smart-6e5cfd60-efce-4358-8f20-f0b10d29ae8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3428614726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3428614726
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2418386562
Short name T196
Test name
Test status
Simulation time 40711911 ps
CPU time 0.56 seconds
Started Jul 24 05:17:35 PM PDT 24
Finished Jul 24 05:17:36 PM PDT 24
Peak memory 195108 kb
Host smart-65cae886-0353-409a-bfdd-3da639addf08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418386562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2418386562
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2846626297
Short name T690
Test name
Test status
Simulation time 116222580 ps
CPU time 0.96 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 197124 kb
Host smart-21a19087-fae0-42f5-b764-62dd0fb15e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846626297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2846626297
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.666486680
Short name T488
Test name
Test status
Simulation time 1287946492 ps
CPU time 11.42 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:37 PM PDT 24
Peak memory 197544 kb
Host smart-dc45c97c-110e-43eb-bf9b-6d8866aa1605
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666486680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.666486680
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2623176327
Short name T18
Test name
Test status
Simulation time 167140335 ps
CPU time 0.8 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:39 PM PDT 24
Peak memory 195208 kb
Host smart-dcd60492-9fc5-4c29-8c46-634d5e66762c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623176327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2623176327
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1841393448
Short name T103
Test name
Test status
Simulation time 22786551 ps
CPU time 0.82 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 196104 kb
Host smart-5e9b13b4-d75b-418e-aeb1-1bfd20f02e6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841393448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1841393448
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1064987376
Short name T465
Test name
Test status
Simulation time 380807939 ps
CPU time 2.12 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 198536 kb
Host smart-7b9eeff4-f62a-41df-a05b-4008a1cb89b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064987376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1064987376
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.850866269
Short name T267
Test name
Test status
Simulation time 92858169 ps
CPU time 2.62 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 197768 kb
Host smart-c37bbb2c-99b6-41d3-81cf-deccd0eb27f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850866269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
850866269
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2197084577
Short name T292
Test name
Test status
Simulation time 113167706 ps
CPU time 1.28 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 198568 kb
Host smart-41571754-bd42-430b-8757-0f8a78718795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197084577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2197084577
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.625853508
Short name T331
Test name
Test status
Simulation time 152652495 ps
CPU time 0.69 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:25 PM PDT 24
Peak memory 194772 kb
Host smart-43c3cf9f-14e9-48f0-b052-71937b0a3c58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625853508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.625853508
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.470787153
Short name T145
Test name
Test status
Simulation time 288279868 ps
CPU time 4.7 seconds
Started Jul 24 05:17:16 PM PDT 24
Finished Jul 24 05:17:21 PM PDT 24
Peak memory 198356 kb
Host smart-a4e7dc11-41ed-4c30-9496-1897670a817b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470787153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.470787153
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.972529222
Short name T299
Test name
Test status
Simulation time 79714861 ps
CPU time 1.05 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:48 PM PDT 24
Peak memory 196916 kb
Host smart-d5c64f31-36fe-4871-b5c1-9d8c381e81f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972529222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.972529222
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2176721994
Short name T273
Test name
Test status
Simulation time 37799343 ps
CPU time 0.87 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 195856 kb
Host smart-16acc4a2-fcf7-4ff2-a798-144af122456c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176721994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2176721994
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1474758132
Short name T635
Test name
Test status
Simulation time 8449780208 ps
CPU time 202.46 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:20:47 PM PDT 24
Peak memory 198668 kb
Host smart-3191a566-d486-414b-86a5-bea109a2152c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474758132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1474758132
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1553743254
Short name T422
Test name
Test status
Simulation time 20446394 ps
CPU time 0.56 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:49 PM PDT 24
Peak memory 194368 kb
Host smart-5155cb60-ffce-4596-b49e-99837be971fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553743254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1553743254
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3677777372
Short name T407
Test name
Test status
Simulation time 134518690 ps
CPU time 0.79 seconds
Started Jul 24 05:16:31 PM PDT 24
Finished Jul 24 05:16:32 PM PDT 24
Peak memory 195736 kb
Host smart-1802040e-f493-48ba-978e-3ccfb657d610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677777372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3677777372
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3961852076
Short name T521
Test name
Test status
Simulation time 1007167182 ps
CPU time 19.5 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:17:04 PM PDT 24
Peak memory 197464 kb
Host smart-4aa240a5-e5fa-4a18-b126-0b0c6387e16f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961852076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3961852076
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2360931326
Short name T352
Test name
Test status
Simulation time 323197688 ps
CPU time 0.96 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:49 PM PDT 24
Peak memory 198300 kb
Host smart-d4c87b30-271b-4c4c-96f2-e10e83f9f36c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360931326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2360931326
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1212051195
Short name T235
Test name
Test status
Simulation time 61245135 ps
CPU time 0.95 seconds
Started Jul 24 05:16:34 PM PDT 24
Finished Jul 24 05:16:35 PM PDT 24
Peak memory 196192 kb
Host smart-32d03fdd-5e62-41df-b308-389bfb28f761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212051195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1212051195
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.337598224
Short name T17
Test name
Test status
Simulation time 97347575 ps
CPU time 1.19 seconds
Started Jul 24 05:16:34 PM PDT 24
Finished Jul 24 05:16:36 PM PDT 24
Peak memory 196848 kb
Host smart-77d0ba68-5521-45a0-b425-ddf4b7998cad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337598224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.337598224
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3196612802
Short name T550
Test name
Test status
Simulation time 313700588 ps
CPU time 2.91 seconds
Started Jul 24 05:16:36 PM PDT 24
Finished Jul 24 05:16:39 PM PDT 24
Peak memory 196416 kb
Host smart-91a202d9-61fa-4b85-9d66-4f976244e4ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196612802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3196612802
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3217506988
Short name T621
Test name
Test status
Simulation time 109061919 ps
CPU time 0.71 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:16:37 PM PDT 24
Peak memory 195776 kb
Host smart-0c322434-5394-469b-8f22-b013c0810238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217506988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3217506988
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3881812854
Short name T294
Test name
Test status
Simulation time 65605267 ps
CPU time 0.91 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:16:36 PM PDT 24
Peak memory 196480 kb
Host smart-f36e458a-9d0e-46e2-a7b4-991f0aaa47fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881812854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3881812854
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.429552659
Short name T384
Test name
Test status
Simulation time 290704698 ps
CPU time 3.42 seconds
Started Jul 24 05:16:58 PM PDT 24
Finished Jul 24 05:17:02 PM PDT 24
Peak memory 198436 kb
Host smart-fa8a6ec8-3ea3-4608-9a30-1232c9a0ab88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429552659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.429552659
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.290499752
Short name T43
Test name
Test status
Simulation time 37288893 ps
CPU time 0.83 seconds
Started Jul 24 05:16:31 PM PDT 24
Finished Jul 24 05:16:32 PM PDT 24
Peak memory 214292 kb
Host smart-9ce7d03d-bd0b-4ab9-99c9-ef5392093778
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290499752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.290499752
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.470841647
Short name T511
Test name
Test status
Simulation time 77519873 ps
CPU time 1.34 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:16:36 PM PDT 24
Peak memory 197260 kb
Host smart-07ffd416-14fb-4914-a165-0f3da336de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470841647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.470841647
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2974965647
Short name T262
Test name
Test status
Simulation time 132376524 ps
CPU time 1.29 seconds
Started Jul 24 05:16:36 PM PDT 24
Finished Jul 24 05:16:38 PM PDT 24
Peak memory 197276 kb
Host smart-d93cce13-b46d-4a1f-bfc1-0abeeaeb13d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974965647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2974965647
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1289317722
Short name T1
Test name
Test status
Simulation time 59769763106 ps
CPU time 159.65 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 198600 kb
Host smart-57343206-2fa1-4f6e-b9ee-f8379297a632
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289317722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1289317722
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.531006043
Short name T20
Test name
Test status
Simulation time 66431940506 ps
CPU time 1234.23 seconds
Started Jul 24 05:16:53 PM PDT 24
Finished Jul 24 05:37:28 PM PDT 24
Peak memory 198696 kb
Host smart-41b9a9e6-cce0-474c-99c4-b4f761cec964
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=531006043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.531006043
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1471254194
Short name T297
Test name
Test status
Simulation time 11335704 ps
CPU time 0.56 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 194384 kb
Host smart-7d259414-84fa-4817-8c3b-b429c205132e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471254194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1471254194
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3830545969
Short name T193
Test name
Test status
Simulation time 100253109 ps
CPU time 0.96 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 196428 kb
Host smart-fad7a576-59f5-473d-b3cc-8a2a56885413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830545969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3830545969
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1900659903
Short name T599
Test name
Test status
Simulation time 1654337355 ps
CPU time 28.13 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:18:14 PM PDT 24
Peak memory 197276 kb
Host smart-3451ce6c-414f-47f1-b443-75041178c993
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900659903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1900659903
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2330029234
Short name T14
Test name
Test status
Simulation time 42697013 ps
CPU time 0.74 seconds
Started Jul 24 05:17:29 PM PDT 24
Finished Jul 24 05:17:30 PM PDT 24
Peak memory 196012 kb
Host smart-9ac06dad-7a6b-4d84-ac54-983fd6ba517f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330029234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2330029234
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.4240337494
Short name T123
Test name
Test status
Simulation time 41117514 ps
CPU time 0.68 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 195504 kb
Host smart-885e7fd5-df4d-4495-8567-d736bd539ed3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240337494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.4240337494
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1322075718
Short name T703
Test name
Test status
Simulation time 166150253 ps
CPU time 3.13 seconds
Started Jul 24 05:17:29 PM PDT 24
Finished Jul 24 05:17:32 PM PDT 24
Peak memory 197008 kb
Host smart-6b9462df-b7f3-4b90-b1df-6017538e11e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322075718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1322075718
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3208078633
Short name T243
Test name
Test status
Simulation time 286264308 ps
CPU time 1.69 seconds
Started Jul 24 05:17:21 PM PDT 24
Finished Jul 24 05:17:23 PM PDT 24
Peak memory 197004 kb
Host smart-83437fc5-02f2-44f5-9e1d-5dbd24df8893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208078633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3208078633
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.269359637
Short name T54
Test name
Test status
Simulation time 35230091 ps
CPU time 0.95 seconds
Started Jul 24 05:17:31 PM PDT 24
Finished Jul 24 05:17:32 PM PDT 24
Peak memory 196532 kb
Host smart-5ee8dd72-a06e-415e-8ae5-0c0048273bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269359637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.269359637
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2842232534
Short name T226
Test name
Test status
Simulation time 71300211 ps
CPU time 1.27 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 198580 kb
Host smart-d3f8f85e-db9d-413d-9afb-fb0209c411a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842232534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2842232534
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3986529149
Short name T503
Test name
Test status
Simulation time 660749710 ps
CPU time 5.24 seconds
Started Jul 24 05:17:24 PM PDT 24
Finished Jul 24 05:17:30 PM PDT 24
Peak memory 198452 kb
Host smart-25a13e87-bf6a-4115-9eb1-ada80f654e42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986529149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3986529149
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1299984741
Short name T287
Test name
Test status
Simulation time 25556985 ps
CPU time 0.75 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 194680 kb
Host smart-45d258ec-99c0-434f-9227-ab4c36ea4e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299984741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1299984741
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1905206416
Short name T664
Test name
Test status
Simulation time 36422270 ps
CPU time 1.05 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 196368 kb
Host smart-f4c76859-59e6-4ebf-85d4-71fcd00b1ede
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905206416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1905206416
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2115029361
Short name T470
Test name
Test status
Simulation time 2531202897 ps
CPU time 51.36 seconds
Started Jul 24 05:17:31 PM PDT 24
Finished Jul 24 05:18:22 PM PDT 24
Peak memory 198616 kb
Host smart-0b94abd8-ec55-4994-862e-50bcd9b1a9b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115029361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2115029361
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.554208468
Short name T580
Test name
Test status
Simulation time 72501880 ps
CPU time 0.58 seconds
Started Jul 24 05:17:30 PM PDT 24
Finished Jul 24 05:17:31 PM PDT 24
Peak memory 194568 kb
Host smart-b4b2a2cc-43e0-44a8-9ece-450316d70680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554208468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.554208468
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2890024714
Short name T209
Test name
Test status
Simulation time 32751135 ps
CPU time 0.8 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 196356 kb
Host smart-d3b5b217-a6a5-44a5-8427-1d8fd6179359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890024714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2890024714
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.4033485594
Short name T289
Test name
Test status
Simulation time 310287774 ps
CPU time 16.11 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:17:43 PM PDT 24
Peak memory 198480 kb
Host smart-050bbb61-e782-48ea-9a28-0f60d21b3127
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033485594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.4033485594
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3813244018
Short name T705
Test name
Test status
Simulation time 120849411 ps
CPU time 1.04 seconds
Started Jul 24 05:17:33 PM PDT 24
Finished Jul 24 05:17:34 PM PDT 24
Peak memory 197124 kb
Host smart-ac222ce0-7966-4820-a7d4-0845167f9547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813244018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3813244018
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2839163276
Short name T665
Test name
Test status
Simulation time 360566348 ps
CPU time 1.4 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 198508 kb
Host smart-eff03c95-19e8-422b-afa8-d20eef3ee50c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839163276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2839163276
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1677093806
Short name T567
Test name
Test status
Simulation time 213382637 ps
CPU time 2.11 seconds
Started Jul 24 05:17:32 PM PDT 24
Finished Jul 24 05:17:34 PM PDT 24
Peak memory 198560 kb
Host smart-a62c7fa6-9e50-4ec9-af6f-24874aa98330
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677093806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1677093806
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1742526128
Short name T411
Test name
Test status
Simulation time 1211244033 ps
CPU time 1.66 seconds
Started Jul 24 05:17:28 PM PDT 24
Finished Jul 24 05:17:30 PM PDT 24
Peak memory 197336 kb
Host smart-4cf67a2a-e44c-4e63-9ffa-e348962fa495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742526128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1742526128
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1040722037
Short name T460
Test name
Test status
Simulation time 118494827 ps
CPU time 1.05 seconds
Started Jul 24 05:17:35 PM PDT 24
Finished Jul 24 05:17:36 PM PDT 24
Peak memory 196488 kb
Host smart-4c595966-2f14-4dd2-8293-19da82b3e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040722037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1040722037
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2300008954
Short name T693
Test name
Test status
Simulation time 36581409 ps
CPU time 1.29 seconds
Started Jul 24 05:17:22 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 197604 kb
Host smart-f4eb06c2-b431-455a-889a-b8b614f55ff7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300008954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2300008954
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1030256899
Short name T477
Test name
Test status
Simulation time 5049204015 ps
CPU time 6.19 seconds
Started Jul 24 05:17:37 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 198520 kb
Host smart-cd319621-6b3e-43db-a728-d50298edd600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030256899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1030256899
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3445995598
Short name T709
Test name
Test status
Simulation time 59578971 ps
CPU time 1.2 seconds
Started Jul 24 05:17:32 PM PDT 24
Finished Jul 24 05:17:33 PM PDT 24
Peak memory 197384 kb
Host smart-201e63f2-cecc-4978-aacb-bdd1ff814d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445995598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3445995598
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.423180284
Short name T396
Test name
Test status
Simulation time 30219892 ps
CPU time 0.79 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 196356 kb
Host smart-664365c5-f740-4e83-a061-7ef4586c1d21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423180284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.423180284
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1055998383
Short name T388
Test name
Test status
Simulation time 20280228151 ps
CPU time 137.67 seconds
Started Jul 24 05:17:21 PM PDT 24
Finished Jul 24 05:19:39 PM PDT 24
Peak memory 198604 kb
Host smart-4a1e2d75-6a4b-447a-821e-2916a3b346c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055998383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1055998383
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.397413337
Short name T469
Test name
Test status
Simulation time 85023210424 ps
CPU time 1717.14 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:46:03 PM PDT 24
Peak memory 198736 kb
Host smart-9177733d-585a-4ad6-8be4-35633a735441
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=397413337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.397413337
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1161404349
Short name T185
Test name
Test status
Simulation time 42081110 ps
CPU time 0.55 seconds
Started Jul 24 05:17:34 PM PDT 24
Finished Jul 24 05:17:35 PM PDT 24
Peak memory 194376 kb
Host smart-fa200a35-3dd9-47ac-aa46-992d591be5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161404349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1161404349
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2892365931
Short name T633
Test name
Test status
Simulation time 25079625 ps
CPU time 0.8 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 195956 kb
Host smart-480dacfa-a061-4ca6-aeb3-280e529fcc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892365931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2892365931
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2551137122
Short name T254
Test name
Test status
Simulation time 437223668 ps
CPU time 10 seconds
Started Jul 24 05:17:30 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 197228 kb
Host smart-1044085f-f160-4598-8007-3e2beafae4ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551137122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2551137122
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.4144537999
Short name T216
Test name
Test status
Simulation time 579902414 ps
CPU time 0.87 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 196172 kb
Host smart-59af0d93-2587-4182-8563-6721656152c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144537999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.4144537999
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3637581590
Short name T90
Test name
Test status
Simulation time 177850128 ps
CPU time 1.32 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 197348 kb
Host smart-429cc637-2eac-4ff7-b220-2519a4b58b61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637581590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3637581590
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.445881543
Short name T677
Test name
Test status
Simulation time 91523537 ps
CPU time 2.5 seconds
Started Jul 24 05:17:32 PM PDT 24
Finished Jul 24 05:17:35 PM PDT 24
Peak memory 198524 kb
Host smart-c3be311e-a761-4172-a769-3a04f5e9f5ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445881543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.445881543
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.557498773
Short name T219
Test name
Test status
Simulation time 41308331 ps
CPU time 1.12 seconds
Started Jul 24 05:17:35 PM PDT 24
Finished Jul 24 05:17:36 PM PDT 24
Peak memory 196220 kb
Host smart-28275cec-c4ae-465b-b368-c53d1c8a4702
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557498773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
557498773
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3157630512
Short name T542
Test name
Test status
Simulation time 135363895 ps
CPU time 1.09 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 196332 kb
Host smart-b219b101-f804-49ff-93b8-40f3e24efaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157630512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3157630512
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2375442570
Short name T494
Test name
Test status
Simulation time 27439156 ps
CPU time 0.79 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:38 PM PDT 24
Peak memory 195872 kb
Host smart-10dc5fa2-c390-4cff-b59a-71709d7cdb51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375442570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2375442570
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3104825782
Short name T317
Test name
Test status
Simulation time 81018965 ps
CPU time 3.53 seconds
Started Jul 24 05:17:33 PM PDT 24
Finished Jul 24 05:17:36 PM PDT 24
Peak memory 198496 kb
Host smart-6d227202-4af1-4318-b77f-e05504fb539a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104825782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3104825782
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3701986890
Short name T485
Test name
Test status
Simulation time 323019167 ps
CPU time 0.95 seconds
Started Jul 24 05:17:33 PM PDT 24
Finished Jul 24 05:17:34 PM PDT 24
Peak memory 196060 kb
Host smart-b36044fb-8c8a-45ec-9892-b59cf8cb858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701986890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3701986890
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3120887210
Short name T225
Test name
Test status
Simulation time 57655678 ps
CPU time 0.97 seconds
Started Jul 24 05:17:21 PM PDT 24
Finished Jul 24 05:17:22 PM PDT 24
Peak memory 196020 kb
Host smart-1d8f9acc-850e-4169-b6db-1e7a27f7ba54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120887210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3120887210
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1612473503
Short name T2
Test name
Test status
Simulation time 19713050941 ps
CPU time 209.83 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:21:15 PM PDT 24
Peak memory 198660 kb
Host smart-0068a435-6d21-4d31-b376-3569da8a38b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612473503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1612473503
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.755860349
Short name T281
Test name
Test status
Simulation time 79012525848 ps
CPU time 826.35 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:31:13 PM PDT 24
Peak memory 198748 kb
Host smart-f3a6b28e-4f26-4ed2-b9ba-ffbafa10325f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=755860349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.755860349
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3441882551
Short name T662
Test name
Test status
Simulation time 141420827 ps
CPU time 0.59 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 194668 kb
Host smart-40d3ebd8-57cb-4581-ba70-41a3add015f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441882551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3441882551
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3208563379
Short name T234
Test name
Test status
Simulation time 53118566 ps
CPU time 0.66 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 195232 kb
Host smart-134f1e7f-3f6d-450e-a3e8-0cdec663086a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208563379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3208563379
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.919616025
Short name T197
Test name
Test status
Simulation time 386699175 ps
CPU time 18.83 seconds
Started Jul 24 05:17:30 PM PDT 24
Finished Jul 24 05:17:49 PM PDT 24
Peak memory 196876 kb
Host smart-b6211c2c-33a1-48f1-bb94-6ba7e70538ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919616025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.919616025
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2597429582
Short name T101
Test name
Test status
Simulation time 113622519 ps
CPU time 0.99 seconds
Started Jul 24 05:17:23 PM PDT 24
Finished Jul 24 05:17:24 PM PDT 24
Peak memory 197296 kb
Host smart-b211f89b-8396-4d9b-a071-ea7b4b0adde3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597429582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2597429582
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.488915
Short name T424
Test name
Test status
Simulation time 141087573 ps
CPU time 0.87 seconds
Started Jul 24 05:17:28 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 197388 kb
Host smart-3c133ed6-90c9-4d4a-a6cc-ea509d9d6758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.488915
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3461882614
Short name T448
Test name
Test status
Simulation time 438262788 ps
CPU time 1.27 seconds
Started Jul 24 05:17:29 PM PDT 24
Finished Jul 24 05:17:31 PM PDT 24
Peak memory 197096 kb
Host smart-1f3965c6-0701-4797-b884-a0575cc5f639
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461882614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3461882614
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1312062125
Short name T221
Test name
Test status
Simulation time 840693772 ps
CPU time 2.73 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 198548 kb
Host smart-00724b6e-76b1-4d59-9a3c-9288b48e5c42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312062125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1312062125
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3333749374
Short name T449
Test name
Test status
Simulation time 48644860 ps
CPU time 1.17 seconds
Started Jul 24 05:17:29 PM PDT 24
Finished Jul 24 05:17:30 PM PDT 24
Peak memory 197284 kb
Host smart-8738fd13-4edb-4f90-819e-f2f0c616518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333749374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3333749374
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1768234797
Short name T520
Test name
Test status
Simulation time 36545374 ps
CPU time 1.28 seconds
Started Jul 24 05:17:28 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 197460 kb
Host smart-211072f6-5090-4bf6-9dfa-3edf9e652a96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768234797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1768234797
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1024127507
Short name T394
Test name
Test status
Simulation time 183559044 ps
CPU time 2.31 seconds
Started Jul 24 05:17:33 PM PDT 24
Finished Jul 24 05:17:36 PM PDT 24
Peak memory 198384 kb
Host smart-66ffbf9a-e54f-4a29-be43-49dbbc54ad15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024127507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1024127507
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.4058613161
Short name T160
Test name
Test status
Simulation time 46013643 ps
CPU time 0.94 seconds
Started Jul 24 05:17:33 PM PDT 24
Finished Jul 24 05:17:34 PM PDT 24
Peak memory 196848 kb
Host smart-f5e2c333-1a54-43f2-8f78-9f5c5cb975c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058613161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.4058613161
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.21949966
Short name T118
Test name
Test status
Simulation time 61998610 ps
CPU time 1.23 seconds
Started Jul 24 05:17:28 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 197172 kb
Host smart-2ca7e63e-b600-44fe-937a-591d2ddd10da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21949966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.21949966
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.790977761
Short name T122
Test name
Test status
Simulation time 9522146217 ps
CPU time 61.37 seconds
Started Jul 24 05:17:34 PM PDT 24
Finished Jul 24 05:18:35 PM PDT 24
Peak memory 198632 kb
Host smart-24d56cce-d6db-47f5-a8bf-59894070496d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790977761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.790977761
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1742676131
Short name T387
Test name
Test status
Simulation time 80546933418 ps
CPU time 628.79 seconds
Started Jul 24 05:17:19 PM PDT 24
Finished Jul 24 05:27:48 PM PDT 24
Peak memory 198788 kb
Host smart-3cf7f542-f9dd-46c1-8a5d-6c643628c714
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1742676131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1742676131
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2212619424
Short name T306
Test name
Test status
Simulation time 37272304 ps
CPU time 0.6 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:39 PM PDT 24
Peak memory 195260 kb
Host smart-1ceb2eb1-b0f4-47e0-8aab-a60b9bb7ec25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212619424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2212619424
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2485926062
Short name T571
Test name
Test status
Simulation time 31619764 ps
CPU time 0.61 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:41 PM PDT 24
Peak memory 194480 kb
Host smart-aa3f6bf5-2c70-459c-a036-f278970e3cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485926062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2485926062
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1880267536
Short name T588
Test name
Test status
Simulation time 1508033554 ps
CPU time 23.06 seconds
Started Jul 24 05:17:34 PM PDT 24
Finished Jul 24 05:17:57 PM PDT 24
Peak memory 198476 kb
Host smart-209eb73a-8d9d-4508-b007-0fbc1f1a61ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880267536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1880267536
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2217828553
Short name T467
Test name
Test status
Simulation time 91041065 ps
CPU time 1.1 seconds
Started Jul 24 05:17:44 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 198564 kb
Host smart-3fe9d1f9-b6b9-492c-b74e-42d64c9336e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217828553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2217828553
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3502258780
Short name T168
Test name
Test status
Simulation time 36734174 ps
CPU time 1 seconds
Started Jul 24 05:17:39 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 196508 kb
Host smart-5235feeb-d98e-4699-8a4f-5d4526559628
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502258780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3502258780
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1943498706
Short name T279
Test name
Test status
Simulation time 98973569 ps
CPU time 3.61 seconds
Started Jul 24 05:17:43 PM PDT 24
Finished Jul 24 05:17:47 PM PDT 24
Peak memory 198524 kb
Host smart-961692ed-c43f-4647-8df5-6e1294659c0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943498706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1943498706
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1528771193
Short name T155
Test name
Test status
Simulation time 419769887 ps
CPU time 2.03 seconds
Started Jul 24 05:17:35 PM PDT 24
Finished Jul 24 05:17:37 PM PDT 24
Peak memory 196680 kb
Host smart-976b795e-6f78-40e7-97ba-13bcd274ed42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528771193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1528771193
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1158831277
Short name T697
Test name
Test status
Simulation time 106862789 ps
CPU time 0.67 seconds
Started Jul 24 05:17:41 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 196540 kb
Host smart-1e84d9ba-6bfa-46f8-9ff7-f8caf380fc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158831277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1158831277
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.597268908
Short name T676
Test name
Test status
Simulation time 132340455 ps
CPU time 0.97 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 196480 kb
Host smart-eb92a502-e05c-4f1a-918b-753865466908
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597268908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.597268908
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3591942374
Short name T471
Test name
Test status
Simulation time 421107545 ps
CPU time 1.79 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 198472 kb
Host smart-eadf843c-a5e1-4002-8fc4-613a481cba90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591942374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3591942374
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.4144316061
Short name T712
Test name
Test status
Simulation time 45936764 ps
CPU time 0.97 seconds
Started Jul 24 05:17:22 PM PDT 24
Finished Jul 24 05:17:23 PM PDT 24
Peak memory 196988 kb
Host smart-30024d88-c1cf-419c-b78f-858dfa75793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144316061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.4144316061
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2615780210
Short name T372
Test name
Test status
Simulation time 57686767 ps
CPU time 1.03 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 196188 kb
Host smart-6895c0ff-02ab-43ca-abf6-a4b5bf353d82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615780210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2615780210
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.526662919
Short name T130
Test name
Test status
Simulation time 15201073186 ps
CPU time 212.78 seconds
Started Jul 24 05:17:46 PM PDT 24
Finished Jul 24 05:21:19 PM PDT 24
Peak memory 198528 kb
Host smart-4fa73e15-eb0c-43d2-870e-0322778cb02e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526662919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.526662919
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2578502555
Short name T572
Test name
Test status
Simulation time 39871107 ps
CPU time 0.58 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 194396 kb
Host smart-83d57c2c-526e-4e0e-8f52-f7491cba6789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578502555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2578502555
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2790165667
Short name T366
Test name
Test status
Simulation time 56963091 ps
CPU time 0.68 seconds
Started Jul 24 05:17:34 PM PDT 24
Finished Jul 24 05:17:35 PM PDT 24
Peak memory 195124 kb
Host smart-56c498d0-0e9f-47f4-b91a-b5efcc25a6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790165667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2790165667
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.19937121
Short name T639
Test name
Test status
Simulation time 2353187028 ps
CPU time 18.41 seconds
Started Jul 24 05:17:50 PM PDT 24
Finished Jul 24 05:18:09 PM PDT 24
Peak memory 196764 kb
Host smart-f3b301da-b19c-4ac2-88bb-36f7b0e00b64
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19937121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stress
.19937121
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.530238203
Short name T195
Test name
Test status
Simulation time 57034036 ps
CPU time 0.95 seconds
Started Jul 24 05:17:43 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 198100 kb
Host smart-a627b97d-3299-4600-98e0-5564d34fa105
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530238203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.530238203
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3654812490
Short name T631
Test name
Test status
Simulation time 181831361 ps
CPU time 1.4 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 198432 kb
Host smart-279b7a60-fbed-4a5d-8024-170cacff6f2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654812490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3654812490
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1684342864
Short name T59
Test name
Test status
Simulation time 93856814 ps
CPU time 3.52 seconds
Started Jul 24 05:17:35 PM PDT 24
Finished Jul 24 05:17:39 PM PDT 24
Peak memory 198664 kb
Host smart-c749f329-d731-46a7-936c-4dee69498507
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684342864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1684342864
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3365667488
Short name T128
Test name
Test status
Simulation time 98914761 ps
CPU time 2.11 seconds
Started Jul 24 05:17:32 PM PDT 24
Finished Jul 24 05:17:35 PM PDT 24
Peak memory 197080 kb
Host smart-6a44a61e-4403-420f-a65d-12da50b38702
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365667488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3365667488
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2977604573
Short name T413
Test name
Test status
Simulation time 147851684 ps
CPU time 1.08 seconds
Started Jul 24 05:17:27 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 197244 kb
Host smart-0524dcaf-8a7a-42d1-9317-2e333c7975ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977604573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2977604573
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3166714624
Short name T208
Test name
Test status
Simulation time 47007461 ps
CPU time 1.02 seconds
Started Jul 24 05:17:26 PM PDT 24
Finished Jul 24 05:17:28 PM PDT 24
Peak memory 197180 kb
Host smart-05190db7-0ad8-41bd-877a-08d5fd36b234
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166714624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3166714624
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3440029636
Short name T545
Test name
Test status
Simulation time 227336162 ps
CPU time 3.48 seconds
Started Jul 24 05:17:31 PM PDT 24
Finished Jul 24 05:17:35 PM PDT 24
Peak memory 196760 kb
Host smart-cee83197-8bc2-46ef-8739-9f426eccfcf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440029636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3440029636
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2033439751
Short name T329
Test name
Test status
Simulation time 50682636 ps
CPU time 0.88 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:41 PM PDT 24
Peak memory 195948 kb
Host smart-42e66de3-debe-4cec-9ad6-fb9678914435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033439751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2033439751
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3112203279
Short name T649
Test name
Test status
Simulation time 55645401 ps
CPU time 0.99 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:27 PM PDT 24
Peak memory 196920 kb
Host smart-56eab62f-148a-468c-b393-d92570a7b33a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112203279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3112203279
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3565114551
Short name T559
Test name
Test status
Simulation time 10033259314 ps
CPU time 98.35 seconds
Started Jul 24 05:17:39 PM PDT 24
Finished Jul 24 05:19:18 PM PDT 24
Peak memory 198600 kb
Host smart-8ff50fb7-3b40-43f0-a097-0b69119eddf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565114551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3565114551
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4102164061
Short name T203
Test name
Test status
Simulation time 31360162 ps
CPU time 0.59 seconds
Started Jul 24 05:17:36 PM PDT 24
Finished Jul 24 05:17:37 PM PDT 24
Peak memory 195080 kb
Host smart-3149da69-e551-4752-ac0d-85e4e150f547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102164061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4102164061
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1891612501
Short name T265
Test name
Test status
Simulation time 17725515 ps
CPU time 0.67 seconds
Started Jul 24 05:17:34 PM PDT 24
Finished Jul 24 05:17:35 PM PDT 24
Peak memory 195340 kb
Host smart-99dbddb5-7099-4bc5-bf3b-a47e7bdefa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891612501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1891612501
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2554674698
Short name T256
Test name
Test status
Simulation time 725575277 ps
CPU time 10.27 seconds
Started Jul 24 05:17:48 PM PDT 24
Finished Jul 24 05:17:58 PM PDT 24
Peak memory 198492 kb
Host smart-eacc3ecb-870d-413b-8428-724d33f662cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554674698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2554674698
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.56244645
Short name T113
Test name
Test status
Simulation time 60146508 ps
CPU time 0.91 seconds
Started Jul 24 05:17:33 PM PDT 24
Finished Jul 24 05:17:34 PM PDT 24
Peak memory 197520 kb
Host smart-3c6feeb6-4827-4b9d-b369-23232098e08f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56244645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.56244645
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1352397644
Short name T246
Test name
Test status
Simulation time 111328793 ps
CPU time 0.89 seconds
Started Jul 24 05:17:44 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 196540 kb
Host smart-db6f8ecc-7cca-48a4-b52b-8b1c4e9e0398
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352397644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1352397644
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2237776964
Short name T421
Test name
Test status
Simulation time 208125487 ps
CPU time 2.04 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:17:47 PM PDT 24
Peak memory 198640 kb
Host smart-623bf19e-9453-429e-8187-af458ba41a4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237776964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2237776964
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.681566569
Short name T507
Test name
Test status
Simulation time 82406407 ps
CPU time 2.32 seconds
Started Jul 24 05:17:43 PM PDT 24
Finished Jul 24 05:17:46 PM PDT 24
Peak memory 197288 kb
Host smart-e8ca3b68-d642-4808-869d-5bc20d9e75e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681566569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
681566569
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1468048363
Short name T609
Test name
Test status
Simulation time 64429282 ps
CPU time 0.73 seconds
Started Jul 24 05:17:25 PM PDT 24
Finished Jul 24 05:17:26 PM PDT 24
Peak memory 195912 kb
Host smart-f3571d9d-f52e-485f-8293-8aab5da0bf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468048363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1468048363
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1623146109
Short name T108
Test name
Test status
Simulation time 337470576 ps
CPU time 1.06 seconds
Started Jul 24 05:17:39 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 196276 kb
Host smart-927e48b2-1273-4e37-9105-7cab7572e001
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623146109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1623146109
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1928345500
Short name T319
Test name
Test status
Simulation time 185670139 ps
CPU time 3.19 seconds
Started Jul 24 05:17:44 PM PDT 24
Finished Jul 24 05:17:48 PM PDT 24
Peak memory 198556 kb
Host smart-0082f001-b8fc-43df-ae63-017bd9d7fa5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928345500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1928345500
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2779877814
Short name T443
Test name
Test status
Simulation time 235758395 ps
CPU time 1.22 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:39 PM PDT 24
Peak memory 196684 kb
Host smart-e74b62af-cded-4f85-bc3e-789f4b332cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779877814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2779877814
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2146428928
Short name T613
Test name
Test status
Simulation time 29683160 ps
CPU time 0.85 seconds
Started Jul 24 05:17:29 PM PDT 24
Finished Jul 24 05:17:30 PM PDT 24
Peak memory 195796 kb
Host smart-c853b036-3759-4b2c-9cfd-7fb8b63754b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146428928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2146428928
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1441741807
Short name T328
Test name
Test status
Simulation time 5750087573 ps
CPU time 49.06 seconds
Started Jul 24 05:17:36 PM PDT 24
Finished Jul 24 05:18:25 PM PDT 24
Peak memory 198608 kb
Host smart-12e71a95-3cd8-4cd4-b46b-d99250192f61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441741807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1441741807
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1937461184
Short name T302
Test name
Test status
Simulation time 115597903 ps
CPU time 0.57 seconds
Started Jul 24 05:17:28 PM PDT 24
Finished Jul 24 05:17:29 PM PDT 24
Peak memory 194372 kb
Host smart-f7d282f2-f71a-446a-9bd6-5730db7977b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937461184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1937461184
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.83086253
Short name T569
Test name
Test status
Simulation time 113854071 ps
CPU time 0.86 seconds
Started Jul 24 05:17:44 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 196996 kb
Host smart-00d15977-54a5-43c8-b69d-9ea67c9bb563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83086253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.83086253
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2415143200
Short name T275
Test name
Test status
Simulation time 1681719590 ps
CPU time 10.29 seconds
Started Jul 24 05:17:52 PM PDT 24
Finished Jul 24 05:18:02 PM PDT 24
Peak memory 195972 kb
Host smart-37695b5b-6f2f-4d46-931a-3f8b93c06b38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415143200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2415143200
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2582006644
Short name T280
Test name
Test status
Simulation time 385216732 ps
CPU time 1.13 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 197108 kb
Host smart-ac6431f8-2d70-4cc7-9425-66bd31f0e3d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582006644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2582006644
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3472031960
Short name T462
Test name
Test status
Simulation time 417434768 ps
CPU time 0.77 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:43 PM PDT 24
Peak memory 196604 kb
Host smart-687d119a-89a7-48e8-8a39-a1c200a08b93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472031960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3472031960
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2059274141
Short name T189
Test name
Test status
Simulation time 123031402 ps
CPU time 2.53 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 198476 kb
Host smart-8a147dba-7f83-4f8d-ad4a-7de828c9458c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059274141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2059274141
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2224580439
Short name T419
Test name
Test status
Simulation time 311651936 ps
CPU time 3.62 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 198528 kb
Host smart-ff6f5382-7ead-4c2e-ae45-ae02a1060c56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224580439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2224580439
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.405044042
Short name T589
Test name
Test status
Simulation time 348158166 ps
CPU time 1.19 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 197584 kb
Host smart-b60006b3-b37c-4c89-939e-82c205b975a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405044042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.405044042
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2911178651
Short name T115
Test name
Test status
Simulation time 228062096 ps
CPU time 1.25 seconds
Started Jul 24 05:17:37 PM PDT 24
Finished Jul 24 05:17:38 PM PDT 24
Peak memory 198552 kb
Host smart-988fc0f3-bb93-4b4e-a670-62c4bd6afe60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911178651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2911178651
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3315470737
Short name T681
Test name
Test status
Simulation time 463083821 ps
CPU time 5.17 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 198408 kb
Host smart-d8dee627-ee56-44cc-990e-11ee8247b99e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315470737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3315470737
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.762535713
Short name T222
Test name
Test status
Simulation time 50689866 ps
CPU time 1.08 seconds
Started Jul 24 05:17:20 PM PDT 24
Finished Jul 24 05:17:21 PM PDT 24
Peak memory 196016 kb
Host smart-3b2f004b-8ca6-4698-9d28-25e81f0f681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762535713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.762535713
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3640566739
Short name T453
Test name
Test status
Simulation time 62161772 ps
CPU time 1.04 seconds
Started Jul 24 05:17:37 PM PDT 24
Finished Jul 24 05:17:38 PM PDT 24
Peak memory 196308 kb
Host smart-28a73a17-245e-49af-8428-baeb1b2f648f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640566739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3640566739
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.804691224
Short name T718
Test name
Test status
Simulation time 12815004891 ps
CPU time 184.43 seconds
Started Jul 24 05:17:51 PM PDT 24
Finished Jul 24 05:20:56 PM PDT 24
Peak memory 198616 kb
Host smart-19811b87-666d-4f80-a122-24d07f6507d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804691224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.804691224
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2535739673
Short name T46
Test name
Test status
Simulation time 310539015081 ps
CPU time 1470.11 seconds
Started Jul 24 05:17:36 PM PDT 24
Finished Jul 24 05:42:06 PM PDT 24
Peak memory 198736 kb
Host smart-e1a8c1e7-e70b-4e5c-b182-8d326ae320ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2535739673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2535739673
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1841674267
Short name T205
Test name
Test status
Simulation time 36705807 ps
CPU time 0.55 seconds
Started Jul 24 05:17:43 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 194508 kb
Host smart-e13c61ec-f34a-47db-ad9c-c6dbcfd7f7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841674267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1841674267
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4000488626
Short name T493
Test name
Test status
Simulation time 93406074 ps
CPU time 0.81 seconds
Started Jul 24 05:17:57 PM PDT 24
Finished Jul 24 05:17:58 PM PDT 24
Peak memory 195860 kb
Host smart-4d378f8e-f172-4eac-87a1-e86e7f62546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000488626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4000488626
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.343073008
Short name T156
Test name
Test status
Simulation time 4807531480 ps
CPU time 27.94 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:18:09 PM PDT 24
Peak memory 198508 kb
Host smart-2d11e972-c6ea-4936-a5e0-7e3e14d83976
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343073008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.343073008
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2140568212
Short name T627
Test name
Test status
Simulation time 62839989 ps
CPU time 0.95 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:43 PM PDT 24
Peak memory 197044 kb
Host smart-b5ad304c-4746-452a-9c57-4b61d70cd2a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140568212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2140568212
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3289409076
Short name T671
Test name
Test status
Simulation time 28653083 ps
CPU time 0.71 seconds
Started Jul 24 05:17:53 PM PDT 24
Finished Jul 24 05:17:54 PM PDT 24
Peak memory 195588 kb
Host smart-e0d2779d-0011-4715-9603-b770eec7590a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289409076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3289409076
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1281439184
Short name T136
Test name
Test status
Simulation time 65883997 ps
CPU time 2.52 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:17:48 PM PDT 24
Peak memory 198684 kb
Host smart-f75846f6-aa16-4974-9556-b9b94961bb4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281439184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1281439184
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.4181304742
Short name T556
Test name
Test status
Simulation time 233627082 ps
CPU time 1.9 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 197760 kb
Host smart-19b7e2e0-0dff-421a-a426-bf3a294971df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181304742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.4181304742
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2297716665
Short name T310
Test name
Test status
Simulation time 25025798 ps
CPU time 0.72 seconds
Started Jul 24 05:17:48 PM PDT 24
Finished Jul 24 05:17:48 PM PDT 24
Peak memory 196508 kb
Host smart-e5a66256-1ccb-455d-9b07-980d880f43d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297716665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2297716665
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.957025688
Short name T363
Test name
Test status
Simulation time 83649193 ps
CPU time 1.04 seconds
Started Jul 24 05:17:44 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 196500 kb
Host smart-56822214-76cb-4232-a584-8bc6ed0818b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957025688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.957025688
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.815112300
Short name T367
Test name
Test status
Simulation time 211060385 ps
CPU time 2.27 seconds
Started Jul 24 05:17:41 PM PDT 24
Finished Jul 24 05:17:43 PM PDT 24
Peak memory 198092 kb
Host smart-24872c99-2eb9-4be6-ae47-cf2500661a8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815112300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.815112300
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.241725610
Short name T263
Test name
Test status
Simulation time 105915374 ps
CPU time 1.09 seconds
Started Jul 24 05:17:44 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 196220 kb
Host smart-f74fd0c5-2750-471b-9d47-38a12e0d27de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241725610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.241725610
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1103378811
Short name T464
Test name
Test status
Simulation time 66451025 ps
CPU time 1.26 seconds
Started Jul 24 05:17:58 PM PDT 24
Finished Jul 24 05:18:00 PM PDT 24
Peak memory 197376 kb
Host smart-e1b22ce7-d9f3-4c69-b6fe-48164f0ea716
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103378811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1103378811
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2136068583
Short name T188
Test name
Test status
Simulation time 11924082415 ps
CPU time 74.49 seconds
Started Jul 24 05:17:39 PM PDT 24
Finished Jul 24 05:18:54 PM PDT 24
Peak memory 198580 kb
Host smart-7641c5d3-af73-44ca-b936-1cff70ba1848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136068583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2136068583
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.253565065
Short name T182
Test name
Test status
Simulation time 11491000 ps
CPU time 0.6 seconds
Started Jul 24 05:18:10 PM PDT 24
Finished Jul 24 05:18:11 PM PDT 24
Peak memory 194380 kb
Host smart-26858360-4ae1-4105-ad2d-891110de920b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253565065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.253565065
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1521039319
Short name T116
Test name
Test status
Simulation time 24265232 ps
CPU time 0.71 seconds
Started Jul 24 05:17:37 PM PDT 24
Finished Jul 24 05:17:38 PM PDT 24
Peak memory 194596 kb
Host smart-ad3d9a84-e72e-4f7c-a20c-c17ab5f7befc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521039319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1521039319
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2611027834
Short name T579
Test name
Test status
Simulation time 444292851 ps
CPU time 14.04 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:57 PM PDT 24
Peak memory 198540 kb
Host smart-ac52f0c7-4a20-47b2-ac7d-8ce33a46939b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611027834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2611027834
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.5668970
Short name T238
Test name
Test status
Simulation time 105798072 ps
CPU time 0.85 seconds
Started Jul 24 05:17:34 PM PDT 24
Finished Jul 24 05:17:35 PM PDT 24
Peak memory 197036 kb
Host smart-3eb4ff0a-bdb9-40c9-a581-5b0beeee481e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5668970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.5668970
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2551693174
Short name T652
Test name
Test status
Simulation time 69704113 ps
CPU time 0.76 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:48 PM PDT 24
Peak memory 195812 kb
Host smart-a8ade7b7-f8b9-4ece-a957-84685969d9a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551693174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2551693174
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1920393638
Short name T650
Test name
Test status
Simulation time 251246492 ps
CPU time 2.6 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:41 PM PDT 24
Peak memory 198604 kb
Host smart-07214cd9-7bc0-4cd5-a399-2f3ee40b1d89
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920393638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1920393638
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2405892839
Short name T710
Test name
Test status
Simulation time 686371365 ps
CPU time 3.25 seconds
Started Jul 24 05:17:41 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 197548 kb
Host smart-495f7ce9-181c-4069-8346-8b899aa502f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405892839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2405892839
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3189210933
Short name T88
Test name
Test status
Simulation time 48412390 ps
CPU time 0.97 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 196332 kb
Host smart-449ec547-2fa4-4fbf-85df-3ac2fda026e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189210933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3189210933
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3785837820
Short name T204
Test name
Test status
Simulation time 101841873 ps
CPU time 0.82 seconds
Started Jul 24 05:17:41 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 197120 kb
Host smart-0c7fec90-7720-41d6-9712-89fb6596a3c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785837820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3785837820
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.99652101
Short name T525
Test name
Test status
Simulation time 117363374 ps
CPU time 1.64 seconds
Started Jul 24 05:17:46 PM PDT 24
Finished Jul 24 05:17:48 PM PDT 24
Peak memory 198472 kb
Host smart-4a72ee1e-6ee3-4acc-af47-316fd95a2ddf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99652101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand
om_long_reg_writes_reg_reads.99652101
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1457059393
Short name T335
Test name
Test status
Simulation time 30082108 ps
CPU time 0.77 seconds
Started Jul 24 05:17:44 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 195648 kb
Host smart-07b91025-bd3d-43ae-bbb2-e6d1a22bf3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457059393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1457059393
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.770592308
Short name T704
Test name
Test status
Simulation time 58194798 ps
CPU time 1 seconds
Started Jul 24 05:17:46 PM PDT 24
Finished Jul 24 05:17:47 PM PDT 24
Peak memory 196676 kb
Host smart-005e5eb3-07a3-448b-979d-99039f7022b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770592308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.770592308
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3571874540
Short name T433
Test name
Test status
Simulation time 10026418262 ps
CPU time 93.96 seconds
Started Jul 24 05:17:50 PM PDT 24
Finished Jul 24 05:19:24 PM PDT 24
Peak memory 198604 kb
Host smart-b5f1e91b-4761-4898-b524-1900edcbeb54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571874540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3571874540
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.4077948472
Short name T266
Test name
Test status
Simulation time 53266180328 ps
CPU time 1451.47 seconds
Started Jul 24 05:17:55 PM PDT 24
Finished Jul 24 05:42:07 PM PDT 24
Peak memory 198732 kb
Host smart-b1360ae4-7ed4-4e47-b91e-1786b74be472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4077948472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.4077948472
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3425010049
Short name T326
Test name
Test status
Simulation time 23764907 ps
CPU time 0.64 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:16:36 PM PDT 24
Peak memory 194404 kb
Host smart-0f8e6cbe-64dd-496a-9100-eac3ef503b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425010049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3425010049
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3672545894
Short name T487
Test name
Test status
Simulation time 80967944 ps
CPU time 0.68 seconds
Started Jul 24 05:16:45 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 194508 kb
Host smart-23434761-18fd-433b-b520-6bf2fe13eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672545894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3672545894
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4102099012
Short name T581
Test name
Test status
Simulation time 2754728660 ps
CPU time 19.83 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:17:07 PM PDT 24
Peak memory 197052 kb
Host smart-de4d2e0d-0adb-4992-b450-fe896bf6244f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102099012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4102099012
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2292285370
Short name T412
Test name
Test status
Simulation time 333747139 ps
CPU time 1.04 seconds
Started Jul 24 05:16:39 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 196860 kb
Host smart-3758b3f4-63df-4888-b184-fdd5d93c9d5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292285370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2292285370
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.999684404
Short name T585
Test name
Test status
Simulation time 69089753 ps
CPU time 1.1 seconds
Started Jul 24 05:16:32 PM PDT 24
Finished Jul 24 05:16:34 PM PDT 24
Peak memory 196344 kb
Host smart-b202735f-7738-4768-b1f5-b6d93c563b6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999684404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.999684404
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3501900222
Short name T259
Test name
Test status
Simulation time 281295675 ps
CPU time 2.59 seconds
Started Jul 24 05:16:33 PM PDT 24
Finished Jul 24 05:16:36 PM PDT 24
Peak memory 197032 kb
Host smart-28de1ffa-36bf-4e5d-ba52-8caabb22d44f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501900222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3501900222
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.423272469
Short name T691
Test name
Test status
Simulation time 111320189 ps
CPU time 0.81 seconds
Started Jul 24 05:16:37 PM PDT 24
Finished Jul 24 05:16:38 PM PDT 24
Peak memory 194836 kb
Host smart-1b9e22b2-dbb5-4581-a273-31c80fa94e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423272469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.423272469
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2747588122
Short name T658
Test name
Test status
Simulation time 27702918 ps
CPU time 0.86 seconds
Started Jul 24 05:16:32 PM PDT 24
Finished Jul 24 05:16:33 PM PDT 24
Peak memory 197048 kb
Host smart-c8d2e69f-20d1-43ce-b7a3-c7307e873bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747588122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2747588122
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.626197366
Short name T514
Test name
Test status
Simulation time 37393315 ps
CPU time 0.97 seconds
Started Jul 24 05:16:36 PM PDT 24
Finished Jul 24 05:16:37 PM PDT 24
Peak memory 196536 kb
Host smart-182d45cd-3db3-498b-ad61-43a3b5b920ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626197366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.626197366
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.795696269
Short name T148
Test name
Test status
Simulation time 150394600 ps
CPU time 1.75 seconds
Started Jul 24 05:16:37 PM PDT 24
Finished Jul 24 05:16:39 PM PDT 24
Peak memory 198456 kb
Host smart-9771eda6-85e8-408a-973e-e7db5ce4eae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795696269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.795696269
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1615978545
Short name T32
Test name
Test status
Simulation time 90625827 ps
CPU time 0.95 seconds
Started Jul 24 05:16:45 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 215444 kb
Host smart-4388b6a1-e9fc-48c9-95d9-e63e0e6e510f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615978545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1615978545
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2785683410
Short name T126
Test name
Test status
Simulation time 157969171 ps
CPU time 0.85 seconds
Started Jul 24 05:16:34 PM PDT 24
Finished Jul 24 05:16:35 PM PDT 24
Peak memory 196716 kb
Host smart-f0d51226-40dd-48ea-a6f3-34f3458374f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785683410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2785683410
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3569093158
Short name T217
Test name
Test status
Simulation time 110783283 ps
CPU time 0.96 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 196940 kb
Host smart-66417591-b2f9-4e12-a0f7-d2090c1a5728
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569093158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3569093158
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3219972752
Short name T478
Test name
Test status
Simulation time 17602431282 ps
CPU time 71.59 seconds
Started Jul 24 05:16:41 PM PDT 24
Finished Jul 24 05:17:53 PM PDT 24
Peak memory 198684 kb
Host smart-46e5111a-4bde-4231-9d91-069fa5024b6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219972752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3219972752
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3465319500
Short name T320
Test name
Test status
Simulation time 40705913 ps
CPU time 0.55 seconds
Started Jul 24 05:17:47 PM PDT 24
Finished Jul 24 05:17:48 PM PDT 24
Peak memory 195304 kb
Host smart-28e4344b-ca93-476a-b296-9f713d456b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465319500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3465319500
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3674308327
Short name T245
Test name
Test status
Simulation time 106794976 ps
CPU time 0.85 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:17:46 PM PDT 24
Peak memory 197036 kb
Host smart-9bb9fffb-9da1-42ff-827b-af4bb10b963b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674308327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3674308327
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1097649698
Short name T355
Test name
Test status
Simulation time 424033507 ps
CPU time 20.85 seconds
Started Jul 24 05:17:39 PM PDT 24
Finished Jul 24 05:18:00 PM PDT 24
Peak memory 197436 kb
Host smart-6cfff7b8-b384-4a71-bc1b-2d4ee32529d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097649698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1097649698
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1350820696
Short name T530
Test name
Test status
Simulation time 42358011 ps
CPU time 0.74 seconds
Started Jul 24 05:17:48 PM PDT 24
Finished Jul 24 05:17:48 PM PDT 24
Peak memory 196192 kb
Host smart-e79e840c-2c09-40ea-8081-5e9a8abfeb94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350820696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1350820696
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3170397345
Short name T492
Test name
Test status
Simulation time 85993086 ps
CPU time 1.13 seconds
Started Jul 24 05:17:39 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 196604 kb
Host smart-407d1324-cb97-46b3-9877-67b5cc0b1682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170397345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3170397345
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3377154690
Short name T679
Test name
Test status
Simulation time 586633476 ps
CPU time 3.13 seconds
Started Jul 24 05:17:41 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 197052 kb
Host smart-5af6559c-59af-4ffc-b8c2-2f3933de2580
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377154690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3377154690
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3046173778
Short name T240
Test name
Test status
Simulation time 295778249 ps
CPU time 2.23 seconds
Started Jul 24 05:17:53 PM PDT 24
Finished Jul 24 05:17:55 PM PDT 24
Peak memory 197652 kb
Host smart-fde18a69-09fc-44d9-bb24-11655c6e25c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046173778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3046173778
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3894038314
Short name T472
Test name
Test status
Simulation time 35511847 ps
CPU time 1.23 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 196260 kb
Host smart-e2ab692b-1959-470c-9682-c269e658a376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894038314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3894038314
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3217230058
Short name T526
Test name
Test status
Simulation time 32592518 ps
CPU time 1.17 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 197344 kb
Host smart-f7ea6230-b58b-461d-a331-780f70746929
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217230058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3217230058
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1242579807
Short name T468
Test name
Test status
Simulation time 804757152 ps
CPU time 3.59 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:43 PM PDT 24
Peak memory 198464 kb
Host smart-3575d0a7-3ce3-44fe-be52-18e9f59969f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242579807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1242579807
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2504866300
Short name T137
Test name
Test status
Simulation time 25157360 ps
CPU time 0.73 seconds
Started Jul 24 05:17:54 PM PDT 24
Finished Jul 24 05:17:54 PM PDT 24
Peak memory 195388 kb
Host smart-51e07138-c328-48df-8311-5e2fba86a180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504866300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2504866300
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.4049170540
Short name T486
Test name
Test status
Simulation time 49132229 ps
CPU time 0.97 seconds
Started Jul 24 05:17:54 PM PDT 24
Finished Jul 24 05:17:55 PM PDT 24
Peak memory 196052 kb
Host smart-f86ccc72-7d47-47c9-bb9a-6c7536f7de7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049170540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.4049170540
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.906234995
Short name T439
Test name
Test status
Simulation time 9431384354 ps
CPU time 145.46 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:20:06 PM PDT 24
Peak memory 198632 kb
Host smart-12977363-bf27-49f3-98fc-1ab903ab5de7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906234995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.906234995
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2444423774
Short name T314
Test name
Test status
Simulation time 20484172 ps
CPU time 0.57 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 195312 kb
Host smart-726e7f2b-06c4-41d5-bc6a-369786098da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444423774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2444423774
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2363903495
Short name T466
Test name
Test status
Simulation time 44117523 ps
CPU time 0.84 seconds
Started Jul 24 05:18:00 PM PDT 24
Finished Jul 24 05:18:01 PM PDT 24
Peak memory 196824 kb
Host smart-c533ed3e-368b-46b5-8af7-d98a61553034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363903495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2363903495
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2383543676
Short name T339
Test name
Test status
Simulation time 6997049178 ps
CPU time 12.3 seconds
Started Jul 24 05:17:51 PM PDT 24
Finished Jul 24 05:18:03 PM PDT 24
Peak memory 197428 kb
Host smart-084f3900-0779-4ba0-ab54-734ae606c74f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383543676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2383543676
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1356453744
Short name T657
Test name
Test status
Simulation time 242719710 ps
CPU time 0.91 seconds
Started Jul 24 05:17:39 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 196868 kb
Host smart-08953a67-01c1-4224-bc05-ad89cd381bec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356453744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1356453744
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1272322358
Short name T719
Test name
Test status
Simulation time 94140588 ps
CPU time 0.74 seconds
Started Jul 24 05:17:34 PM PDT 24
Finished Jul 24 05:17:35 PM PDT 24
Peak memory 195968 kb
Host smart-5b972a97-9eaa-4111-8314-8e44a00b172d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272322358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1272322358
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2396692231
Short name T171
Test name
Test status
Simulation time 84865873 ps
CPU time 1.98 seconds
Started Jul 24 05:17:35 PM PDT 24
Finished Jul 24 05:17:37 PM PDT 24
Peak memory 198540 kb
Host smart-a5c5abfc-1e73-4d08-bde6-d1ab97e9f6b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396692231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2396692231
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.799680143
Short name T414
Test name
Test status
Simulation time 210024017 ps
CPU time 1.28 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:39 PM PDT 24
Peak memory 196612 kb
Host smart-c5ff1a79-9ccd-4f17-96cf-757b4031ee78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799680143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
799680143
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.889700710
Short name T170
Test name
Test status
Simulation time 144054583 ps
CPU time 1.24 seconds
Started Jul 24 05:17:55 PM PDT 24
Finished Jul 24 05:17:56 PM PDT 24
Peak memory 198588 kb
Host smart-6a6af390-f979-43a2-8055-6f6c5598f54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889700710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.889700710
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.135379940
Short name T87
Test name
Test status
Simulation time 240672132 ps
CPU time 0.84 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:43 PM PDT 24
Peak memory 196476 kb
Host smart-2d46e38c-3f34-4b12-956b-c0fbedb2c1e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135379940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.135379940
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1284910361
Short name T597
Test name
Test status
Simulation time 252871834 ps
CPU time 3.34 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 198368 kb
Host smart-52d3606b-fd3f-46b7-9365-c65b27522323
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284910361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1284910361
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.927147537
Short name T508
Test name
Test status
Simulation time 38961032 ps
CPU time 1.01 seconds
Started Jul 24 05:17:48 PM PDT 24
Finished Jul 24 05:17:49 PM PDT 24
Peak memory 196756 kb
Host smart-fdd37452-750f-4b2a-9657-f372a1b4b9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927147537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.927147537
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.874305779
Short name T402
Test name
Test status
Simulation time 99012199 ps
CPU time 0.83 seconds
Started Jul 24 05:17:38 PM PDT 24
Finished Jul 24 05:17:39 PM PDT 24
Peak memory 197004 kb
Host smart-6a389eb0-9a1e-4e57-a6cc-f9244287e5a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874305779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.874305779
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3064595517
Short name T342
Test name
Test status
Simulation time 14229948144 ps
CPU time 188.78 seconds
Started Jul 24 05:17:46 PM PDT 24
Finished Jul 24 05:20:55 PM PDT 24
Peak memory 198660 kb
Host smart-f57a3e9c-d1b7-46ae-a17b-86139573266f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064595517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3064595517
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1056642099
Short name T52
Test name
Test status
Simulation time 565287161797 ps
CPU time 518.69 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:26:24 PM PDT 24
Peak memory 198956 kb
Host smart-2c915abf-8427-4a65-b83a-b7c244ee9c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1056642099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1056642099
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3003091908
Short name T501
Test name
Test status
Simulation time 48482404 ps
CPU time 0.55 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:40 PM PDT 24
Peak memory 194428 kb
Host smart-57454199-7cf6-454c-bcf5-b239ceab0803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003091908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3003091908
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2945426394
Short name T278
Test name
Test status
Simulation time 103681247 ps
CPU time 0.85 seconds
Started Jul 24 05:17:46 PM PDT 24
Finished Jul 24 05:17:47 PM PDT 24
Peak memory 197032 kb
Host smart-db34b18d-8aca-4a93-a9c6-962c545dc28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945426394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2945426394
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3791041304
Short name T169
Test name
Test status
Simulation time 195784289 ps
CPU time 5.71 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:49 PM PDT 24
Peak memory 197468 kb
Host smart-d5cc3296-7466-4023-b304-9f939af64180
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791041304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3791041304
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1283108957
Short name T695
Test name
Test status
Simulation time 122980493 ps
CPU time 0.78 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:43 PM PDT 24
Peak memory 196468 kb
Host smart-9bb27b23-3958-4f1f-b9de-9bc7993b8697
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283108957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1283108957
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.114084691
Short name T154
Test name
Test status
Simulation time 349240118 ps
CPU time 1.24 seconds
Started Jul 24 05:17:43 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 196288 kb
Host smart-67521728-4dd9-4caf-94f0-eb0e38205da1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114084691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.114084691
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3939592164
Short name T192
Test name
Test status
Simulation time 40949288 ps
CPU time 1.48 seconds
Started Jul 24 05:17:40 PM PDT 24
Finished Jul 24 05:17:41 PM PDT 24
Peak memory 197448 kb
Host smart-a457c03e-5d44-41fc-b142-848155e712fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939592164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3939592164
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1084656074
Short name T187
Test name
Test status
Simulation time 35213628 ps
CPU time 1.04 seconds
Started Jul 24 05:18:01 PM PDT 24
Finished Jul 24 05:18:02 PM PDT 24
Peak memory 196836 kb
Host smart-4ea7d2cc-da65-42ad-8d0e-e24965312b6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084656074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1084656074
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1820799037
Short name T174
Test name
Test status
Simulation time 30234083 ps
CPU time 1.12 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:17:47 PM PDT 24
Peak memory 197380 kb
Host smart-eda48b52-e09b-4cda-8891-4652be2af445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820799037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1820799037
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.247460675
Short name T573
Test name
Test status
Simulation time 42302742 ps
CPU time 0.66 seconds
Started Jul 24 05:17:41 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 195384 kb
Host smart-bb77c225-ba98-42c3-929e-d348b5220d2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247460675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.247460675
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2840128179
Short name T241
Test name
Test status
Simulation time 2564534704 ps
CPU time 3.81 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:47 PM PDT 24
Peak memory 198568 kb
Host smart-8fc73ea1-a1de-470d-bb35-3a3394f33467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840128179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2840128179
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2714093468
Short name T383
Test name
Test status
Simulation time 552839882 ps
CPU time 1.36 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:17:47 PM PDT 24
Peak memory 197372 kb
Host smart-a7024541-8122-43d7-a20c-280d3372b388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714093468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2714093468
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1553495116
Short name T228
Test name
Test status
Simulation time 87248651 ps
CPU time 0.76 seconds
Started Jul 24 05:17:41 PM PDT 24
Finished Jul 24 05:17:42 PM PDT 24
Peak memory 195700 kb
Host smart-7f334c1b-0107-4eb0-bd46-34772ae9c58a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553495116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1553495116
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3426312309
Short name T675
Test name
Test status
Simulation time 116256443282 ps
CPU time 198.11 seconds
Started Jul 24 05:17:50 PM PDT 24
Finished Jul 24 05:21:08 PM PDT 24
Peak memory 198644 kb
Host smart-58a28f08-deb9-450e-bbcc-967b5c5ac43a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426312309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3426312309
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1497611602
Short name T53
Test name
Test status
Simulation time 70727974976 ps
CPU time 1524.03 seconds
Started Jul 24 05:17:43 PM PDT 24
Finished Jul 24 05:43:08 PM PDT 24
Peak memory 198784 kb
Host smart-29a27d62-e5fa-42ba-a194-f5248335b63b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1497611602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1497611602
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.521451551
Short name T544
Test name
Test status
Simulation time 81691741 ps
CPU time 0.6 seconds
Started Jul 24 05:17:50 PM PDT 24
Finished Jul 24 05:17:51 PM PDT 24
Peak memory 194396 kb
Host smart-75fedb06-1998-4b2b-bd17-0e3589d959c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521451551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.521451551
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2326147408
Short name T369
Test name
Test status
Simulation time 33172929 ps
CPU time 0.79 seconds
Started Jul 24 05:18:13 PM PDT 24
Finished Jul 24 05:18:14 PM PDT 24
Peak memory 195908 kb
Host smart-62ec9215-b1ad-41ef-b976-c07ec279a847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326147408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2326147408
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.362348194
Short name T674
Test name
Test status
Simulation time 279038211 ps
CPU time 6.72 seconds
Started Jul 24 05:17:46 PM PDT 24
Finished Jul 24 05:17:53 PM PDT 24
Peak memory 198528 kb
Host smart-d4db0386-b45e-4a6b-b723-1dbf1b25b2e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362348194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.362348194
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2583364664
Short name T322
Test name
Test status
Simulation time 27826677 ps
CPU time 0.63 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:18:05 PM PDT 24
Peak memory 194908 kb
Host smart-b9c64fe5-921e-4eb4-8a1b-43b7eb8bf071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583364664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2583364664
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2790196863
Short name T563
Test name
Test status
Simulation time 67776930 ps
CPU time 0.66 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:18:06 PM PDT 24
Peak memory 194684 kb
Host smart-2ce2ce7d-522c-46b0-866f-d6137808a663
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790196863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2790196863
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1898340488
Short name T252
Test name
Test status
Simulation time 258391934 ps
CPU time 2.63 seconds
Started Jul 24 05:17:57 PM PDT 24
Finished Jul 24 05:18:00 PM PDT 24
Peak memory 198620 kb
Host smart-5e4d6e1a-f6d8-41a7-b375-bbf809e6c1cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898340488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1898340488
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2171035305
Short name T379
Test name
Test status
Simulation time 120321595 ps
CPU time 1.91 seconds
Started Jul 24 05:17:50 PM PDT 24
Finished Jul 24 05:18:02 PM PDT 24
Peak memory 197444 kb
Host smart-f23a3bbc-b6f1-4dc2-bd46-b011819a8f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171035305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2171035305
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3037629169
Short name T655
Test name
Test status
Simulation time 57184386 ps
CPU time 1.2 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:17:47 PM PDT 24
Peak memory 197440 kb
Host smart-4c08fb56-897b-4b69-8a30-675b44c058fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037629169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3037629169
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2010609169
Short name T151
Test name
Test status
Simulation time 74882989 ps
CPU time 0.67 seconds
Started Jul 24 05:17:42 PM PDT 24
Finished Jul 24 05:17:43 PM PDT 24
Peak memory 195884 kb
Host smart-9b28fe6a-cd59-47ea-b1ff-88245802c88c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010609169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2010609169
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3475085579
Short name T436
Test name
Test status
Simulation time 446929623 ps
CPU time 2.06 seconds
Started Jul 24 05:18:11 PM PDT 24
Finished Jul 24 05:18:13 PM PDT 24
Peak memory 198428 kb
Host smart-a40f74bb-524a-4a01-83c8-65c0c059c528
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475085579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3475085579
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2094072201
Short name T260
Test name
Test status
Simulation time 118029017 ps
CPU time 0.91 seconds
Started Jul 24 05:17:51 PM PDT 24
Finished Jul 24 05:17:52 PM PDT 24
Peak memory 196984 kb
Host smart-ab3d8f52-7cd7-4ce2-82d9-4f608e308a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094072201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2094072201
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.230492966
Short name T179
Test name
Test status
Simulation time 121156642 ps
CPU time 0.87 seconds
Started Jul 24 05:17:59 PM PDT 24
Finished Jul 24 05:18:00 PM PDT 24
Peak memory 195912 kb
Host smart-f42ac083-8f14-4796-b3f1-6441fb8a2c78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230492966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.230492966
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3020512439
Short name T560
Test name
Test status
Simulation time 14522704633 ps
CPU time 80.54 seconds
Started Jul 24 05:17:55 PM PDT 24
Finished Jul 24 05:19:15 PM PDT 24
Peak memory 198600 kb
Host smart-b759afff-7fb6-4d9f-b3f6-f97c7cadc212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020512439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3020512439
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3737532459
Short name T432
Test name
Test status
Simulation time 101310112298 ps
CPU time 645.35 seconds
Started Jul 24 05:18:06 PM PDT 24
Finished Jul 24 05:28:51 PM PDT 24
Peak memory 198792 kb
Host smart-61ff24c2-00d3-4841-af20-91a4b5873fd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3737532459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3737532459
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.4258387614
Short name T36
Test name
Test status
Simulation time 40410589 ps
CPU time 0.58 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:18:08 PM PDT 24
Peak memory 194420 kb
Host smart-03f9854f-2658-4c1f-89cd-eb3c761ac0d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258387614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.4258387614
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1816963492
Short name T479
Test name
Test status
Simulation time 129778890 ps
CPU time 0.93 seconds
Started Jul 24 05:17:56 PM PDT 24
Finished Jul 24 05:17:57 PM PDT 24
Peak memory 197172 kb
Host smart-492573f0-ffc0-4d90-bde0-361149e1274b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816963492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1816963492
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3789993561
Short name T286
Test name
Test status
Simulation time 1452766229 ps
CPU time 25.99 seconds
Started Jul 24 05:18:11 PM PDT 24
Finished Jul 24 05:18:38 PM PDT 24
Peak memory 197088 kb
Host smart-a73d144b-e083-416c-866c-0326cd2ca1f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789993561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3789993561
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.981278499
Short name T707
Test name
Test status
Simulation time 121092767 ps
CPU time 0.71 seconds
Started Jul 24 05:18:04 PM PDT 24
Finished Jul 24 05:18:05 PM PDT 24
Peak memory 195724 kb
Host smart-84d9bc3b-c51b-493c-91ac-727fe11977f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981278499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.981278499
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2955696524
Short name T368
Test name
Test status
Simulation time 39294796 ps
CPU time 0.7 seconds
Started Jul 24 05:17:58 PM PDT 24
Finished Jul 24 05:17:59 PM PDT 24
Peak memory 195892 kb
Host smart-aeb23f6e-e500-4f79-97cb-677c90abc019
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955696524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2955696524
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.454471
Short name T553
Test name
Test status
Simulation time 22401126 ps
CPU time 0.9 seconds
Started Jul 24 05:17:43 PM PDT 24
Finished Jul 24 05:17:44 PM PDT 24
Peak memory 196772 kb
Host smart-9d23b787-f913-4be4-a9d2-0cfeabcc70c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ
=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.gpio_intr_with_filter_rand_intr_event.454471
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4124650887
Short name T135
Test name
Test status
Simulation time 135992769 ps
CPU time 1.13 seconds
Started Jul 24 05:17:57 PM PDT 24
Finished Jul 24 05:17:58 PM PDT 24
Peak memory 196908 kb
Host smart-d906b11e-7b12-4905-b42a-4191ef075fd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124650887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4124650887
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1562613687
Short name T106
Test name
Test status
Simulation time 685303735 ps
CPU time 1.25 seconds
Started Jul 24 05:18:02 PM PDT 24
Finished Jul 24 05:18:03 PM PDT 24
Peak memory 197504 kb
Host smart-c19534fd-d9c8-4ff8-b9be-690be2222f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562613687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1562613687
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1141025964
Short name T489
Test name
Test status
Simulation time 319208516 ps
CPU time 0.97 seconds
Started Jul 24 05:18:00 PM PDT 24
Finished Jul 24 05:18:02 PM PDT 24
Peak memory 196364 kb
Host smart-27e03d0a-302f-470f-b980-3d005f0d0c67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141025964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1141025964
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3435131248
Short name T604
Test name
Test status
Simulation time 921133072 ps
CPU time 5.9 seconds
Started Jul 24 05:17:53 PM PDT 24
Finished Jul 24 05:18:04 PM PDT 24
Peak memory 198476 kb
Host smart-92aeefd5-ac20-42cc-98d9-a529af42b860
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435131248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3435131248
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.4056565606
Short name T417
Test name
Test status
Simulation time 47437479 ps
CPU time 1.19 seconds
Started Jul 24 05:18:04 PM PDT 24
Finished Jul 24 05:18:05 PM PDT 24
Peak memory 197104 kb
Host smart-d2d9b592-2399-470f-8468-44c77b0d2cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056565606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.4056565606
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1273774648
Short name T403
Test name
Test status
Simulation time 98797311 ps
CPU time 0.98 seconds
Started Jul 24 05:17:50 PM PDT 24
Finished Jul 24 05:17:51 PM PDT 24
Peak memory 196860 kb
Host smart-caddea21-f463-4640-8ee7-ded2fa6a7e17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273774648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1273774648
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.4180702509
Short name T23
Test name
Test status
Simulation time 23358796920 ps
CPU time 93.02 seconds
Started Jul 24 05:17:51 PM PDT 24
Finished Jul 24 05:19:24 PM PDT 24
Peak memory 198532 kb
Host smart-54b54a58-3526-4ca0-8669-c6a65138f207
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180702509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4180702509
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2595006042
Short name T274
Test name
Test status
Simulation time 177863346610 ps
CPU time 771.04 seconds
Started Jul 24 05:18:00 PM PDT 24
Finished Jul 24 05:30:51 PM PDT 24
Peak memory 198768 kb
Host smart-cce47717-58f0-416a-8a86-8e602c6c8457
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2595006042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2595006042
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3702881598
Short name T517
Test name
Test status
Simulation time 58327163 ps
CPU time 0.57 seconds
Started Jul 24 05:17:51 PM PDT 24
Finished Jul 24 05:17:52 PM PDT 24
Peak memory 195128 kb
Host smart-b0ff5019-da60-4d02-bc28-3d8262ecff8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702881598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3702881598
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.987400121
Short name T500
Test name
Test status
Simulation time 83556493 ps
CPU time 0.67 seconds
Started Jul 24 05:17:54 PM PDT 24
Finished Jul 24 05:17:54 PM PDT 24
Peak memory 194380 kb
Host smart-55039fd4-f41b-4ef6-9aaf-0762f6a1da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987400121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.987400121
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.928821663
Short name T206
Test name
Test status
Simulation time 1996806794 ps
CPU time 23.16 seconds
Started Jul 24 05:18:20 PM PDT 24
Finished Jul 24 05:18:48 PM PDT 24
Peak memory 197500 kb
Host smart-ca321d18-41b7-4584-814a-f51df0ad2339
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928821663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.928821663
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1216245389
Short name T450
Test name
Test status
Simulation time 278211613 ps
CPU time 1 seconds
Started Jul 24 05:18:02 PM PDT 24
Finished Jul 24 05:18:03 PM PDT 24
Peak memory 197000 kb
Host smart-a5844bc9-18b9-4370-98a1-ffec099f5d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216245389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1216245389
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1983678509
Short name T591
Test name
Test status
Simulation time 95337724 ps
CPU time 1.24 seconds
Started Jul 24 05:17:51 PM PDT 24
Finished Jul 24 05:17:52 PM PDT 24
Peak memory 197748 kb
Host smart-3841bf21-2649-4613-a884-bb7b240cb845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983678509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1983678509
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2110250762
Short name T120
Test name
Test status
Simulation time 130742912 ps
CPU time 2.57 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:18:08 PM PDT 24
Peak memory 196816 kb
Host smart-904b4519-6509-465a-b241-16f6fb9f600d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110250762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2110250762
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.838684537
Short name T533
Test name
Test status
Simulation time 593535174 ps
CPU time 1.64 seconds
Started Jul 24 05:18:12 PM PDT 24
Finished Jul 24 05:18:14 PM PDT 24
Peak memory 196420 kb
Host smart-4389e001-20bb-4751-bf3f-abf1daea9326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838684537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
838684537
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3349341777
Short name T496
Test name
Test status
Simulation time 123036491 ps
CPU time 1.22 seconds
Started Jul 24 05:17:55 PM PDT 24
Finished Jul 24 05:17:56 PM PDT 24
Peak memory 197572 kb
Host smart-90f8154d-0bd0-42c6-891e-7a1203d64a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349341777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3349341777
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2864568565
Short name T181
Test name
Test status
Simulation time 20355800 ps
CPU time 0.82 seconds
Started Jul 24 05:17:57 PM PDT 24
Finished Jul 24 05:17:58 PM PDT 24
Peak memory 196360 kb
Host smart-0b9a16b9-69d0-4123-8d8a-9495d3e46f34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864568565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2864568565
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4180626068
Short name T336
Test name
Test status
Simulation time 567297224 ps
CPU time 3.41 seconds
Started Jul 24 05:17:43 PM PDT 24
Finished Jul 24 05:17:47 PM PDT 24
Peak memory 198516 kb
Host smart-e19fb608-b289-47d3-b349-f2c1d5a0f399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180626068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4180626068
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.895081844
Short name T441
Test name
Test status
Simulation time 81287737 ps
CPU time 0.77 seconds
Started Jul 24 05:17:59 PM PDT 24
Finished Jul 24 05:18:00 PM PDT 24
Peak memory 195668 kb
Host smart-e5918648-a250-4b43-adc5-2792c82b00a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895081844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.895081844
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.210588652
Short name T457
Test name
Test status
Simulation time 567228651 ps
CPU time 1.36 seconds
Started Jul 24 05:18:04 PM PDT 24
Finished Jul 24 05:18:06 PM PDT 24
Peak memory 197180 kb
Host smart-093e24be-f6eb-4683-a831-0d84e8dd5b75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210588652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.210588652
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.749285282
Short name T666
Test name
Test status
Simulation time 14791170690 ps
CPU time 45.4 seconds
Started Jul 24 05:17:54 PM PDT 24
Finished Jul 24 05:18:40 PM PDT 24
Peak memory 198640 kb
Host smart-e1f7de32-6db8-4049-908a-ba3037a49a0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749285282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.749285282
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2222755615
Short name T48
Test name
Test status
Simulation time 24071137236 ps
CPU time 714.2 seconds
Started Jul 24 05:18:19 PM PDT 24
Finished Jul 24 05:30:13 PM PDT 24
Peak memory 198360 kb
Host smart-0535bb35-30fb-4432-9008-eaffc4312ac3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2222755615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2222755615
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.281348951
Short name T537
Test name
Test status
Simulation time 12965252 ps
CPU time 0.56 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:09 PM PDT 24
Peak memory 194592 kb
Host smart-e052da7d-39c9-4042-b301-f6dc8556cc53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281348951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.281348951
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.665833847
Short name T434
Test name
Test status
Simulation time 34544048 ps
CPU time 0.83 seconds
Started Jul 24 05:17:52 PM PDT 24
Finished Jul 24 05:17:53 PM PDT 24
Peak memory 196420 kb
Host smart-93048c40-4f92-43d0-9a17-f91728f03b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665833847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.665833847
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.192411138
Short name T405
Test name
Test status
Simulation time 745324229 ps
CPU time 20.38 seconds
Started Jul 24 05:17:46 PM PDT 24
Finished Jul 24 05:18:07 PM PDT 24
Peak memory 197416 kb
Host smart-e2d63fda-19a1-450c-90a0-f1fa9aa174ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192411138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.192411138
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2708768592
Short name T9
Test name
Test status
Simulation time 364758413 ps
CPU time 0.97 seconds
Started Jul 24 05:17:45 PM PDT 24
Finished Jul 24 05:17:46 PM PDT 24
Peak memory 197072 kb
Host smart-4579312f-d30e-4773-83d5-7171866a15c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708768592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2708768592
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3931084499
Short name T491
Test name
Test status
Simulation time 300379602 ps
CPU time 1.37 seconds
Started Jul 24 05:17:59 PM PDT 24
Finished Jul 24 05:18:00 PM PDT 24
Peak memory 198496 kb
Host smart-ba1c9dca-cb3b-4dae-aab1-9aa81ef37510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931084499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3931084499
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1994256317
Short name T178
Test name
Test status
Simulation time 147340882 ps
CPU time 2.91 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:11 PM PDT 24
Peak memory 198444 kb
Host smart-f8531ba6-1e21-414f-ad47-3ad24f0544f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994256317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1994256317
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3460532455
Short name T701
Test name
Test status
Simulation time 199783340 ps
CPU time 1.56 seconds
Started Jul 24 05:17:50 PM PDT 24
Finished Jul 24 05:17:51 PM PDT 24
Peak memory 196608 kb
Host smart-4dafc5f8-5119-46bd-8479-8dcc17e83df8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460532455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3460532455
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2685942430
Short name T546
Test name
Test status
Simulation time 47951352 ps
CPU time 1.2 seconds
Started Jul 24 05:18:06 PM PDT 24
Finished Jul 24 05:18:07 PM PDT 24
Peak memory 197168 kb
Host smart-e96852ca-a5b3-4a3f-9eac-66f6812c7ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685942430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2685942430
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1859250855
Short name T291
Test name
Test status
Simulation time 48989573 ps
CPU time 0.91 seconds
Started Jul 24 05:17:51 PM PDT 24
Finished Jul 24 05:17:52 PM PDT 24
Peak memory 196468 kb
Host smart-097d14d1-cedb-4591-bddc-b9a56b9101e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859250855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1859250855
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.236635394
Short name T315
Test name
Test status
Simulation time 845797672 ps
CPU time 3.53 seconds
Started Jul 24 05:18:02 PM PDT 24
Finished Jul 24 05:18:06 PM PDT 24
Peak memory 198248 kb
Host smart-dd34b216-d44f-41c7-9074-e65b11df16d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236635394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.236635394
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1832713618
Short name T324
Test name
Test status
Simulation time 122991217 ps
CPU time 1.24 seconds
Started Jul 24 05:17:49 PM PDT 24
Finished Jul 24 05:17:50 PM PDT 24
Peak memory 197316 kb
Host smart-05227cf4-f9f3-4184-8f1b-203e66e59fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832713618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1832713618
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.277792275
Short name T601
Test name
Test status
Simulation time 47097620 ps
CPU time 1.2 seconds
Started Jul 24 05:18:19 PM PDT 24
Finished Jul 24 05:18:20 PM PDT 24
Peak memory 195992 kb
Host smart-d3256850-202c-4a33-a1ca-ae5f755ee045
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277792275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.277792275
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.4008100961
Short name T586
Test name
Test status
Simulation time 53458855011 ps
CPU time 147.15 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:20:34 PM PDT 24
Peak memory 198520 kb
Host smart-c9249ae3-7e39-4c10-9108-fca30cdc53f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008100961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.4008100961
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1646492370
Short name T458
Test name
Test status
Simulation time 18611056 ps
CPU time 0.55 seconds
Started Jul 24 05:18:01 PM PDT 24
Finished Jul 24 05:18:01 PM PDT 24
Peak memory 194332 kb
Host smart-1ab0d1dd-ad7f-4a84-a93e-eef338787e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646492370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1646492370
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.4008627839
Short name T248
Test name
Test status
Simulation time 493703122 ps
CPU time 0.83 seconds
Started Jul 24 05:17:58 PM PDT 24
Finished Jul 24 05:17:59 PM PDT 24
Peak memory 196972 kb
Host smart-a8a1cded-e416-466e-9b29-e5577d4655bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008627839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.4008627839
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.993479749
Short name T227
Test name
Test status
Simulation time 370222914 ps
CPU time 12.3 seconds
Started Jul 24 05:18:00 PM PDT 24
Finished Jul 24 05:18:13 PM PDT 24
Peak memory 197480 kb
Host smart-c34f289f-5dce-4c56-b289-19fab9e7acd1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993479749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.993479749
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.936802263
Short name T632
Test name
Test status
Simulation time 308279661 ps
CPU time 0.9 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:09 PM PDT 24
Peak memory 197588 kb
Host smart-04ca5b01-aaed-4161-ade4-f63a9a7d2c4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936802263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.936802263
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.224177929
Short name T340
Test name
Test status
Simulation time 48915236 ps
CPU time 0.93 seconds
Started Jul 24 05:17:52 PM PDT 24
Finished Jul 24 05:17:53 PM PDT 24
Peak memory 197676 kb
Host smart-f4092438-1808-40b8-9e00-3787b5d38ed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224177929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.224177929
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.156362577
Short name T483
Test name
Test status
Simulation time 51027394 ps
CPU time 2.02 seconds
Started Jul 24 05:18:02 PM PDT 24
Finished Jul 24 05:18:04 PM PDT 24
Peak memory 196744 kb
Host smart-930bd02c-0ef7-4641-9839-b6d2309ec5aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156362577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.156362577
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2400219013
Short name T645
Test name
Test status
Simulation time 566209881 ps
CPU time 1.79 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:18:09 PM PDT 24
Peak memory 196568 kb
Host smart-7505d5d3-368c-4f3b-9749-9672691f2653
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400219013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2400219013
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2736967650
Short name T296
Test name
Test status
Simulation time 69945315 ps
CPU time 1.16 seconds
Started Jul 24 05:17:47 PM PDT 24
Finished Jul 24 05:17:48 PM PDT 24
Peak memory 197092 kb
Host smart-d9543e8a-07aa-43d9-ac6b-92218bde87d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736967650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2736967650
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1391968219
Short name T290
Test name
Test status
Simulation time 18451073 ps
CPU time 0.7 seconds
Started Jul 24 05:18:04 PM PDT 24
Finished Jul 24 05:18:04 PM PDT 24
Peak memory 195452 kb
Host smart-98087b53-aa8f-4003-80ce-065622109d41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391968219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1391968219
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3615105070
Short name T692
Test name
Test status
Simulation time 738675852 ps
CPU time 3.46 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:12 PM PDT 24
Peak memory 198528 kb
Host smart-9d17858a-3f6a-44fd-b6c4-337c3df493cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615105070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3615105070
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3082993882
Short name T497
Test name
Test status
Simulation time 104964725 ps
CPU time 1.09 seconds
Started Jul 24 05:17:43 PM PDT 24
Finished Jul 24 05:17:45 PM PDT 24
Peak memory 196352 kb
Host smart-b41cd109-f581-4bcc-861f-05ea78a69c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082993882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3082993882
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3791492187
Short name T223
Test name
Test status
Simulation time 36568334 ps
CPU time 0.92 seconds
Started Jul 24 05:17:50 PM PDT 24
Finished Jul 24 05:17:51 PM PDT 24
Peak memory 197680 kb
Host smart-d79ecaa8-83ba-480a-83a0-6f27aab5c249
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791492187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3791492187
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.4246743405
Short name T6
Test name
Test status
Simulation time 32467779234 ps
CPU time 95.03 seconds
Started Jul 24 05:18:03 PM PDT 24
Finished Jul 24 05:19:38 PM PDT 24
Peak memory 198712 kb
Host smart-be67be20-70bd-4196-95f9-c7f634f61caf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246743405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.4246743405
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4193392542
Short name T140
Test name
Test status
Simulation time 45291736 ps
CPU time 0.59 seconds
Started Jul 24 05:18:06 PM PDT 24
Finished Jul 24 05:18:06 PM PDT 24
Peak memory 194408 kb
Host smart-8c352ed5-4bcb-44e1-94fb-6b7ebfd833aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193392542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4193392542
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.13323280
Short name T337
Test name
Test status
Simulation time 32849720 ps
CPU time 0.65 seconds
Started Jul 24 05:18:09 PM PDT 24
Finished Jul 24 05:18:10 PM PDT 24
Peak memory 194524 kb
Host smart-25520102-17e1-4fc8-bc79-367982d9c006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13323280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.13323280
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1978680923
Short name T431
Test name
Test status
Simulation time 849423937 ps
CPU time 12.04 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:18:20 PM PDT 24
Peak memory 197004 kb
Host smart-b71d5aab-732e-470e-ad61-4d3948c83fb4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978680923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1978680923
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2814430649
Short name T298
Test name
Test status
Simulation time 67710843 ps
CPU time 0.89 seconds
Started Jul 24 05:18:18 PM PDT 24
Finished Jul 24 05:18:20 PM PDT 24
Peak memory 196984 kb
Host smart-7aac5c07-ae3e-4292-81a9-1bf7a8aac886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814430649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2814430649
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1344087534
Short name T218
Test name
Test status
Simulation time 47837249 ps
CPU time 0.97 seconds
Started Jul 24 05:18:02 PM PDT 24
Finished Jul 24 05:18:03 PM PDT 24
Peak memory 196168 kb
Host smart-10f8b156-ec0a-4dea-b94e-3ced9969bc89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344087534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1344087534
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2660942061
Short name T547
Test name
Test status
Simulation time 366052583 ps
CPU time 3.39 seconds
Started Jul 24 05:17:51 PM PDT 24
Finished Jul 24 05:17:55 PM PDT 24
Peak memory 196952 kb
Host smart-83b94874-1abf-4329-8f98-21e340bdbb5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660942061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2660942061
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.945215080
Short name T341
Test name
Test status
Simulation time 83898016 ps
CPU time 1.91 seconds
Started Jul 24 05:18:01 PM PDT 24
Finished Jul 24 05:18:03 PM PDT 24
Peak memory 196432 kb
Host smart-967e9c90-e6cc-4268-9b03-477ba8588aa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945215080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
945215080
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3028999718
Short name T576
Test name
Test status
Simulation time 32941470 ps
CPU time 0.71 seconds
Started Jul 24 05:18:06 PM PDT 24
Finished Jul 24 05:18:07 PM PDT 24
Peak memory 196512 kb
Host smart-533eb457-8e11-4c8b-82d1-d7e0bf35c3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028999718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3028999718
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.4157552264
Short name T482
Test name
Test status
Simulation time 49719175 ps
CPU time 1.06 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:09 PM PDT 24
Peak memory 196476 kb
Host smart-e5554a78-59a6-4fde-87d0-19797c0fce08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157552264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.4157552264
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2222643039
Short name T513
Test name
Test status
Simulation time 80883460 ps
CPU time 3.23 seconds
Started Jul 24 05:18:09 PM PDT 24
Finished Jul 24 05:18:12 PM PDT 24
Peak memory 198428 kb
Host smart-dd383644-3b32-48fc-a6b5-82f1488c04cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222643039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2222643039
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1817689020
Short name T98
Test name
Test status
Simulation time 291345388 ps
CPU time 1.37 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:18:08 PM PDT 24
Peak memory 198560 kb
Host smart-f98a0e71-bc57-4218-80bc-0046f24cfc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817689020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1817689020
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.166860650
Short name T11
Test name
Test status
Simulation time 30194230 ps
CPU time 0.94 seconds
Started Jul 24 05:18:01 PM PDT 24
Finished Jul 24 05:18:02 PM PDT 24
Peak memory 195932 kb
Host smart-03ac23b6-50cc-4969-81a9-72a2ed6bfd39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166860650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.166860650
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2851836522
Short name T5
Test name
Test status
Simulation time 88331524942 ps
CPU time 190.87 seconds
Started Jul 24 05:17:50 PM PDT 24
Finished Jul 24 05:21:01 PM PDT 24
Peak memory 198484 kb
Host smart-a389f151-a065-494f-9530-707cc272b7f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851836522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2851836522
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.453087035
Short name T34
Test name
Test status
Simulation time 16725338 ps
CPU time 0.59 seconds
Started Jul 24 05:18:09 PM PDT 24
Finished Jul 24 05:18:10 PM PDT 24
Peak memory 195008 kb
Host smart-b8ac937a-bf69-44ee-8bb1-e7975e6aebb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453087035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.453087035
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.873505792
Short name T509
Test name
Test status
Simulation time 54657485 ps
CPU time 0.59 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:09 PM PDT 24
Peak memory 194984 kb
Host smart-216a88bf-fd4a-4e9b-9bbe-3afc82e3b94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873505792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.873505792
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1619744135
Short name T538
Test name
Test status
Simulation time 3491983966 ps
CPU time 24.06 seconds
Started Jul 24 05:18:08 PM PDT 24
Finished Jul 24 05:18:33 PM PDT 24
Peak memory 197356 kb
Host smart-42067a87-f43d-4dad-852e-a2ecdc42d279
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619744135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1619744135
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3546973105
Short name T616
Test name
Test status
Simulation time 21531407 ps
CPU time 0.65 seconds
Started Jul 24 05:18:05 PM PDT 24
Finished Jul 24 05:18:05 PM PDT 24
Peak memory 195292 kb
Host smart-22d56f31-72d0-4876-ba68-dba5740004fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546973105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3546973105
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3607758243
Short name T150
Test name
Test status
Simulation time 135968091 ps
CPU time 1.12 seconds
Started Jul 24 05:17:59 PM PDT 24
Finished Jul 24 05:18:01 PM PDT 24
Peak memory 197324 kb
Host smart-b1294897-7d38-46e7-8e22-a8db062cb153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607758243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3607758243
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.789466780
Short name T534
Test name
Test status
Simulation time 207231705 ps
CPU time 2.28 seconds
Started Jul 24 05:18:09 PM PDT 24
Finished Jul 24 05:18:11 PM PDT 24
Peak memory 198648 kb
Host smart-4bb59b1c-1e9e-48c2-ba01-d86f8d9389a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789466780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.789466780
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1373945871
Short name T617
Test name
Test status
Simulation time 81736262 ps
CPU time 1.85 seconds
Started Jul 24 05:17:59 PM PDT 24
Finished Jul 24 05:18:01 PM PDT 24
Peak memory 196968 kb
Host smart-4e98403d-78c6-4d0d-9914-3d729ed2959c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373945871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1373945871
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3046508344
Short name T325
Test name
Test status
Simulation time 91425712 ps
CPU time 1 seconds
Started Jul 24 05:18:13 PM PDT 24
Finished Jul 24 05:18:14 PM PDT 24
Peak memory 197176 kb
Host smart-5994de13-b405-4464-8cc0-cb38707136bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046508344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3046508344
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2772067356
Short name T630
Test name
Test status
Simulation time 130494006 ps
CPU time 1.17 seconds
Started Jul 24 05:17:59 PM PDT 24
Finished Jul 24 05:18:01 PM PDT 24
Peak memory 197056 kb
Host smart-656990dc-9b8c-49f8-bba3-66e9a6075ea3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772067356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2772067356
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.4070840228
Short name T215
Test name
Test status
Simulation time 4058002998 ps
CPU time 3.46 seconds
Started Jul 24 05:18:00 PM PDT 24
Finished Jul 24 05:18:04 PM PDT 24
Peak memory 198468 kb
Host smart-054882e6-7380-4f5a-bb2b-c20b81bc9fbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070840228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.4070840228
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3059047242
Short name T416
Test name
Test status
Simulation time 761858117 ps
CPU time 1.25 seconds
Started Jul 24 05:17:57 PM PDT 24
Finished Jul 24 05:17:58 PM PDT 24
Peak memory 196844 kb
Host smart-b787c088-f047-4bdd-87ee-dfde2a589d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059047242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3059047242
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1266797383
Short name T229
Test name
Test status
Simulation time 320676129 ps
CPU time 0.81 seconds
Started Jul 24 05:18:07 PM PDT 24
Finished Jul 24 05:18:08 PM PDT 24
Peak memory 196448 kb
Host smart-b51cd3f8-6c4a-48b7-bd73-d0f8794031d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266797383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1266797383
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3307284081
Short name T568
Test name
Test status
Simulation time 19788903754 ps
CPU time 78.25 seconds
Started Jul 24 05:18:04 PM PDT 24
Finished Jul 24 05:19:22 PM PDT 24
Peak memory 198592 kb
Host smart-1b27c15f-a0ab-4d0f-b78b-675157a45d17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307284081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3307284081
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2570879492
Short name T445
Test name
Test status
Simulation time 49988345861 ps
CPU time 864.36 seconds
Started Jul 24 05:18:15 PM PDT 24
Finished Jul 24 05:32:39 PM PDT 24
Peak memory 198632 kb
Host smart-e34276e0-bff1-4270-965a-6779cb057966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2570879492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2570879492
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.854610012
Short name T233
Test name
Test status
Simulation time 12031247 ps
CPU time 0.57 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:49 PM PDT 24
Peak memory 194384 kb
Host smart-efce9800-2d88-4aac-919a-6b2429d4c732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854610012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.854610012
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3961303326
Short name T327
Test name
Test status
Simulation time 96875300 ps
CPU time 0.9 seconds
Started Jul 24 05:16:34 PM PDT 24
Finished Jul 24 05:16:35 PM PDT 24
Peak memory 197128 kb
Host smart-380b85cc-abf6-41e9-a010-c65df3c80b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961303326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3961303326
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2279024655
Short name T459
Test name
Test status
Simulation time 471964148 ps
CPU time 15.54 seconds
Started Jul 24 05:16:42 PM PDT 24
Finished Jul 24 05:16:58 PM PDT 24
Peak memory 197436 kb
Host smart-1fcc36ec-97af-4e56-9bc8-554f6be37f9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279024655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2279024655
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1582984932
Short name T594
Test name
Test status
Simulation time 40858570 ps
CPU time 0.75 seconds
Started Jul 24 05:16:39 PM PDT 24
Finished Jul 24 05:16:40 PM PDT 24
Peak memory 196328 kb
Host smart-e26e6d1f-8120-440e-ad94-3d54fd2ff9ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582984932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1582984932
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.4167779265
Short name T408
Test name
Test status
Simulation time 144459390 ps
CPU time 1.15 seconds
Started Jul 24 05:16:27 PM PDT 24
Finished Jul 24 05:16:29 PM PDT 24
Peak memory 196480 kb
Host smart-e0edc2e3-dbbd-4555-b449-65cda0bfb1f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167779265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.4167779265
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3133899668
Short name T638
Test name
Test status
Simulation time 79347742 ps
CPU time 2.74 seconds
Started Jul 24 05:16:59 PM PDT 24
Finished Jul 24 05:17:02 PM PDT 24
Peak memory 198428 kb
Host smart-1b30b472-2936-4338-a76b-a32fc18d8793
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133899668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3133899668
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3725537286
Short name T444
Test name
Test status
Simulation time 201801577 ps
CPU time 2.16 seconds
Started Jul 24 05:16:30 PM PDT 24
Finished Jul 24 05:16:33 PM PDT 24
Peak memory 197872 kb
Host smart-ab778c96-4efe-44c2-9e45-684ab0fc671f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725537286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3725537286
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.29682820
Short name T395
Test name
Test status
Simulation time 36224524 ps
CPU time 0.8 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:16:36 PM PDT 24
Peak memory 195832 kb
Host smart-10b43cd2-6205-41d7-8578-d689c4cac408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29682820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.29682820
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4043909960
Short name T498
Test name
Test status
Simulation time 48486303 ps
CPU time 1.18 seconds
Started Jul 24 05:16:31 PM PDT 24
Finished Jul 24 05:16:32 PM PDT 24
Peak memory 196520 kb
Host smart-284d1682-1943-43a0-ae34-4456d63911a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043909960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4043909960
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3012808110
Short name T420
Test name
Test status
Simulation time 303293511 ps
CPU time 3.11 seconds
Started Jul 24 05:16:30 PM PDT 24
Finished Jul 24 05:16:33 PM PDT 24
Peak memory 198488 kb
Host smart-a5bac411-bdc8-4b82-bc85-48030a2bd643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012808110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3012808110
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.326952879
Short name T25
Test name
Test status
Simulation time 728702927 ps
CPU time 1.4 seconds
Started Jul 24 05:16:37 PM PDT 24
Finished Jul 24 05:16:39 PM PDT 24
Peak memory 198500 kb
Host smart-78370335-8bc5-4a01-8f5f-505b9c841a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326952879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.326952879
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.4232388146
Short name T359
Test name
Test status
Simulation time 45170246 ps
CPU time 1.3 seconds
Started Jul 24 05:16:33 PM PDT 24
Finished Jul 24 05:16:35 PM PDT 24
Peak memory 197144 kb
Host smart-a9a4937d-6eea-413e-a669-3b2d186747ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232388146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.4232388146
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.437833988
Short name T288
Test name
Test status
Simulation time 6493530924 ps
CPU time 171.33 seconds
Started Jul 24 05:16:46 PM PDT 24
Finished Jul 24 05:19:37 PM PDT 24
Peak memory 198504 kb
Host smart-08cd80b8-15f1-4cc4-9d30-caf55cee3349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437833988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.437833988
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2371397430
Short name T643
Test name
Test status
Simulation time 33231248107 ps
CPU time 899.19 seconds
Started Jul 24 05:16:39 PM PDT 24
Finished Jul 24 05:31:38 PM PDT 24
Peak memory 198948 kb
Host smart-c6b9a600-7fdf-43b2-9f1e-2ca22a3f6fd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2371397430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2371397430
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.122332321
Short name T177
Test name
Test status
Simulation time 13901552 ps
CPU time 0.58 seconds
Started Jul 24 05:16:46 PM PDT 24
Finished Jul 24 05:16:47 PM PDT 24
Peak memory 195116 kb
Host smart-2335aab2-c979-4a94-beaf-a644dfbcaeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122332321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.122332321
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.119992959
Short name T595
Test name
Test status
Simulation time 103506477 ps
CPU time 0.82 seconds
Started Jul 24 05:16:55 PM PDT 24
Finished Jul 24 05:16:56 PM PDT 24
Peak memory 196852 kb
Host smart-97034aba-8145-43ec-8e02-a83c09611b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119992959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.119992959
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.331711333
Short name T636
Test name
Test status
Simulation time 681122566 ps
CPU time 22.99 seconds
Started Jul 24 05:16:57 PM PDT 24
Finished Jul 24 05:17:20 PM PDT 24
Peak memory 197668 kb
Host smart-ee9ca8ae-80fd-4504-b82f-2df99edf9122
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331711333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.331711333
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.945617505
Short name T593
Test name
Test status
Simulation time 28681989 ps
CPU time 0.65 seconds
Started Jul 24 05:16:37 PM PDT 24
Finished Jul 24 05:16:38 PM PDT 24
Peak memory 195004 kb
Host smart-afee96f5-37bd-47ad-afde-27f2c55d1efb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945617505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.945617505
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1146770349
Short name T670
Test name
Test status
Simulation time 290417026 ps
CPU time 1.16 seconds
Started Jul 24 05:16:46 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 196272 kb
Host smart-0797695c-b01d-4b5a-a5bc-2c61006c14b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146770349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1146770349
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.226132919
Short name T220
Test name
Test status
Simulation time 87984244 ps
CPU time 2.93 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 198648 kb
Host smart-4041cd81-3dd6-4c06-bdd3-6e1a749ba7ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226132919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.226132919
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1588251641
Short name T214
Test name
Test status
Simulation time 148645379 ps
CPU time 1.38 seconds
Started Jul 24 05:16:41 PM PDT 24
Finished Jul 24 05:16:43 PM PDT 24
Peak memory 196412 kb
Host smart-1bb757ac-810d-42f6-bc06-a50eef19a455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588251641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1588251641
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1582334889
Short name T610
Test name
Test status
Simulation time 353023357 ps
CPU time 1.07 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 196548 kb
Host smart-0cdf933b-b648-48a7-a837-7b84435e1131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582334889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1582334889
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2846225977
Short name T702
Test name
Test status
Simulation time 313872027 ps
CPU time 1.27 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 196216 kb
Host smart-4770d094-27e0-40d5-a7f4-90687f7949a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846225977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2846225977
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.751325978
Short name T442
Test name
Test status
Simulation time 595521990 ps
CPU time 2.52 seconds
Started Jul 24 05:16:38 PM PDT 24
Finished Jul 24 05:16:41 PM PDT 24
Peak memory 198488 kb
Host smart-e074844a-7a01-4125-9f4a-033d0d283198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751325978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.751325978
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3333926717
Short name T685
Test name
Test status
Simulation time 154223830 ps
CPU time 1.09 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:45 PM PDT 24
Peak memory 196840 kb
Host smart-6b9d3ab2-95b1-4d85-8c60-f182f8e410ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333926717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3333926717
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2058852184
Short name T142
Test name
Test status
Simulation time 31078216 ps
CPU time 0.86 seconds
Started Jul 24 05:16:34 PM PDT 24
Finished Jul 24 05:16:35 PM PDT 24
Peak memory 196928 kb
Host smart-4ff5dbd6-ddf6-46e1-93df-ba9e0e1efff9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058852184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2058852184
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1234411066
Short name T648
Test name
Test status
Simulation time 1626939715 ps
CPU time 35.35 seconds
Started Jul 24 05:16:45 PM PDT 24
Finished Jul 24 05:17:20 PM PDT 24
Peak memory 198492 kb
Host smart-82aaf388-df4b-46b2-9e0d-bea2802775eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234411066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1234411066
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2955965044
Short name T93
Test name
Test status
Simulation time 31789194 ps
CPU time 0.55 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 195028 kb
Host smart-310ba140-a1d8-4a60-8c10-ab1825dd37a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955965044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2955965044
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2082482141
Short name T451
Test name
Test status
Simulation time 59483221 ps
CPU time 0.7 seconds
Started Jul 24 05:17:00 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 196304 kb
Host smart-ff44ba3b-0a20-46f1-ab21-8f61a5930634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082482141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2082482141
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1187768630
Short name T264
Test name
Test status
Simulation time 399958425 ps
CPU time 19.97 seconds
Started Jul 24 05:16:46 PM PDT 24
Finished Jul 24 05:17:06 PM PDT 24
Peak memory 197432 kb
Host smart-23c98983-7354-47f1-be8c-18e68a26c81e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187768630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1187768630
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1088328974
Short name T236
Test name
Test status
Simulation time 55572907 ps
CPU time 0.6 seconds
Started Jul 24 05:16:45 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 194844 kb
Host smart-2eaab5cf-f341-4069-a43d-d4d7fe56d3b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088328974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1088328974
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.601718881
Short name T202
Test name
Test status
Simulation time 23284097 ps
CPU time 0.69 seconds
Started Jul 24 05:16:41 PM PDT 24
Finished Jul 24 05:16:42 PM PDT 24
Peak memory 195908 kb
Host smart-c8df6caf-28ba-4493-8b03-65fe65aba27e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601718881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.601718881
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.557408761
Short name T527
Test name
Test status
Simulation time 104970166 ps
CPU time 1.8 seconds
Started Jul 24 05:16:43 PM PDT 24
Finished Jul 24 05:16:45 PM PDT 24
Peak memory 198708 kb
Host smart-c9618826-5219-4556-9a6c-ee249c828be9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557408761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.557408761
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2541498978
Short name T343
Test name
Test status
Simulation time 347066284 ps
CPU time 2.67 seconds
Started Jul 24 05:16:42 PM PDT 24
Finished Jul 24 05:16:45 PM PDT 24
Peak memory 196320 kb
Host smart-989598b5-14e7-4aa5-a5be-a492406e1bdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541498978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2541498978
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3194402691
Short name T89
Test name
Test status
Simulation time 77666432 ps
CPU time 1.32 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:45 PM PDT 24
Peak memory 197668 kb
Host smart-7a3a3e02-631a-4d3b-b488-ffcbc5c3304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194402691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3194402691
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1700371834
Short name T357
Test name
Test status
Simulation time 101543293 ps
CPU time 1.03 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:16:36 PM PDT 24
Peak memory 196388 kb
Host smart-23629582-cf1a-4bf5-8d9f-f485c3922366
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700371834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1700371834
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2377486141
Short name T125
Test name
Test status
Simulation time 636861848 ps
CPU time 4.97 seconds
Started Jul 24 05:16:52 PM PDT 24
Finished Jul 24 05:16:57 PM PDT 24
Peak memory 198424 kb
Host smart-cbbf7d74-212e-4706-b044-eceb897e5217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377486141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2377486141
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.4221600777
Short name T687
Test name
Test status
Simulation time 132386180 ps
CPU time 1.43 seconds
Started Jul 24 05:17:18 PM PDT 24
Finished Jul 24 05:17:19 PM PDT 24
Peak memory 197336 kb
Host smart-aa7065f9-fa16-4b54-9920-5febc32934ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221600777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.4221600777
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2239257257
Short name T207
Test name
Test status
Simulation time 50275960 ps
CPU time 0.79 seconds
Started Jul 24 05:16:42 PM PDT 24
Finished Jul 24 05:16:44 PM PDT 24
Peak memory 195828 kb
Host smart-ab9e66f1-5691-4fa6-b7aa-9180442a8bf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239257257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2239257257
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1320588666
Short name T415
Test name
Test status
Simulation time 1024030752 ps
CPU time 21.65 seconds
Started Jul 24 05:16:31 PM PDT 24
Finished Jul 24 05:16:53 PM PDT 24
Peak memory 198524 kb
Host smart-363d42fb-86b8-4a16-9604-1da7307021a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320588666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1320588666
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1116194277
Short name T370
Test name
Test status
Simulation time 30840629336 ps
CPU time 203.27 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:20:12 PM PDT 24
Peak memory 198684 kb
Host smart-d3629547-5a7c-4f93-975f-571623ec643e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1116194277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1116194277
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.121510644
Short name T141
Test name
Test status
Simulation time 18003082 ps
CPU time 0.6 seconds
Started Jul 24 05:16:45 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 195040 kb
Host smart-e5aaaeec-dbb3-4b9a-9e4f-e20199e36e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121510644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.121510644
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1133420179
Short name T131
Test name
Test status
Simulation time 47132046 ps
CPU time 0.78 seconds
Started Jul 24 05:17:00 PM PDT 24
Finished Jul 24 05:17:01 PM PDT 24
Peak memory 195756 kb
Host smart-3627f728-afb8-4306-a5a7-83148e0c930e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133420179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1133420179
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.673227241
Short name T700
Test name
Test status
Simulation time 850755129 ps
CPU time 24.03 seconds
Started Jul 24 05:16:41 PM PDT 24
Finished Jul 24 05:17:05 PM PDT 24
Peak memory 197420 kb
Host smart-5dd0f5aa-31a9-4179-a04f-5de22f52c6b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673227241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.673227241
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2467206926
Short name T558
Test name
Test status
Simulation time 59330404 ps
CPU time 0.89 seconds
Started Jul 24 05:16:42 PM PDT 24
Finished Jul 24 05:16:44 PM PDT 24
Peak memory 197368 kb
Host smart-ab78b8da-2723-4a78-8a74-b9df085557c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467206926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2467206926
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1615630749
Short name T400
Test name
Test status
Simulation time 384876998 ps
CPU time 1.29 seconds
Started Jul 24 05:16:57 PM PDT 24
Finished Jul 24 05:16:58 PM PDT 24
Peak memory 196556 kb
Host smart-e9837d99-171a-435e-9eba-e47170000a77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615630749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1615630749
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1289493152
Short name T282
Test name
Test status
Simulation time 69895587 ps
CPU time 2.74 seconds
Started Jul 24 05:16:33 PM PDT 24
Finished Jul 24 05:16:36 PM PDT 24
Peak memory 198556 kb
Host smart-255e7e2c-b411-43e2-86b0-f728705749fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289493152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1289493152
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2162312473
Short name T555
Test name
Test status
Simulation time 212401480 ps
CPU time 3.42 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:51 PM PDT 24
Peak memory 196416 kb
Host smart-75a80026-e44f-4357-8449-21d38c29566c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162312473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2162312473
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3746038067
Short name T714
Test name
Test status
Simulation time 90142683 ps
CPU time 1.04 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:46 PM PDT 24
Peak memory 197140 kb
Host smart-1d59129a-f2ae-4800-951e-352d4821c2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746038067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3746038067
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1047004234
Short name T330
Test name
Test status
Simulation time 243195166 ps
CPU time 1.24 seconds
Started Jul 24 05:16:39 PM PDT 24
Finished Jul 24 05:16:41 PM PDT 24
Peak memory 197516 kb
Host smart-34f99d46-6d16-46ba-93f3-9ffc4ca3c1ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047004234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1047004234
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3418887063
Short name T164
Test name
Test status
Simulation time 121701684 ps
CPU time 2.95 seconds
Started Jul 24 05:16:40 PM PDT 24
Finished Jul 24 05:16:43 PM PDT 24
Peak memory 198460 kb
Host smart-c5162b87-8ecb-4f34-8aff-1464cedd78a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418887063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3418887063
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1128393833
Short name T138
Test name
Test status
Simulation time 74543459 ps
CPU time 1.19 seconds
Started Jul 24 05:16:48 PM PDT 24
Finished Jul 24 05:16:49 PM PDT 24
Peak memory 197020 kb
Host smart-e8c903b9-867b-4bf6-a8f8-3913191ecbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128393833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1128393833
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2502889933
Short name T356
Test name
Test status
Simulation time 26855086 ps
CPU time 0.75 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 196320 kb
Host smart-73f2f646-b75f-445f-b9eb-1b115b478d2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502889933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2502889933
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2195097661
Short name T378
Test name
Test status
Simulation time 1374123502 ps
CPU time 32.13 seconds
Started Jul 24 05:16:41 PM PDT 24
Finished Jul 24 05:17:14 PM PDT 24
Peak memory 198592 kb
Host smart-42691a7b-1d10-4954-8d9a-294ea650a983
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195097661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2195097661
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3625478629
Short name T51
Test name
Test status
Simulation time 114948590597 ps
CPU time 1428.98 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:40:25 PM PDT 24
Peak memory 198796 kb
Host smart-c33d1e4f-f3a0-46f9-a59d-7a9039dddf72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3625478629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3625478629
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2455825477
Short name T688
Test name
Test status
Simulation time 53560370 ps
CPU time 0.57 seconds
Started Jul 24 05:16:47 PM PDT 24
Finished Jul 24 05:16:48 PM PDT 24
Peak memory 194612 kb
Host smart-cde8a56b-6852-4904-af39-ce306b679044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455825477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2455825477
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2610771006
Short name T552
Test name
Test status
Simulation time 20368805 ps
CPU time 0.69 seconds
Started Jul 24 05:16:40 PM PDT 24
Finished Jul 24 05:16:41 PM PDT 24
Peak memory 194384 kb
Host smart-7d19e14c-52ed-4032-910a-c361b397c665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610771006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2610771006
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3659430212
Short name T230
Test name
Test status
Simulation time 529346759 ps
CPU time 12.56 seconds
Started Jul 24 05:16:44 PM PDT 24
Finished Jul 24 05:16:57 PM PDT 24
Peak memory 196056 kb
Host smart-5d34f85b-00db-4ce4-a059-d79477b6d1d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659430212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3659430212
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3253650697
Short name T251
Test name
Test status
Simulation time 60057831 ps
CPU time 0.81 seconds
Started Jul 24 05:16:46 PM PDT 24
Finished Jul 24 05:16:47 PM PDT 24
Peak memory 196340 kb
Host smart-fb5cf890-241d-494f-a552-672d293999f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253650697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3253650697
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2084168125
Short name T211
Test name
Test status
Simulation time 127891692 ps
CPU time 1.02 seconds
Started Jul 24 05:16:34 PM PDT 24
Finished Jul 24 05:16:35 PM PDT 24
Peak memory 196520 kb
Host smart-881038ba-5f95-4ee4-be2c-b02a0394ba2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084168125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2084168125
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4068766223
Short name T172
Test name
Test status
Simulation time 49514510 ps
CPU time 1.93 seconds
Started Jul 24 05:16:54 PM PDT 24
Finished Jul 24 05:16:56 PM PDT 24
Peak memory 198472 kb
Host smart-8415ce3b-6876-4405-bf09-3962544154e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068766223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4068766223
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2203597656
Short name T386
Test name
Test status
Simulation time 152463827 ps
CPU time 0.97 seconds
Started Jul 24 05:16:50 PM PDT 24
Finished Jul 24 05:16:52 PM PDT 24
Peak memory 195976 kb
Host smart-e77bcaec-d667-4122-a0b9-09981f6bb1e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203597656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2203597656
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2581266997
Short name T389
Test name
Test status
Simulation time 43120181 ps
CPU time 0.98 seconds
Started Jul 24 05:16:35 PM PDT 24
Finished Jul 24 05:16:37 PM PDT 24
Peak memory 197240 kb
Host smart-fe60f5ea-e549-4c7a-90cf-d788b37ac1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581266997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2581266997
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2252019904
Short name T634
Test name
Test status
Simulation time 138187246 ps
CPU time 0.78 seconds
Started Jul 24 05:16:36 PM PDT 24
Finished Jul 24 05:16:37 PM PDT 24
Peak memory 195828 kb
Host smart-cef391a8-c221-4a5c-8997-5dc1af8c12ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252019904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2252019904
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2889475225
Short name T58
Test name
Test status
Simulation time 475166033 ps
CPU time 5.56 seconds
Started Jul 24 05:16:49 PM PDT 24
Finished Jul 24 05:16:55 PM PDT 24
Peak memory 198388 kb
Host smart-5a3fb789-28d0-45a8-bc99-5efdb262526a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889475225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2889475225
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4189296548
Short name T268
Test name
Test status
Simulation time 46971760 ps
CPU time 1 seconds
Started Jul 24 05:16:53 PM PDT 24
Finished Jul 24 05:16:54 PM PDT 24
Peak memory 197792 kb
Host smart-c69c08a7-6f37-49d8-b0ca-8ac378bf0d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189296548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4189296548
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1444338228
Short name T577
Test name
Test status
Simulation time 58532751 ps
CPU time 1.1 seconds
Started Jul 24 05:16:37 PM PDT 24
Finished Jul 24 05:16:39 PM PDT 24
Peak memory 196816 kb
Host smart-ded396b7-ec0c-4531-858f-3bc8fdb4ad57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444338228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1444338228
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3349384837
Short name T659
Test name
Test status
Simulation time 18077900466 ps
CPU time 190.46 seconds
Started Jul 24 05:16:46 PM PDT 24
Finished Jul 24 05:19:56 PM PDT 24
Peak memory 198624 kb
Host smart-1e7f68bf-3d32-4e7b-9d46-a92870825566
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349384837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3349384837
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.1210471904
Short name T50
Test name
Test status
Simulation time 160974513973 ps
CPU time 673.85 seconds
Started Jul 24 05:16:41 PM PDT 24
Finished Jul 24 05:27:55 PM PDT 24
Peak memory 198732 kb
Host smart-06a6427b-46ef-48a7-9d42-7f4f662feb6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1210471904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.1210471904
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3508480013
Short name T942
Test name
Test status
Simulation time 29305205 ps
CPU time 0.96 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 198088 kb
Host smart-1b18ba91-59fa-4f2b-86e2-b24de0e16a97
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3508480013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3508480013
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3234616509
Short name T874
Test name
Test status
Simulation time 160549445 ps
CPU time 1.31 seconds
Started Jul 24 05:14:25 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 191800 kb
Host smart-66c444cd-3327-46be-ac07-2467af6235f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234616509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3234616509
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2103834478
Short name T877
Test name
Test status
Simulation time 209238470 ps
CPU time 1.19 seconds
Started Jul 24 05:14:17 PM PDT 24
Finished Jul 24 05:14:18 PM PDT 24
Peak memory 191856 kb
Host smart-25550f4a-e4cc-4077-85dd-8d6f69baa728
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2103834478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2103834478
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3103398995
Short name T897
Test name
Test status
Simulation time 95021513 ps
CPU time 0.94 seconds
Started Jul 24 05:14:09 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 197196 kb
Host smart-293b78e8-d78b-498d-9622-8cc70814496e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103398995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3103398995
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3405800669
Short name T910
Test name
Test status
Simulation time 275995373 ps
CPU time 1.35 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:12 PM PDT 24
Peak memory 198144 kb
Host smart-af174b9b-8696-4e85-990d-947b10acdfe0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3405800669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3405800669
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1756182149
Short name T945
Test name
Test status
Simulation time 42901902 ps
CPU time 0.84 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 196356 kb
Host smart-f8a60459-75bc-462a-99b7-df5c86cc532c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756182149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1756182149
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3763248589
Short name T912
Test name
Test status
Simulation time 61676566 ps
CPU time 1 seconds
Started Jul 24 05:14:07 PM PDT 24
Finished Jul 24 05:14:08 PM PDT 24
Peak memory 196504 kb
Host smart-7edea2a2-7d6f-4d7f-912a-25a9f6189c15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3763248589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3763248589
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2837377365
Short name T865
Test name
Test status
Simulation time 171495452 ps
CPU time 1.17 seconds
Started Jul 24 05:14:14 PM PDT 24
Finished Jul 24 05:14:15 PM PDT 24
Peak memory 191700 kb
Host smart-2c3eb3ea-2d37-4b5c-8357-c82b247c356a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837377365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2837377365
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1235915717
Short name T867
Test name
Test status
Simulation time 65220620 ps
CPU time 0.92 seconds
Started Jul 24 05:14:09 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 191660 kb
Host smart-1a1e3f3a-4644-4c21-8f4c-9dae55d1ad0e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1235915717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1235915717
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3399911272
Short name T852
Test name
Test status
Simulation time 58904887 ps
CPU time 1.22 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:12 PM PDT 24
Peak memory 191976 kb
Host smart-34ba63dd-8068-4a2f-b141-09b1e4399596
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399911272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3399911272
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3853721855
Short name T948
Test name
Test status
Simulation time 181160352 ps
CPU time 1.29 seconds
Started Jul 24 05:14:12 PM PDT 24
Finished Jul 24 05:14:13 PM PDT 24
Peak memory 198156 kb
Host smart-a3afd83e-2b3f-4b79-8c72-0f01ad3f9370
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3853721855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3853721855
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3822221104
Short name T883
Test name
Test status
Simulation time 100789901 ps
CPU time 1.15 seconds
Started Jul 24 05:14:05 PM PDT 24
Finished Jul 24 05:14:06 PM PDT 24
Peak memory 191772 kb
Host smart-240bf3cc-b77f-47b5-aaf5-92724f1671ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822221104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3822221104
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.645133897
Short name T921
Test name
Test status
Simulation time 100153516 ps
CPU time 1.54 seconds
Started Jul 24 05:14:37 PM PDT 24
Finished Jul 24 05:14:38 PM PDT 24
Peak memory 191668 kb
Host smart-63590397-f8a5-4ee5-a476-ebe47ad99ab1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=645133897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.645133897
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1025243434
Short name T869
Test name
Test status
Simulation time 323441774 ps
CPU time 1.27 seconds
Started Jul 24 05:14:13 PM PDT 24
Finished Jul 24 05:14:14 PM PDT 24
Peak memory 191796 kb
Host smart-3e631b45-f3ec-4ed6-9a95-f3c15bf3d151
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025243434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1025243434
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2595940565
Short name T936
Test name
Test status
Simulation time 72224629 ps
CPU time 1.41 seconds
Started Jul 24 05:14:33 PM PDT 24
Finished Jul 24 05:14:35 PM PDT 24
Peak memory 191756 kb
Host smart-57fabbf8-02f4-420a-afdf-e8458fa1b248
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2595940565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2595940565
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1331306954
Short name T909
Test name
Test status
Simulation time 42331827 ps
CPU time 1.04 seconds
Started Jul 24 05:14:06 PM PDT 24
Finished Jul 24 05:14:07 PM PDT 24
Peak memory 191788 kb
Host smart-d30a1eb1-a189-420d-8568-53b86630d1e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331306954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1331306954
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3079926265
Short name T866
Test name
Test status
Simulation time 433974759 ps
CPU time 1.05 seconds
Started Jul 24 05:14:18 PM PDT 24
Finished Jul 24 05:14:19 PM PDT 24
Peak memory 191852 kb
Host smart-169b3525-a336-482f-b01f-309dd3d7a9ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3079926265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3079926265
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3524135800
Short name T860
Test name
Test status
Simulation time 195444569 ps
CPU time 1.07 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:09 PM PDT 24
Peak memory 191812 kb
Host smart-1cbae726-894a-413b-b5f7-877712c1e7cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524135800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3524135800
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.961956235
Short name T929
Test name
Test status
Simulation time 121846916 ps
CPU time 0.79 seconds
Started Jul 24 05:14:04 PM PDT 24
Finished Jul 24 05:14:05 PM PDT 24
Peak memory 191520 kb
Host smart-5c2d63c7-058a-4cf7-a685-8a862d097fce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=961956235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.961956235
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.252795733
Short name T926
Test name
Test status
Simulation time 260633241 ps
CPU time 0.85 seconds
Started Jul 24 05:14:26 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 191596 kb
Host smart-81ea1372-5b47-44b7-a753-7638fb0e32eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252795733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.252795733
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.845436735
Short name T862
Test name
Test status
Simulation time 38876646 ps
CPU time 0.85 seconds
Started Jul 24 05:14:18 PM PDT 24
Finished Jul 24 05:14:19 PM PDT 24
Peak memory 191612 kb
Host smart-840b01f5-4b72-448b-8504-99fee60c58d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=845436735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.845436735
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.476702091
Short name T870
Test name
Test status
Simulation time 47522027 ps
CPU time 1.01 seconds
Started Jul 24 05:14:28 PM PDT 24
Finished Jul 24 05:14:30 PM PDT 24
Peak memory 191584 kb
Host smart-5000ef5d-f505-4b61-a66c-cdc64ad86ca0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476702091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.476702091
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1296986061
Short name T876
Test name
Test status
Simulation time 40090885 ps
CPU time 0.83 seconds
Started Jul 24 05:14:14 PM PDT 24
Finished Jul 24 05:14:15 PM PDT 24
Peak memory 191604 kb
Host smart-4b48fc59-c5e1-40c1-b4e0-255d473c491f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1296986061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1296986061
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2623084856
Short name T880
Test name
Test status
Simulation time 22781918 ps
CPU time 0.82 seconds
Started Jul 24 05:14:20 PM PDT 24
Finished Jul 24 05:14:21 PM PDT 24
Peak memory 191592 kb
Host smart-32c3dde4-a3ae-49a6-85c6-d02a1d4522d8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623084856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2623084856
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.346969606
Short name T902
Test name
Test status
Simulation time 291064152 ps
CPU time 1.14 seconds
Started Jul 24 05:14:09 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 198096 kb
Host smart-a3b994f7-d88b-45fc-9e3a-e65651a0c967
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=346969606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.346969606
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2204771337
Short name T934
Test name
Test status
Simulation time 56561658 ps
CPU time 0.99 seconds
Started Jul 24 05:14:15 PM PDT 24
Finished Jul 24 05:14:16 PM PDT 24
Peak memory 191752 kb
Host smart-04e7b7e3-f68d-44f1-a7ae-020b6229bc51
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204771337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2204771337
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4292883072
Short name T861
Test name
Test status
Simulation time 102409104 ps
CPU time 0.89 seconds
Started Jul 24 05:14:25 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 197340 kb
Host smart-9423dd69-9f97-4dd9-aaa6-f157d6ea3242
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4292883072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.4292883072
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1714751198
Short name T908
Test name
Test status
Simulation time 128205596 ps
CPU time 1.08 seconds
Started Jul 24 05:14:47 PM PDT 24
Finished Jul 24 05:14:48 PM PDT 24
Peak memory 191748 kb
Host smart-bfc2ded5-ce2a-4af3-801c-0f13b74c21a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714751198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1714751198
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.749200787
Short name T892
Test name
Test status
Simulation time 149548429 ps
CPU time 1.06 seconds
Started Jul 24 05:14:25 PM PDT 24
Finished Jul 24 05:14:26 PM PDT 24
Peak memory 191812 kb
Host smart-4fda28aa-958b-4115-a81e-d076df63dad1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=749200787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.749200787
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.240624259
Short name T859
Test name
Test status
Simulation time 56779626 ps
CPU time 1.1 seconds
Started Jul 24 05:14:22 PM PDT 24
Finished Jul 24 05:14:23 PM PDT 24
Peak memory 191684 kb
Host smart-129656c4-2254-47fa-8840-4b3dae4d8adc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240624259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.240624259
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3984395142
Short name T899
Test name
Test status
Simulation time 19803042 ps
CPU time 0.69 seconds
Started Jul 24 05:14:17 PM PDT 24
Finished Jul 24 05:14:17 PM PDT 24
Peak memory 191436 kb
Host smart-a7df8bc0-4581-4f01-a716-3bc278797185
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3984395142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3984395142
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2998500140
Short name T891
Test name
Test status
Simulation time 40378474 ps
CPU time 1.17 seconds
Started Jul 24 05:14:33 PM PDT 24
Finished Jul 24 05:14:34 PM PDT 24
Peak memory 191716 kb
Host smart-32d14d36-1c68-4e0e-8a8f-48685eacb715
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998500140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2998500140
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3566982734
Short name T947
Test name
Test status
Simulation time 105488056 ps
CPU time 1.08 seconds
Started Jul 24 05:14:36 PM PDT 24
Finished Jul 24 05:14:37 PM PDT 24
Peak memory 197216 kb
Host smart-9d3de29a-6e77-45f1-9367-497966e74ed9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3566982734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3566982734
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2681472181
Short name T937
Test name
Test status
Simulation time 79708452 ps
CPU time 1.2 seconds
Started Jul 24 05:14:17 PM PDT 24
Finished Jul 24 05:14:18 PM PDT 24
Peak memory 198096 kb
Host smart-daecf5ee-00cf-4e2d-905a-05b6f803f795
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681472181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2681472181
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2245696134
Short name T949
Test name
Test status
Simulation time 60037618 ps
CPU time 1.05 seconds
Started Jul 24 05:14:10 PM PDT 24
Finished Jul 24 05:14:11 PM PDT 24
Peak memory 191836 kb
Host smart-369902ef-6415-4178-999c-d04b3bfef180
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2245696134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2245696134
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1113399987
Short name T850
Test name
Test status
Simulation time 239842381 ps
CPU time 1.12 seconds
Started Jul 24 05:14:40 PM PDT 24
Finished Jul 24 05:14:41 PM PDT 24
Peak memory 191684 kb
Host smart-3d670b56-9a54-4238-aef3-c57715e22ed5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113399987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1113399987
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.993412880
Short name T915
Test name
Test status
Simulation time 91737036 ps
CPU time 0.95 seconds
Started Jul 24 05:14:13 PM PDT 24
Finished Jul 24 05:14:14 PM PDT 24
Peak memory 191676 kb
Host smart-632c5616-9ab0-4b66-936d-6a8fa5f5b0c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=993412880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.993412880
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3563740218
Short name T900
Test name
Test status
Simulation time 81400561 ps
CPU time 1.43 seconds
Started Jul 24 05:14:34 PM PDT 24
Finished Jul 24 05:14:35 PM PDT 24
Peak memory 191848 kb
Host smart-53544d01-b9ac-4102-8f57-014f1f068acc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563740218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3563740218
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3683421112
Short name T884
Test name
Test status
Simulation time 189073907 ps
CPU time 1.13 seconds
Started Jul 24 05:14:38 PM PDT 24
Finished Jul 24 05:14:40 PM PDT 24
Peak memory 197284 kb
Host smart-7095b50e-afaf-4c90-8e7b-b203819426d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3683421112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3683421112
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3323262919
Short name T855
Test name
Test status
Simulation time 445207265 ps
CPU time 1.22 seconds
Started Jul 24 05:14:22 PM PDT 24
Finished Jul 24 05:14:23 PM PDT 24
Peak memory 191692 kb
Host smart-31407089-3ba3-43f2-b65d-68e899c74131
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323262919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3323262919
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3285731786
Short name T851
Test name
Test status
Simulation time 35649418 ps
CPU time 0.99 seconds
Started Jul 24 05:14:26 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 197640 kb
Host smart-82ecda1e-f856-4f8e-a41b-d77bd57ce1b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3285731786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3285731786
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3893466113
Short name T856
Test name
Test status
Simulation time 302197484 ps
CPU time 1.24 seconds
Started Jul 24 05:14:32 PM PDT 24
Finished Jul 24 05:14:34 PM PDT 24
Peak memory 191756 kb
Host smart-95d1acb6-cc3c-4633-8ecd-2b9e5ee063fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893466113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3893466113
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2917948513
Short name T938
Test name
Test status
Simulation time 71893726 ps
CPU time 1.28 seconds
Started Jul 24 05:14:21 PM PDT 24
Finished Jul 24 05:14:22 PM PDT 24
Peak memory 198376 kb
Host smart-b7cc65ef-8148-4602-872e-51c7cc2c6954
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2917948513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2917948513
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.415593507
Short name T919
Test name
Test status
Simulation time 369955842 ps
CPU time 0.85 seconds
Started Jul 24 05:14:16 PM PDT 24
Finished Jul 24 05:14:17 PM PDT 24
Peak memory 191612 kb
Host smart-7a64aa1e-2dbe-4a5e-9440-869ae0180a54
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415593507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.415593507
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2714495392
Short name T916
Test name
Test status
Simulation time 47456123 ps
CPU time 1.01 seconds
Started Jul 24 05:14:11 PM PDT 24
Finished Jul 24 05:14:12 PM PDT 24
Peak memory 191792 kb
Host smart-a6b46c57-d48c-4d01-bf2a-c2262cfa0393
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2714495392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2714495392
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1786367155
Short name T946
Test name
Test status
Simulation time 90021707 ps
CPU time 0.9 seconds
Started Jul 24 05:14:15 PM PDT 24
Finished Jul 24 05:14:16 PM PDT 24
Peak memory 191568 kb
Host smart-1fd4387b-8b8b-4caa-87af-205f3aa96f7b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786367155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1786367155
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.60476917
Short name T924
Test name
Test status
Simulation time 51468755 ps
CPU time 0.96 seconds
Started Jul 24 05:14:16 PM PDT 24
Finished Jul 24 05:14:17 PM PDT 24
Peak memory 191776 kb
Host smart-27dac15e-4226-41de-9344-571c1d0ca6ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=60476917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.60476917
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1293180189
Short name T907
Test name
Test status
Simulation time 164954508 ps
CPU time 0.92 seconds
Started Jul 24 05:14:30 PM PDT 24
Finished Jul 24 05:14:31 PM PDT 24
Peak memory 197940 kb
Host smart-9fd2cb1f-4612-4cfb-b481-9ad9313f5c83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293180189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1293180189
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1910592984
Short name T927
Test name
Test status
Simulation time 165385184 ps
CPU time 1.39 seconds
Started Jul 24 05:14:36 PM PDT 24
Finished Jul 24 05:14:38 PM PDT 24
Peak memory 198184 kb
Host smart-57c612fd-5e71-4f9f-a732-f9ba95ff7d70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1910592984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1910592984
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.507698392
Short name T871
Test name
Test status
Simulation time 109207179 ps
CPU time 1.15 seconds
Started Jul 24 05:14:30 PM PDT 24
Finished Jul 24 05:14:31 PM PDT 24
Peak memory 191828 kb
Host smart-daf13442-93d6-45af-bf25-63a5a728dad4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507698392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.507698392
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2608400111
Short name T864
Test name
Test status
Simulation time 233513608 ps
CPU time 1.04 seconds
Started Jul 24 05:14:41 PM PDT 24
Finished Jul 24 05:14:43 PM PDT 24
Peak memory 191744 kb
Host smart-8f9d007b-71b4-4aaf-be63-a41329f31a28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2608400111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2608400111
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1704139065
Short name T933
Test name
Test status
Simulation time 366067693 ps
CPU time 1.32 seconds
Started Jul 24 05:14:15 PM PDT 24
Finished Jul 24 05:14:17 PM PDT 24
Peak memory 191832 kb
Host smart-cdf3a445-dced-4251-9ab7-290707d9cc1e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704139065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1704139065
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4201851813
Short name T893
Test name
Test status
Simulation time 52724141 ps
CPU time 0.9 seconds
Started Jul 24 05:14:32 PM PDT 24
Finished Jul 24 05:14:33 PM PDT 24
Peak memory 196188 kb
Host smart-c2fc5e4d-6ca9-4948-bcf8-c09e015c45b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4201851813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4201851813
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1754332471
Short name T935
Test name
Test status
Simulation time 41423450 ps
CPU time 1.12 seconds
Started Jul 24 05:14:36 PM PDT 24
Finished Jul 24 05:14:37 PM PDT 24
Peak memory 191800 kb
Host smart-81dac7ee-7939-4e2f-9b24-bbd70533968d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754332471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1754332471
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3401228127
Short name T930
Test name
Test status
Simulation time 92036912 ps
CPU time 1.13 seconds
Started Jul 24 05:14:25 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 191804 kb
Host smart-95de0d02-3e4b-4fef-966f-745682adaa3c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3401228127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3401228127
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.767120391
Short name T913
Test name
Test status
Simulation time 24283182 ps
CPU time 0.82 seconds
Started Jul 24 05:14:30 PM PDT 24
Finished Jul 24 05:14:31 PM PDT 24
Peak memory 191528 kb
Host smart-3813ac2c-29a0-4940-bdef-f6a676e3a029
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767120391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.767120391
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.12106246
Short name T881
Test name
Test status
Simulation time 37950987 ps
CPU time 0.87 seconds
Started Jul 24 05:14:26 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 196344 kb
Host smart-881ae30d-5a1e-4581-93c7-213f6f26207f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=12106246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.12106246
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3152039372
Short name T898
Test name
Test status
Simulation time 194487473 ps
CPU time 0.97 seconds
Started Jul 24 05:14:19 PM PDT 24
Finished Jul 24 05:14:20 PM PDT 24
Peak memory 191628 kb
Host smart-934a20b2-f105-476e-ae90-f38c1ff9884a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152039372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3152039372
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1106033468
Short name T941
Test name
Test status
Simulation time 134644906 ps
CPU time 1.16 seconds
Started Jul 24 05:14:36 PM PDT 24
Finished Jul 24 05:14:37 PM PDT 24
Peak memory 191716 kb
Host smart-a9fb372a-9b60-477a-a21b-048b51ee2dcf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1106033468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1106033468
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3172019215
Short name T890
Test name
Test status
Simulation time 57811831 ps
CPU time 0.87 seconds
Started Jul 24 05:14:27 PM PDT 24
Finished Jul 24 05:14:28 PM PDT 24
Peak memory 191580 kb
Host smart-10423b40-4c32-4ea8-b233-e967a7bd95dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172019215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3172019215
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1777170967
Short name T878
Test name
Test status
Simulation time 289408925 ps
CPU time 1.11 seconds
Started Jul 24 05:14:17 PM PDT 24
Finished Jul 24 05:14:18 PM PDT 24
Peak memory 191816 kb
Host smart-a9fe9d22-78bc-43e8-8bfb-30cf0c4dea2a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1777170967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1777170967
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3790825719
Short name T863
Test name
Test status
Simulation time 643154406 ps
CPU time 1.31 seconds
Started Jul 24 05:14:25 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 198024 kb
Host smart-36766dfa-1b3d-41e5-9459-e52ea2731639
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790825719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3790825719
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1848316109
Short name T917
Test name
Test status
Simulation time 134619909 ps
CPU time 0.88 seconds
Started Jul 24 05:14:24 PM PDT 24
Finished Jul 24 05:14:25 PM PDT 24
Peak memory 197460 kb
Host smart-2c859e27-ade0-4886-9507-b4c42876201f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1848316109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1848316109
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3370906656
Short name T944
Test name
Test status
Simulation time 50029853 ps
CPU time 1.3 seconds
Started Jul 24 05:14:31 PM PDT 24
Finished Jul 24 05:14:32 PM PDT 24
Peak memory 191752 kb
Host smart-5f70b3e7-ad0a-4631-87d9-a91861832e30
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370906656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3370906656
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1859820018
Short name T894
Test name
Test status
Simulation time 563418732 ps
CPU time 1.07 seconds
Started Jul 24 05:14:38 PM PDT 24
Finished Jul 24 05:14:40 PM PDT 24
Peak memory 191780 kb
Host smart-19cb8e9e-41d2-4be9-a070-c1580429c5b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1859820018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1859820018
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3114755730
Short name T895
Test name
Test status
Simulation time 83432967 ps
CPU time 1.54 seconds
Started Jul 24 05:14:43 PM PDT 24
Finished Jul 24 05:14:45 PM PDT 24
Peak memory 191796 kb
Host smart-ce8b8025-6590-45b9-a775-4ced7310e204
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114755730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3114755730
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1004880765
Short name T922
Test name
Test status
Simulation time 45555545 ps
CPU time 0.9 seconds
Started Jul 24 05:14:26 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 191596 kb
Host smart-fe6638f6-cedb-4ab5-a638-d4fa43890617
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1004880765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1004880765
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2447759882
Short name T939
Test name
Test status
Simulation time 794323217 ps
CPU time 1.06 seconds
Started Jul 24 05:14:21 PM PDT 24
Finished Jul 24 05:14:22 PM PDT 24
Peak memory 191768 kb
Host smart-d6bf4301-5448-4fd9-afaa-6f47b1401ff9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447759882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2447759882
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4172292966
Short name T879
Test name
Test status
Simulation time 175562648 ps
CPU time 1.48 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 198176 kb
Host smart-4ffa2ffe-04fd-4886-b9eb-f600f8023f2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4172292966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4172292966
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2967735794
Short name T903
Test name
Test status
Simulation time 197876280 ps
CPU time 1 seconds
Started Jul 24 05:14:12 PM PDT 24
Finished Jul 24 05:14:13 PM PDT 24
Peak memory 191736 kb
Host smart-ddcda75d-d78d-4f63-a5a5-b6a07549f7f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967735794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2967735794
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2868205907
Short name T896
Test name
Test status
Simulation time 54831850 ps
CPU time 1.06 seconds
Started Jul 24 05:14:38 PM PDT 24
Finished Jul 24 05:14:39 PM PDT 24
Peak memory 198120 kb
Host smart-0d9ce226-6662-48ed-98f7-7ebc6938a51c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2868205907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2868205907
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3046430996
Short name T888
Test name
Test status
Simulation time 45496203 ps
CPU time 1.21 seconds
Started Jul 24 05:14:24 PM PDT 24
Finished Jul 24 05:14:26 PM PDT 24
Peak memory 198132 kb
Host smart-155c3871-0e46-48c6-b20f-585eb07199b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046430996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3046430996
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.834487534
Short name T904
Test name
Test status
Simulation time 63953763 ps
CPU time 1.15 seconds
Started Jul 24 05:14:32 PM PDT 24
Finished Jul 24 05:14:34 PM PDT 24
Peak memory 191660 kb
Host smart-11e66b19-0bdb-47a4-bfda-551c448ba182
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=834487534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.834487534
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1890961992
Short name T885
Test name
Test status
Simulation time 144601654 ps
CPU time 0.91 seconds
Started Jul 24 05:14:50 PM PDT 24
Finished Jul 24 05:14:51 PM PDT 24
Peak memory 191620 kb
Host smart-22343d22-4fc5-48eb-9bc1-d0e01d2afdf8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890961992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1890961992
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1709390243
Short name T886
Test name
Test status
Simulation time 301296002 ps
CPU time 0.99 seconds
Started Jul 24 05:14:48 PM PDT 24
Finished Jul 24 05:14:49 PM PDT 24
Peak memory 197300 kb
Host smart-ba568795-d49a-4c7a-92bf-103a3532ded8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1709390243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1709390243
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249730103
Short name T928
Test name
Test status
Simulation time 413553293 ps
CPU time 1.39 seconds
Started Jul 24 05:14:47 PM PDT 24
Finished Jul 24 05:14:49 PM PDT 24
Peak memory 191788 kb
Host smart-ff9f307d-dbe0-4fff-91a5-042856b15e29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249730103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.249730103
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2375343751
Short name T905
Test name
Test status
Simulation time 808688057 ps
CPU time 1.04 seconds
Started Jul 24 05:14:44 PM PDT 24
Finished Jul 24 05:14:45 PM PDT 24
Peak memory 191716 kb
Host smart-c7d70350-498e-4d3c-ae17-164d39497028
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2375343751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2375343751
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4085847702
Short name T858
Test name
Test status
Simulation time 29163217 ps
CPU time 0.98 seconds
Started Jul 24 05:14:38 PM PDT 24
Finished Jul 24 05:14:39 PM PDT 24
Peak memory 191748 kb
Host smart-41df131f-f886-4216-8ada-353ad6614a68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085847702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4085847702
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2897169166
Short name T873
Test name
Test status
Simulation time 419403201 ps
CPU time 1.08 seconds
Started Jul 24 05:14:26 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 191708 kb
Host smart-0146a6f3-5bff-4b35-8084-e846142c8f30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2897169166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2897169166
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2637468925
Short name T911
Test name
Test status
Simulation time 120028542 ps
CPU time 1.04 seconds
Started Jul 24 05:14:27 PM PDT 24
Finished Jul 24 05:14:28 PM PDT 24
Peak memory 191720 kb
Host smart-e5ca1ed0-4f03-4735-8e45-360ce1322d1f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637468925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2637468925
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1735857674
Short name T868
Test name
Test status
Simulation time 69740666 ps
CPU time 1.14 seconds
Started Jul 24 05:14:27 PM PDT 24
Finished Jul 24 05:14:29 PM PDT 24
Peak memory 191804 kb
Host smart-1589283f-9ede-4228-bb74-7a21dc3882ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1735857674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1735857674
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2664984364
Short name T931
Test name
Test status
Simulation time 130803711 ps
CPU time 1.05 seconds
Started Jul 24 05:14:26 PM PDT 24
Finished Jul 24 05:14:32 PM PDT 24
Peak memory 197440 kb
Host smart-2ab5cab6-a40a-4c89-9045-0c09f406a59b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664984364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2664984364
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3702808128
Short name T943
Test name
Test status
Simulation time 222688460 ps
CPU time 1.05 seconds
Started Jul 24 05:14:28 PM PDT 24
Finished Jul 24 05:14:29 PM PDT 24
Peak memory 191804 kb
Host smart-c7a6638c-6018-4be6-bf05-0d97f0d2dac3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3702808128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3702808128
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2132058865
Short name T882
Test name
Test status
Simulation time 173412009 ps
CPU time 1.14 seconds
Started Jul 24 05:14:23 PM PDT 24
Finished Jul 24 05:14:24 PM PDT 24
Peak memory 191772 kb
Host smart-bb11f4ec-996e-48ad-b4d5-afe1bda9af7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132058865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2132058865
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1013760816
Short name T887
Test name
Test status
Simulation time 201157167 ps
CPU time 1.07 seconds
Started Jul 24 05:14:32 PM PDT 24
Finished Jul 24 05:14:33 PM PDT 24
Peak memory 191792 kb
Host smart-45f07095-ee19-4b23-82c7-9aa8749d6f3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1013760816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1013760816
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1658928389
Short name T875
Test name
Test status
Simulation time 444661664 ps
CPU time 1.07 seconds
Started Jul 24 05:14:30 PM PDT 24
Finished Jul 24 05:14:32 PM PDT 24
Peak memory 191708 kb
Host smart-382fdaab-a0c5-4cb1-a9ad-d1a66127159d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658928389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1658928389
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3810399552
Short name T901
Test name
Test status
Simulation time 113279323 ps
CPU time 1.22 seconds
Started Jul 24 05:14:52 PM PDT 24
Finished Jul 24 05:14:53 PM PDT 24
Peak memory 198160 kb
Host smart-963c7192-bb70-4f29-b3f5-fa42229d4f1f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3810399552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3810399552
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1738602759
Short name T914
Test name
Test status
Simulation time 194270837 ps
CPU time 1.54 seconds
Started Jul 24 05:14:21 PM PDT 24
Finished Jul 24 05:14:23 PM PDT 24
Peak memory 191752 kb
Host smart-bb377137-2403-4b4f-b040-f2c714c0e48f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738602759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1738602759
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1049548728
Short name T918
Test name
Test status
Simulation time 126718936 ps
CPU time 0.79 seconds
Started Jul 24 05:14:21 PM PDT 24
Finished Jul 24 05:14:21 PM PDT 24
Peak memory 191464 kb
Host smart-2e06dbb0-aa0f-4767-9174-d884945e6c8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1049548728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1049548728
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.383390322
Short name T940
Test name
Test status
Simulation time 75317228 ps
CPU time 0.87 seconds
Started Jul 24 05:14:33 PM PDT 24
Finished Jul 24 05:14:34 PM PDT 24
Peak memory 191612 kb
Host smart-20f345ff-aad9-4c64-a7dc-e479a68bedf4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383390322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.383390322
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3462062004
Short name T923
Test name
Test status
Simulation time 138938965 ps
CPU time 1.15 seconds
Started Jul 24 05:14:08 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 191804 kb
Host smart-1edaa5dc-2662-4b68-aa34-eec0c6ad5e89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3462062004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3462062004
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3858089539
Short name T872
Test name
Test status
Simulation time 708231864 ps
CPU time 1.16 seconds
Started Jul 24 05:14:18 PM PDT 24
Finished Jul 24 05:14:19 PM PDT 24
Peak memory 198036 kb
Host smart-04088592-e232-496e-8a3e-94e3d99e1afb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858089539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3858089539
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2943277078
Short name T854
Test name
Test status
Simulation time 80522120 ps
CPU time 0.79 seconds
Started Jul 24 05:14:14 PM PDT 24
Finished Jul 24 05:14:14 PM PDT 24
Peak memory 191572 kb
Host smart-aa352320-e7ca-4c14-b64a-021ce23e763d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2943277078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2943277078
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3586045160
Short name T889
Test name
Test status
Simulation time 61338287 ps
CPU time 1.02 seconds
Started Jul 24 05:14:12 PM PDT 24
Finished Jul 24 05:14:13 PM PDT 24
Peak memory 191748 kb
Host smart-11b40bfe-b0c1-4d6d-a3b7-00dfb597618d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586045160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3586045160
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1590103692
Short name T853
Test name
Test status
Simulation time 216182745 ps
CPU time 1.35 seconds
Started Jul 24 05:14:21 PM PDT 24
Finished Jul 24 05:14:22 PM PDT 24
Peak memory 191768 kb
Host smart-2f921bda-028a-4740-b951-99972d8af99e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1590103692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1590103692
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1611788729
Short name T932
Test name
Test status
Simulation time 108733849 ps
CPU time 0.83 seconds
Started Jul 24 05:14:09 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 197460 kb
Host smart-c3d48419-ddd5-4442-928c-44b594291532
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611788729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1611788729
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1267711236
Short name T925
Test name
Test status
Simulation time 51309256 ps
CPU time 0.93 seconds
Started Jul 24 05:14:25 PM PDT 24
Finished Jul 24 05:14:27 PM PDT 24
Peak memory 191652 kb
Host smart-2dda952e-012c-4dec-805b-b927ca2342d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1267711236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1267711236
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.106778353
Short name T920
Test name
Test status
Simulation time 61292086 ps
CPU time 0.98 seconds
Started Jul 24 05:14:27 PM PDT 24
Finished Jul 24 05:14:28 PM PDT 24
Peak memory 197164 kb
Host smart-d4a58361-f3a8-4011-ac3b-fbba6cc55de1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106778353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.106778353
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3765428140
Short name T906
Test name
Test status
Simulation time 247799156 ps
CPU time 1.3 seconds
Started Jul 24 05:14:15 PM PDT 24
Finished Jul 24 05:14:17 PM PDT 24
Peak memory 196600 kb
Host smart-747dbd2b-573f-477a-852a-991fcb5e866c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3765428140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3765428140
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2105219028
Short name T857
Test name
Test status
Simulation time 230994520 ps
CPU time 1.14 seconds
Started Jul 24 05:14:09 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 191732 kb
Host smart-a800a39e-6e44-42ac-9a86-e821fde34505
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105219028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2105219028
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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