Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4255203	1			T30	1		T31	1		T32	113
all_pins[1]	4255203	1			T30	1		T31	1		T32	113
all_pins[2]	4255203	1			T30	1		T31	1		T32	113
all_pins[3]	4255203	1			T30	1		T31	1		T32	113
all_pins[4]	4255203	1			T30	1		T31	1		T32	113
all_pins[5]	4255203	1			T30	1		T31	1		T32	113
all_pins[6]	4255203	1			T30	1		T31	1		T32	113
all_pins[7]	4255203	1			T30	1		T31	1		T32	113
all_pins[8]	4255203	1			T30	1		T31	1		T32	113
all_pins[9]	4255203	1			T30	1		T31	1		T32	113
all_pins[10]	4255203	1			T30	1		T31	1		T32	113
all_pins[11]	4255203	1			T30	1		T31	1		T32	113
all_pins[12]	4255203	1			T30	1		T31	1		T32	113
all_pins[13]	4255203	1			T30	1		T31	1		T32	113
all_pins[14]	4255203	1			T30	1		T31	1		T32	113
all_pins[15]	4255203	1			T30	1		T31	1		T32	113
all_pins[16]	4255203	1			T30	1		T31	1		T32	113
all_pins[17]	4255203	1			T30	1		T31	1		T32	113
all_pins[18]	4255203	1			T30	1		T31	1		T32	113
all_pins[19]	4255203	1			T30	1		T31	1		T32	113
all_pins[20]	4255203	1			T30	1		T31	1		T32	113
all_pins[21]	4255203	1			T30	1		T31	1		T32	113
all_pins[22]	4255203	1			T30	1		T31	1		T32	113
all_pins[23]	4255203	1			T30	1		T31	1		T32	113
all_pins[24]	4255203	1			T30	1		T31	1		T32	113
all_pins[25]	4255203	1			T30	1		T31	1		T32	113
all_pins[26]	4255203	1			T30	1		T31	1		T32	113
all_pins[27]	4255203	1			T30	1		T31	1		T32	113
all_pins[28]	4255203	1			T30	1		T31	1		T32	113
all_pins[29]	4255203	1			T30	1		T31	1		T32	113
all_pins[30]	4255203	1			T30	1		T31	1		T32	113
all_pins[31]	4255203	1			T30	1		T31	1		T32	113

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	84584960	1			T30	32		T31	32		T32	1894
values[0x1]	51581536	1			T32	1722		T33	1064		T34	5788
transitions[0x0=>0x1]	30915019	1			T32	922		T33	533		T34	3447
transitions[0x1=>0x0]	30914876	1			T32	922		T33	533		T34	3446

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2643366	1			T30	1		T31	1		T32	60
all_pins[0]	values[0x1]	1611837	1			T32	53		T33	27		T34	150
all_pins[0]	transitions[0x0=>0x1]	996570	1			T32	27		T33	12		T34	98
all_pins[0]	transitions[0x1=>0x0]	1000271	1			T32	27		T33	17		T34	158
all_pins[1]	values[0x0]	2644615	1			T30	1		T31	1		T32	65
all_pins[1]	values[0x1]	1610588	1			T32	48		T33	34		T34	239
all_pins[1]	transitions[0x0=>0x1]	964613	1			T32	29		T33	24		T34	147
all_pins[1]	transitions[0x1=>0x0]	965862	1			T32	34		T33	17		T34	58
all_pins[2]	values[0x0]	2642838	1			T30	1		T31	1		T32	64
all_pins[2]	values[0x1]	1612365	1			T32	49		T33	35		T34	183
all_pins[2]	transitions[0x0=>0x1]	964757	1			T32	24		T33	23		T34	76
all_pins[2]	transitions[0x1=>0x0]	962980	1			T32	23		T33	22		T34	132
all_pins[3]	values[0x0]	2641925	1			T30	1		T31	1		T32	55
all_pins[3]	values[0x1]	1613278	1			T32	58		T33	38		T34	177
all_pins[3]	transitions[0x0=>0x1]	967051	1			T32	30		T33	19		T34	119
all_pins[3]	transitions[0x1=>0x0]	966138	1			T32	21		T33	16		T34	125
all_pins[4]	values[0x0]	2641266	1			T30	1		T31	1		T32	63
all_pins[4]	values[0x1]	1613937	1			T32	50		T33	31		T34	196
all_pins[4]	transitions[0x0=>0x1]	967286	1			T32	24		T33	12		T34	99
all_pins[4]	transitions[0x1=>0x0]	966627	1			T32	32		T33	19		T34	80
all_pins[5]	values[0x0]	2647438	1			T30	1		T31	1		T32	53
all_pins[5]	values[0x1]	1607765	1			T32	60		T33	26		T34	132
all_pins[5]	transitions[0x0=>0x1]	964465	1			T32	34		T33	13		T34	103
all_pins[5]	transitions[0x1=>0x0]	970637	1			T32	24		T33	18		T34	167
all_pins[6]	values[0x0]	2643351	1			T30	1		T31	1		T32	60
all_pins[6]	values[0x1]	1611852	1			T32	53		T33	31		T34	253
all_pins[6]	transitions[0x0=>0x1]	967277	1			T32	24		T33	19		T34	196
all_pins[6]	transitions[0x1=>0x0]	963190	1			T32	31		T33	14		T34	75
all_pins[7]	values[0x0]	2641052	1			T30	1		T31	1		T32	56
all_pins[7]	values[0x1]	1614151	1			T32	57		T33	42		T34	132
all_pins[7]	transitions[0x0=>0x1]	965736	1			T32	27		T33	23		T34	53
all_pins[7]	transitions[0x1=>0x0]	963437	1			T32	23		T33	12		T34	174
all_pins[8]	values[0x0]	2647861	1			T30	1		T31	1		T32	64
all_pins[8]	values[0x1]	1607342	1			T32	49		T33	38		T34	167
all_pins[8]	transitions[0x0=>0x1]	961737	1			T32	27		T33	11		T34	125
all_pins[8]	transitions[0x1=>0x0]	968546	1			T32	35		T33	15		T34	90
all_pins[9]	values[0x0]	2644085	1			T30	1		T31	1		T32	54
all_pins[9]	values[0x1]	1611118	1			T32	59		T33	31		T34	129
all_pins[9]	transitions[0x0=>0x1]	966913	1			T32	38		T33	17		T34	99
all_pins[9]	transitions[0x1=>0x0]	963137	1			T32	28		T33	24		T34	137
all_pins[10]	values[0x0]	2638990	1			T30	1		T31	1		T32	55
all_pins[10]	values[0x1]	1616213	1			T32	58		T33	41		T34	119
all_pins[10]	transitions[0x0=>0x1]	966093	1			T32	29		T33	21		T34	104
all_pins[10]	transitions[0x1=>0x0]	960998	1			T32	30		T33	11		T34	114
all_pins[11]	values[0x0]	2646057	1			T30	1		T31	1		T32	67
all_pins[11]	values[0x1]	1609146	1			T32	46		T33	33		T34	155
all_pins[11]	transitions[0x0=>0x1]	962068	1			T32	23		T33	15		T34	111
all_pins[11]	transitions[0x1=>0x0]	969135	1			T32	35		T33	23		T34	75
all_pins[12]	values[0x0]	2644524	1			T30	1		T31	1		T32	62
all_pins[12]	values[0x1]	1610679	1			T32	51		T33	40		T34	214
all_pins[12]	transitions[0x0=>0x1]	967047	1			T32	34		T33	21		T34	142
all_pins[12]	transitions[0x1=>0x0]	965514	1			T32	29		T33	14		T34	83
all_pins[13]	values[0x0]	2634566	1			T30	1		T31	1		T32	59
all_pins[13]	values[0x1]	1620637	1			T32	54		T33	37		T34	228
all_pins[13]	transitions[0x0=>0x1]	970918	1			T32	31		T33	12		T34	88
all_pins[13]	transitions[0x1=>0x0]	960960	1			T32	28		T33	15		T34	74
all_pins[14]	values[0x0]	2639963	1			T30	1		T31	1		T32	43
all_pins[14]	values[0x1]	1615240	1			T32	70		T33	39		T34	137
all_pins[14]	transitions[0x0=>0x1]	960752	1			T32	35		T33	21		T34	51
all_pins[14]	transitions[0x1=>0x0]	966149	1			T32	19		T33	19		T34	142
all_pins[15]	values[0x0]	2640825	1			T30	1		T31	1		T32	64
all_pins[15]	values[0x1]	1614378	1			T32	49		T33	31		T34	210
all_pins[15]	transitions[0x0=>0x1]	964646	1			T32	21		T33	13		T34	147
all_pins[15]	transitions[0x1=>0x0]	965508	1			T32	42		T33	21		T34	74
all_pins[16]	values[0x0]	2641894	1			T30	1		T31	1		T32	61
all_pins[16]	values[0x1]	1613309	1			T32	52		T33	44		T34	194
all_pins[16]	transitions[0x0=>0x1]	966458	1			T32	23		T33	21		T34	116
all_pins[16]	transitions[0x1=>0x0]	967527	1			T32	20		T33	8		T34	132
all_pins[17]	values[0x0]	2641628	1			T30	1		T31	1		T32	55
all_pins[17]	values[0x1]	1613575	1			T32	58		T33	34		T34	189
all_pins[17]	transitions[0x0=>0x1]	966740	1			T32	38		T33	10		T34	82
all_pins[17]	transitions[0x1=>0x0]	966474	1			T32	32		T33	20		T34	87
all_pins[18]	values[0x0]	2648093	1			T30	1		T31	1		T32	59
all_pins[18]	values[0x1]	1607110	1			T32	54		T33	28		T34	137
all_pins[18]	transitions[0x0=>0x1]	962885	1			T32	25		T33	12		T34	93
all_pins[18]	transitions[0x1=>0x0]	969350	1			T32	29		T33	18		T34	145
all_pins[19]	values[0x0]	2649952	1			T30	1		T31	1		T32	62
all_pins[19]	values[0x1]	1605251	1			T32	51		T33	39		T34	228
all_pins[19]	transitions[0x0=>0x1]	964105	1			T32	30		T33	24		T34	187
all_pins[19]	transitions[0x1=>0x0]	965964	1			T32	33		T33	13		T34	96
all_pins[20]	values[0x0]	2647853	1			T30	1		T31	1		T32	64
all_pins[20]	values[0x1]	1607350	1			T32	49		T33	30		T34	189
all_pins[20]	transitions[0x0=>0x1]	964849	1			T32	29		T33	14		T34	69
all_pins[20]	transitions[0x1=>0x0]	962750	1			T32	31		T33	23		T34	108
all_pins[21]	values[0x0]	2640758	1			T30	1		T31	1		T32	63
all_pins[21]	values[0x1]	1614445	1			T32	50		T33	27		T34	208
all_pins[21]	transitions[0x0=>0x1]	968857	1			T32	29		T33	15		T34	114
all_pins[21]	transitions[0x1=>0x0]	961762	1			T32	28		T33	18		T34	95
all_pins[22]	values[0x0]	2648697	1			T30	1		T31	1		T32	61
all_pins[22]	values[0x1]	1606506	1			T32	52		T33	28		T34	175
all_pins[22]	transitions[0x0=>0x1]	960091	1			T32	28		T33	18		T34	108
all_pins[22]	transitions[0x1=>0x0]	968030	1			T32	26		T33	17		T34	141
all_pins[23]	values[0x0]	2646415	1			T30	1		T31	1		T32	52
all_pins[23]	values[0x1]	1608788	1			T32	61		T33	33		T34	194
all_pins[23]	transitions[0x0=>0x1]	965187	1			T32	36		T33	19		T34	81
all_pins[23]	transitions[0x1=>0x0]	962905	1			T32	27		T33	14		T34	62
all_pins[24]	values[0x0]	2642020	1			T30	1		T31	1		T32	57
all_pins[24]	values[0x1]	1613183	1			T32	56		T33	35		T34	171
all_pins[24]	transitions[0x0=>0x1]	964765	1			T32	23		T33	17		T34	77
all_pins[24]	transitions[0x1=>0x0]	960370	1			T32	28		T33	15		T34	100
all_pins[25]	values[0x0]	2639174	1			T30	1		T31	1		T32	62
all_pins[25]	values[0x1]	1616029	1			T32	51		T33	24		T34	204
all_pins[25]	transitions[0x0=>0x1]	967341	1			T32	21		T33	11		T34	127
all_pins[25]	transitions[0x1=>0x0]	964495	1			T32	26		T33	22		T34	94
all_pins[26]	values[0x0]	2640598	1			T30	1		T31	1		T32	46
all_pins[26]	values[0x1]	1614605	1			T32	67		T33	32		T34	193
all_pins[26]	transitions[0x0=>0x1]	965069	1			T32	38		T33	20		T34	107
all_pins[26]	transitions[0x1=>0x0]	966493	1			T32	22		T33	12		T34	118
all_pins[27]	values[0x0]	2646378	1			T30	1		T31	1		T32	66
all_pins[27]	values[0x1]	1608825	1			T32	47		T33	29		T34	146
all_pins[27]	transitions[0x0=>0x1]	960696	1			T32	23		T33	14		T34	69
all_pins[27]	transitions[0x1=>0x0]	966476	1			T32	43		T33	17		T34	116
all_pins[28]	values[0x0]	2642776	1			T30	1		T31	1		T32	55
all_pins[28]	values[0x1]	1612427	1			T32	58		T33	35		T34	151
all_pins[28]	transitions[0x0=>0x1]	965947	1			T32	37		T33	18		T34	106
all_pins[28]	transitions[0x1=>0x0]	962345	1			T32	26		T33	12		T34	101
all_pins[29]	values[0x0]	2640195	1			T30	1		T31	1		T32	56
all_pins[29]	values[0x1]	1615008	1			T32	57		T33	31		T34	210
all_pins[29]	transitions[0x0=>0x1]	965329	1			T32	33		T33	13		T34	138
all_pins[29]	transitions[0x1=>0x0]	962748	1			T32	34		T33	17		T34	79
all_pins[30]	values[0x0]	2646285	1			T30	1		T31	1		T32	71
all_pins[30]	values[0x1]	1608918	1			T32	42		T33	29		T34	167
all_pins[30]	transitions[0x0=>0x1]	960307	1			T32	19		T33	14		T34	73
all_pins[30]	transitions[0x1=>0x0]	966397	1			T32	34		T33	16		T34	116
all_pins[31]	values[0x0]	2639522	1			T30	1		T31	1		T32	60
all_pins[31]	values[0x1]	1615681	1			T32	53		T33	32		T34	211
all_pins[31]	transitions[0x0=>0x1]	968464	1			T32	33		T33	17		T34	142
all_pins[31]	transitions[0x1=>0x0]	961701	1			T32	22		T33	14		T34	98