Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14211290	1			T30	1		T31	273		T32	55284
all_values[1]	14211290	1			T30	1		T31	273		T32	55284
all_values[2]	14211290	1			T30	1		T31	273		T32	55284
all_values[3]	14211290	1			T30	1		T31	273		T32	55284
all_values[4]	14211290	1			T30	1		T31	273		T32	55284
all_values[5]	14211290	1			T30	1		T31	273		T32	55284
all_values[6]	14211290	1			T30	1		T31	273		T32	55284
all_values[7]	14211290	1			T30	1		T31	273		T32	55284
all_values[8]	14211290	1			T30	1		T31	273		T32	55284
all_values[9]	14211290	1			T30	1		T31	273		T32	55284
all_values[10]	14211290	1			T30	1		T31	273		T32	55284
all_values[11]	14211290	1			T30	1		T31	273		T32	55284
all_values[12]	14211290	1			T30	1		T31	273		T32	55284
all_values[13]	14211290	1			T30	1		T31	273		T32	55284
all_values[14]	14211290	1			T30	1		T31	273		T32	55284
all_values[15]	14211290	1			T30	1		T31	273		T32	55284
all_values[16]	14211290	1			T30	1		T31	273		T32	55284
all_values[17]	14211290	1			T30	1		T31	273		T32	55284
all_values[18]	14211290	1			T30	1		T31	273		T32	55284
all_values[19]	14211290	1			T30	1		T31	273		T32	55284
all_values[20]	14211290	1			T30	1		T31	273		T32	55284
all_values[21]	14211290	1			T30	1		T31	273		T32	55284
all_values[22]	14211290	1			T30	1		T31	273		T32	55284
all_values[23]	14211290	1			T30	1		T31	273		T32	55284
all_values[24]	14211290	1			T30	1		T31	273		T32	55284
all_values[25]	14211290	1			T30	1		T31	273		T32	55284
all_values[26]	14211290	1			T30	1		T31	273		T32	55284
all_values[27]	14211290	1			T30	1		T31	273		T32	55284
all_values[28]	14211290	1			T30	1		T31	273		T32	55284
all_values[29]	14211290	1			T30	1		T31	273		T32	55284
all_values[30]	14211290	1			T30	1		T31	273		T32	55284
all_values[31]	14211290	1			T30	1		T31	273		T32	55284

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262086043

1

T30

32

T31

8736

T32

176908

auto[1]

192675237

1

T34

17935

T35

9501

T37

897213

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106427707

1

T30

32

T31

8736

T32

176908

auto[1]

348333573

1

T34

31992

T35

17237

T37

161674

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

449763137

1

T30

32

T31

8736

T32

176908

auto[1]

4998143

1

T37

225550

T48

90

T20

287

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2742426	1			T30	1		T31	273		T32	55284
all_values[0]	auto[0]	auto[0]	auto[1]	5361547	1			T34	615		T35	278		T37	247408
all_values[0]	auto[0]	auto[1]	auto[0]	586319	1			T34	22		T35	12		T37	29111
all_values[0]	auto[0]	auto[1]	auto[1]	5364650	1			T34	425		T35	271		T37	250498
all_values[0]	auto[1]	auto[0]	auto[1]	78312	1			T37	3515		T48	2		T20	4
all_values[0]	auto[1]	auto[1]	auto[1]	78036	1			T37	3503		T20	2		T25	164
all_values[1]	auto[0]	auto[0]	auto[0]	2744960	1			T30	1		T31	273		T32	55284
all_values[1]	auto[0]	auto[0]	auto[1]	5367498	1			T34	350		T35	327		T37	253152
all_values[1]	auto[0]	auto[1]	auto[0]	582280	1			T34	62		T35	18		T37	27673
all_values[1]	auto[0]	auto[1]	auto[1]	5360358	1			T34	642		T35	187		T37	244948
all_values[1]	auto[1]	auto[0]	auto[1]	77779	1			T37	3340		T20	6		T25	167
all_values[1]	auto[1]	auto[1]	auto[1]	78415	1			T37	3654		T48	1		T20	3
all_values[2]	auto[0]	auto[0]	auto[0]	2735237	1			T30	1		T31	273		T32	55284
all_values[2]	auto[0]	auto[0]	auto[1]	5380467	1			T34	532		T35	214		T37	247987
all_values[2]	auto[0]	auto[1]	auto[0]	584632	1			T34	44		T35	9		T37	27690
all_values[2]	auto[0]	auto[1]	auto[1]	5354744	1			T34	510		T35	345		T37	249875
all_values[2]	auto[1]	auto[0]	auto[1]	78696	1			T37	3569		T48	4		T20	4
all_values[2]	auto[1]	auto[1]	auto[1]	77514	1			T37	3519		T20	3		T25	194
all_values[3]	auto[0]	auto[0]	auto[0]	2737883	1			T30	1		T31	273		T32	55284
all_values[3]	auto[0]	auto[0]	auto[1]	5391909	1			T34	469		T35	263		T37	246661
all_values[3]	auto[0]	auto[1]	auto[0]	583980	1			T34	74		T35	25		T37	26351
all_values[3]	auto[0]	auto[1]	auto[1]	5341323	1			T34	492		T35	275		T37	251720
all_values[3]	auto[1]	auto[0]	auto[1]	78376	1			T37	3549		T48	2		T20	2
all_values[3]	auto[1]	auto[1]	auto[1]	77819	1			T37	3581		T48	1		T20	5
all_values[4]	auto[0]	auto[0]	auto[0]	2748392	1			T30	1		T31	273		T32	55284
all_values[4]	auto[0]	auto[0]	auto[1]	5341552	1			T34	464		T35	263		T37	247842
all_values[4]	auto[0]	auto[1]	auto[0]	589498	1			T34	71		T35	17		T37	29096
all_values[4]	auto[0]	auto[1]	auto[1]	5375519	1			T34	537		T35	255		T37	249236
all_values[4]	auto[1]	auto[0]	auto[1]	78703	1			T37	3542		T48	3		T20	7
all_values[4]	auto[1]	auto[1]	auto[1]	77626	1			T37	3518		T48	1		T20	3
all_values[5]	auto[0]	auto[0]	auto[0]	2746759	1			T30	1		T31	273		T32	55284
all_values[5]	auto[0]	auto[0]	auto[1]	5364401	1			T34	648		T35	243		T37	250141
all_values[5]	auto[0]	auto[1]	auto[0]	583860	1			T34	27		T35	12		T37	25632
all_values[5]	auto[0]	auto[1]	auto[1]	5360027	1			T34	344		T35	318		T37	250433
all_values[5]	auto[1]	auto[0]	auto[1]	78566	1			T37	3576		T48	2		T20	6
all_values[5]	auto[1]	auto[1]	auto[1]	77677	1			T37	3569		T48	1		T20	2
all_values[6]	auto[0]	auto[0]	auto[0]	2740879	1			T30	1		T31	273		T32	55284
all_values[6]	auto[0]	auto[0]	auto[1]	5376586	1			T34	291		T35	344		T37	248851
all_values[6]	auto[0]	auto[1]	auto[0]	578837	1			T34	54		T35	43		T37	26252
all_values[6]	auto[0]	auto[1]	auto[1]	5359099	1			T34	698		T35	177		T37	251680
all_values[6]	auto[1]	auto[0]	auto[1]	78077	1			T37	3373		T48	1		T20	7
all_values[6]	auto[1]	auto[1]	auto[1]	77812	1			T37	3619		T20	7		T25	188
all_values[7]	auto[0]	auto[0]	auto[0]	2751609	1			T30	1		T31	273		T32	55284
all_values[7]	auto[0]	auto[0]	auto[1]	5359729	1			T34	598		T35	218		T37	244238
all_values[7]	auto[0]	auto[1]	auto[0]	585693	1			T34	37		T35	10		T37	25755
all_values[7]	auto[0]	auto[1]	auto[1]	5357896	1			T34	399		T35	344		T37	256834
all_values[7]	auto[1]	auto[0]	auto[1]	77826	1			T37	3487		T48	1		T20	6
all_values[7]	auto[1]	auto[1]	auto[1]	78537	1			T37	3477		T48	1		T20	4
all_values[8]	auto[0]	auto[0]	auto[0]	2738457	1			T30	1		T31	273		T32	55284
all_values[8]	auto[0]	auto[0]	auto[1]	5389329	1			T34	544		T35	219		T37	259764
all_values[8]	auto[0]	auto[1]	auto[0]	584724	1			T34	56		T35	21		T37	27145
all_values[8]	auto[0]	auto[1]	auto[1]	5342840	1			T34	455		T35	322		T37	239549
all_values[8]	auto[1]	auto[0]	auto[1]	78369	1			T37	3471		T20	7		T25	192
all_values[8]	auto[1]	auto[1]	auto[1]	77571	1			T37	3553		T48	1		T20	2
all_values[9]	auto[0]	auto[0]	auto[0]	2739231	1			T30	1		T31	273		T32	55284
all_values[9]	auto[0]	auto[0]	auto[1]	5375310	1			T34	584		T35	208		T37	249497
all_values[9]	auto[0]	auto[1]	auto[0]	587610	1			T34	73		T35	6		T37	27698
all_values[9]	auto[0]	auto[1]	auto[1]	5352710	1			T34	372		T35	363		T37	248883
all_values[9]	auto[1]	auto[0]	auto[1]	78378	1			T37	3607		T48	1		T20	7
all_values[9]	auto[1]	auto[1]	auto[1]	78051	1			T37	3382		T48	2		T20	2
all_values[10]	auto[0]	auto[0]	auto[0]	2736083	1			T30	1		T31	273		T32	55284
all_values[10]	auto[0]	auto[0]	auto[1]	5370779	1			T34	671		T35	239		T37	248030
all_values[10]	auto[0]	auto[1]	auto[0]	589895	1			T34	17		T35	15		T37	29585
all_values[10]	auto[0]	auto[1]	auto[1]	5358790	1			T34	298		T35	308		T37	246599
all_values[10]	auto[1]	auto[0]	auto[1]	78205	1			T37	3550		T20	5		T25	180
all_values[10]	auto[1]	auto[1]	auto[1]	77538	1			T37	3390		T48	1		T20	3
all_values[11]	auto[0]	auto[0]	auto[0]	2738496	1			T30	1		T31	273		T32	55284
all_values[11]	auto[0]	auto[0]	auto[1]	5368392	1			T34	623		T35	311		T37	256209
all_values[11]	auto[0]	auto[1]	auto[0]	589537	1			T34	48		T35	23		T37	28693
all_values[11]	auto[0]	auto[1]	auto[1]	5358472	1			T34	382		T35	220		T37	242131
all_values[11]	auto[1]	auto[0]	auto[1]	78157	1			T37	3552		T48	1		T20	5
all_values[11]	auto[1]	auto[1]	auto[1]	78236	1			T37	3553		T48	3		T20	3
all_values[12]	auto[0]	auto[0]	auto[0]	2742386	1			T30	1		T31	273		T32	55284
all_values[12]	auto[0]	auto[0]	auto[1]	5337979	1			T34	402		T35	180		T37	239820
all_values[12]	auto[0]	auto[1]	auto[0]	579911	1			T34	50		T35	29		T37	27235
all_values[12]	auto[0]	auto[1]	auto[1]	5394650	1			T34	604		T35	363		T37	254580
all_values[12]	auto[1]	auto[0]	auto[1]	78314	1			T37	3471		T48	1		T20	6
all_values[12]	auto[1]	auto[1]	auto[1]	78050	1			T37	3537		T48	1		T20	4
all_values[13]	auto[0]	auto[0]	auto[0]	2738506	1			T30	1		T31	273		T32	55284
all_values[13]	auto[0]	auto[0]	auto[1]	5363474	1			T34	313		T35	327		T37	244526
all_values[13]	auto[0]	auto[1]	auto[0]	578576	1			T34	99		T35	8		T37	25773
all_values[13]	auto[0]	auto[1]	auto[1]	5374377	1			T34	624		T35	191		T37	256577
all_values[13]	auto[1]	auto[0]	auto[1]	78787	1			T37	3632		T48	4		T20	4
all_values[13]	auto[1]	auto[1]	auto[1]	77570	1			T37	3544		T20	1		T25	182
all_values[14]	auto[0]	auto[0]	auto[0]	2738631	1			T30	1		T31	273		T32	55284
all_values[14]	auto[0]	auto[0]	auto[1]	5365680	1			T34	578		T35	203		T37	250463
all_values[14]	auto[0]	auto[1]	auto[0]	585999	1			T34	56		T35	35		T37	28986
all_values[14]	auto[0]	auto[1]	auto[1]	5364704	1			T34	413		T35	325		T37	245187
all_values[14]	auto[1]	auto[0]	auto[1]	78488	1			T37	3630		T48	4		T20	9
all_values[14]	auto[1]	auto[1]	auto[1]	77788	1			T37	3476		T48	1		T25	177
all_values[15]	auto[0]	auto[0]	auto[0]	2750138	1			T30	1		T31	273		T32	55284
all_values[15]	auto[0]	auto[0]	auto[1]	5351446	1			T34	377		T35	351		T37	255944
all_values[15]	auto[0]	auto[1]	auto[0]	577066	1			T34	83		T35	10		T37	24936
all_values[15]	auto[0]	auto[1]	auto[1]	5375877	1			T34	620		T35	191		T37	244893
all_values[15]	auto[1]	auto[0]	auto[1]	78529	1			T37	3418		T48	2		T20	7
all_values[15]	auto[1]	auto[1]	auto[1]	78234	1			T37	3478		T48	1		T20	3
all_values[16]	auto[0]	auto[0]	auto[0]	2743317	1			T30	1		T31	273		T32	55284
all_values[16]	auto[0]	auto[0]	auto[1]	5338168	1			T34	531		T35	190		T37	248146
all_values[16]	auto[0]	auto[1]	auto[0]	579528	1			T34	20		T35	17		T37	26013
all_values[16]	auto[0]	auto[1]	auto[1]	5394135	1			T34	494		T35	348		T37	251987
all_values[16]	auto[1]	auto[0]	auto[1]	77848	1			T37	3495		T48	1		T20	4
all_values[16]	auto[1]	auto[1]	auto[1]	78294	1			T37	3587		T48	2		T20	3
all_values[17]	auto[0]	auto[0]	auto[0]	2742607	1			T30	1		T31	273		T32	55284
all_values[17]	auto[0]	auto[0]	auto[1]	5378215	1			T34	454		T35	365		T37	248451
all_values[17]	auto[0]	auto[1]	auto[0]	581752	1			T34	48		T35	5		T37	26966
all_values[17]	auto[0]	auto[1]	auto[1]	5352511	1			T34	588		T35	190		T37	246793
all_values[17]	auto[1]	auto[0]	auto[1]	78108	1			T37	3479		T48	2		T20	6
all_values[17]	auto[1]	auto[1]	auto[1]	78097	1			T37	3594		T48	1		T20	6
all_values[18]	auto[0]	auto[0]	auto[0]	2740677	1			T30	1		T31	273		T32	55284
all_values[18]	auto[0]	auto[0]	auto[1]	5378341	1			T34	584		T35	276		T37	252817
all_values[18]	auto[0]	auto[1]	auto[0]	582990	1			T34	64		T35	31		T37	28814
all_values[18]	auto[0]	auto[1]	auto[1]	5353087	1			T34	426		T35	266		T37	244856
all_values[18]	auto[1]	auto[0]	auto[1]	78516	1			T37	3550		T48	3		T20	5
all_values[18]	auto[1]	auto[1]	auto[1]	77679	1			T37	3564		T20	4		T25	171
all_values[19]	auto[0]	auto[0]	auto[0]	2744700	1			T30	1		T31	273		T32	55284
all_values[19]	auto[0]	auto[0]	auto[1]	5395854	1			T34	373		T35	414		T37	257218
all_values[19]	auto[0]	auto[1]	auto[0]	587879	1			T34	39		T35	9		T37	27461
all_values[19]	auto[0]	auto[1]	auto[1]	5327162	1			T34	662		T35	141		T37	241610
all_values[19]	auto[1]	auto[0]	auto[1]	78861	1			T37	3574		T48	2		T20	5
all_values[19]	auto[1]	auto[1]	auto[1]	76834	1			T37	3514		T48	1		T20	3
all_values[20]	auto[0]	auto[0]	auto[0]	2739489	1			T30	1		T31	273		T32	55284
all_values[20]	auto[0]	auto[0]	auto[1]	5364093	1			T34	434		T35	199		T37	250359
all_values[20]	auto[0]	auto[1]	auto[0]	582622	1			T34	39		T35	15		T37	26864
all_values[20]	auto[0]	auto[1]	auto[1]	5368785	1			T34	545		T35	357		T37	248377
all_values[20]	auto[1]	auto[0]	auto[1]	78578	1			T37	3417		T48	2		T20	6
all_values[20]	auto[1]	auto[1]	auto[1]	77723	1			T37	3526		T48	1		T20	4
all_values[21]	auto[0]	auto[0]	auto[0]	2743612	1			T30	1		T31	273		T32	55284
all_values[21]	auto[0]	auto[0]	auto[1]	5387669	1			T34	461		T35	268		T37	254149
all_values[21]	auto[0]	auto[1]	auto[0]	578355	1			T34	55		T35	2		T37	26635
all_values[21]	auto[0]	auto[1]	auto[1]	5345452	1			T34	566		T35	306		T37	246527
all_values[21]	auto[1]	auto[0]	auto[1]	78654	1			T37	3509		T20	4		T25	177
all_values[21]	auto[1]	auto[1]	auto[1]	77548	1			T37	3571		T48	2		T20	1
all_values[22]	auto[0]	auto[0]	auto[0]	2740318	1			T30	1		T31	273		T32	55284
all_values[22]	auto[0]	auto[0]	auto[1]	5396277	1			T34	530		T35	329		T37	241761
all_values[22]	auto[0]	auto[1]	auto[0]	580378	1			T34	54		T35	3		T37	29074
all_values[22]	auto[0]	auto[1]	auto[1]	5338517	1			T34	459		T35	222		T37	254895
all_values[22]	auto[1]	auto[0]	auto[1]	78178	1			T37	3472		T48	2		T20	7
all_values[22]	auto[1]	auto[1]	auto[1]	77622	1			T37	3519		T48	2		T20	3
all_values[23]	auto[0]	auto[0]	auto[0]	2749030	1			T30	1		T31	273		T32	55284
all_values[23]	auto[0]	auto[0]	auto[1]	5370233	1			T34	462		T35	158		T37	242135
all_values[23]	auto[0]	auto[1]	auto[0]	586164	1			T34	39		T35	64		T37	27789
all_values[23]	auto[0]	auto[1]	auto[1]	5349598	1			T34	557		T35	345		T37	254577
all_values[23]	auto[1]	auto[0]	auto[1]	78409	1			T37	3618		T20	5		T25	200
all_values[23]	auto[1]	auto[1]	auto[1]	77856	1			T37	3492		T48	1		T20	4
all_values[24]	auto[0]	auto[0]	auto[0]	2735390	1			T30	1		T31	273		T32	55284
all_values[24]	auto[0]	auto[0]	auto[1]	5348584	1			T34	549		T35	174		T37	248337
all_values[24]	auto[0]	auto[1]	auto[0]	592159	1			T34	29		T35	26		T37	26769
all_values[24]	auto[0]	auto[1]	auto[1]	5378888	1			T34	472		T35	362		T37	249401
all_values[24]	auto[1]	auto[0]	auto[1]	78237	1			T37	3563		T48	1		T20	7
all_values[24]	auto[1]	auto[1]	auto[1]	78032	1			T37	3572		T48	2		T20	3
all_values[25]	auto[0]	auto[0]	auto[0]	2738445	1			T30	1		T31	273		T32	55284
all_values[25]	auto[0]	auto[0]	auto[1]	5401761	1			T34	356		T35	235		T37	243746
all_values[25]	auto[0]	auto[1]	auto[0]	578285	1			T34	102		T35	44		T37	27857
all_values[25]	auto[0]	auto[1]	auto[1]	5337072	1			T34	626		T35	276		T37	253487
all_values[25]	auto[1]	auto[0]	auto[1]	78174	1			T37	3461		T48	2		T20	7
all_values[25]	auto[1]	auto[1]	auto[1]	77553	1			T37	3650		T20	3		T25	175
all_values[26]	auto[0]	auto[0]	auto[0]	2737176	1			T30	1		T31	273		T32	55284
all_values[26]	auto[0]	auto[0]	auto[1]	5348712	1			T34	462		T35	302		T37	242921
all_values[26]	auto[0]	auto[1]	auto[0]	590296	1			T34	61		T35	33		T37	31472
all_values[26]	auto[0]	auto[1]	auto[1]	5379078	1			T34	548		T35	201		T37	252938
all_values[26]	auto[1]	auto[0]	auto[1]	77941	1			T37	3541		T48	3		T20	5
all_values[26]	auto[1]	auto[1]	auto[1]	78087	1			T37	3582		T48	1		T20	2
all_values[27]	auto[0]	auto[0]	auto[0]	2739590	1			T30	1		T31	273		T32	55284
all_values[27]	auto[0]	auto[0]	auto[1]	5371884	1			T34	543		T35	305		T37	246504
all_values[27]	auto[0]	auto[1]	auto[0]	585600	1			T34	63		T35	37		T37	27523
all_values[27]	auto[0]	auto[1]	auto[1]	5357773	1			T34	417		T35	214		T37	253024
all_values[27]	auto[1]	auto[0]	auto[1]	78868	1			T37	3514		T48	1		T20	5
all_values[27]	auto[1]	auto[1]	auto[1]	77575	1			T37	3583		T48	1		T20	6
all_values[28]	auto[0]	auto[0]	auto[0]	2746063	1			T30	1		T31	273		T32	55284
all_values[28]	auto[0]	auto[0]	auto[1]	5378458	1			T34	562		T35	342		T37	247054
all_values[28]	auto[0]	auto[1]	auto[0]	587153	1			T34	26		T35	24		T37	28045
all_values[28]	auto[0]	auto[1]	auto[1]	5343093	1			T34	454		T35	194		T37	250060
all_values[28]	auto[1]	auto[0]	auto[1]	78635	1			T37	3497		T48	4		T20	7
all_values[28]	auto[1]	auto[1]	auto[1]	77888	1			T37	3526		T48	1		T20	1
all_values[29]	auto[0]	auto[0]	auto[0]	2743286	1			T30	1		T31	273		T32	55284
all_values[29]	auto[0]	auto[0]	auto[1]	5368974	1			T34	435		T35	245		T37	246566
all_values[29]	auto[0]	auto[1]	auto[0]	578650	1			T34	15		T35	10		T37	26468
all_values[29]	auto[0]	auto[1]	auto[1]	5364388	1			T34	589		T35	304		T37	253478
all_values[29]	auto[1]	auto[0]	auto[1]	78257	1			T37	3395		T20	5		T25	216
all_values[29]	auto[1]	auto[1]	auto[1]	77735	1			T37	3569		T48	1		T20	4
all_values[30]	auto[0]	auto[0]	auto[0]	2749265	1			T30	1		T31	273		T32	55284
all_values[30]	auto[0]	auto[0]	auto[1]	5371816	1			T34	470		T35	230		T37	247661
all_values[30]	auto[0]	auto[1]	auto[0]	584359	1			T34	43		T35	68		T37	28012
all_values[30]	auto[0]	auto[1]	auto[1]	5349376	1			T34	525		T35	276		T37	248321
all_values[30]	auto[1]	auto[0]	auto[1]	78404	1			T37	3498		T48	2		T20	9
all_values[30]	auto[1]	auto[1]	auto[1]	78070	1			T37	3462		T48	2		T20	2
all_values[31]	auto[0]	auto[0]	auto[0]	2741045	1			T30	1		T31	273		T32	55284
all_values[31]	auto[0]	auto[0]	auto[1]	5369304	1			T34	411		T35	208		T37	253968
all_values[31]	auto[0]	auto[1]	auto[0]	579037	1			T34	49		T35	11		T37	26158
all_values[31]	auto[0]	auto[1]	auto[1]	5366058	1			T34	573		T35	352		T37	245578
all_values[31]	auto[1]	auto[0]	auto[1]	78309	1			T37	3616		T48	2		T20	8
all_values[31]	auto[1]	auto[1]	auto[1]	77537	1			T37	3405		T48	2		T20	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal