Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[1]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[2]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[3]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[4]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[5]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[6]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[7]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[8]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[9]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[10]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[11]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[12]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[13]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[14]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[15]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[16]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[17]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[18]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[19]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[20]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[21]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[22]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[23]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[24]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[25]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[26]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[27]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[28]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[29]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[30]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[31]	13998114	1			T30	1		T31	351		T32	55284

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263836864

1

T30

32

T31

6852

T32

886769

auto[1]

184102784

1

T31

4380

T32

882319

T33

713821

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

359243858

1

T30

32

T31

8775

T32

176908

auto[1]

88695790

1

T31

2457

T36

1538

T37

384430

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

333214268

1

T30

32

T31

8732

T32

176908

auto[1]

114725380

1

T31

2500

T36

2852

T37

500480

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5137945	1			T30	1		T31	135		T32	29422
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3876837	1			T31	93		T32	25862		T33	22742
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1393642	1			T31	64		T36	46		T37	59740
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1709456	1			T31	31		T36	53		T37	89355
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	492221	1			T36	7		T37	6190		T48	4
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1388013	1			T31	28		T36	28		T37	59949
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5137896	1			T30	1		T31	132		T32	27951
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3877816	1			T31	94		T32	27333		T33	22273
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1400413	1			T31	42		T36	18		T37	59556
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1708498	1			T31	44		T36	65		T37	90761
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	490746	1			T36	2		T37	6410		T48	9
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1382745	1			T31	39		T36	17		T37	60842
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5137578	1			T30	1		T31	155		T32	29157
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3879507	1			T31	87		T32	26127		T33	22645
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1390992	1			T31	30		T36	26		T37	59931
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1712885	1			T31	44		T36	46		T37	89475
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	494315	1			T36	6		T37	6389		T48	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1382837	1			T31	35		T36	21		T37	60355
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5140991	1			T30	1		T31	163		T32	28083
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3878771	1			T31	87		T32	27201		T33	21252
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1393782	1			T31	53		T36	15		T37	60768
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1710798	1			T31	28		T36	47		T37	89811
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	491974	1			T36	1		T37	6491		T48	6
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1381798	1			T31	20		T36	17		T37	59957
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5133865	1			T30	1		T31	159		T32	26567
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3886354	1			T31	90		T32	28717		T33	21506
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1395963	1			T31	22		T36	18		T37	60164
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1712593	1			T31	54		T36	64		T37	89866
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	489163	1			T36	3		T37	6686		T48	8
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1380176	1			T31	26		T36	15		T37	60378
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5144045	1			T30	1		T31	123		T32	25345
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3879209	1			T31	109		T32	29939		T33	22117
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1393535	1			T31	43		T36	12		T37	59612
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1709966	1			T31	42		T36	69		T37	90075
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	491054	1			T36	6		T37	6498		T48	7
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1380305	1			T31	34		T36	40		T37	59895
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5142734	1			T30	1		T31	121		T32	26641
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3880678	1			T31	107		T32	28643		T33	21333
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1391035	1			T31	40		T36	50		T37	60321
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1712359	1			T31	39		T36	55		T37	91126
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	491367	1			T36	6		T37	6399		T48	10
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1379941	1			T31	44		T36	4		T37	59661
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5150781	1			T30	1		T31	130		T32	27055
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3864898	1			T31	103		T32	28229		T33	21363
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1395419	1			T31	26		T36	43		T37	60039
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1707832	1			T31	46		T36	51		T37	88730
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	491608	1			T36	4		T37	6352		T48	6
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1387576	1			T31	46		T36	18		T37	60899
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5144921	1			T30	1		T31	122		T32	28615
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3874506	1			T31	102		T32	26669		T33	23525
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1392808	1			T31	36		T36	35		T37	60217
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1711083	1			T31	42		T36	54		T37	89806
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	492063	1			T36	4		T37	6281		T48	9
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1382733	1			T31	49		T36	28		T37	58778
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5141634	1			T30	1		T31	132		T32	27381
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3872854	1			T31	96		T32	27903		T33	21202
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1393899	1			T31	59		T36	27		T37	60240
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1711598	1			T31	34		T36	91		T37	89998
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	492467	1			T36	7		T37	6421		T48	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1385662	1			T31	30		T36	14		T37	60258
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5141130	1			T30	1		T31	148		T32	28349
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3877673	1			T31	88		T32	26935		T33	21813
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1387172	1			T31	44		T36	22		T37	60060
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1714926	1			T31	35		T36	80		T37	90326
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	493973	1			T36	4		T37	6351		T20	15
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1383240	1			T31	36		T36	6		T37	60037
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5139783	1			T30	1		T31	142		T32	26028
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3884731	1			T31	104		T32	29256		T33	22411
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1392766	1			T31	26		T36	13		T37	60990
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1707689	1			T31	44		T36	79		T37	88420
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	492869	1			T36	6		T37	6434		T48	8
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1380276	1			T31	35		T36	36		T37	60981
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5146152	1			T30	1		T31	130		T32	27156
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3870278	1			T31	104		T32	28128		T33	22131
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1393587	1			T31	49		T36	19		T37	60050
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1713345	1			T31	40		T36	76		T37	90872
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	493033	1			T36	8		T37	6283		T48	3
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1381719	1			T31	28		T36	6		T37	59836
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5146299	1			T30	1		T31	131		T32	28488
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3872499	1			T31	103		T32	26796		T33	20747
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1393568	1			T31	37		T36	20		T37	61346
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1709847	1			T31	32		T36	97		T37	88709
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	490458	1			T36	11		T37	6368		T20	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1385443	1			T31	48		T36	40		T37	59674
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5132358	1			T30	1		T31	127		T32	25575
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3889954	1			T31	103		T32	29709		T33	22882
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1392592	1			T31	34		T36	21		T37	59904
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1708036	1			T31	33		T36	52		T37	89539
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	489058	1			T36	6		T37	6355		T48	3
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1386116	1			T31	54		T36	30		T37	60444
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5139000	1			T30	1		T31	142		T32	26894
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3881005	1			T31	100		T32	28390		T33	22735
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1393669	1			T31	18		T36	40		T37	59950
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1713993	1			T31	60		T36	59		T37	90361
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	492915	1			T36	5		T37	6429		T48	10
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1377532	1			T31	31		T36	19		T37	59303
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5145063	1			T30	1		T31	126		T32	26470
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3881449	1			T31	104		T32	28814		T33	23037
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1389088	1			T31	41		T36	43		T37	60244
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1716188	1			T31	32		T36	64		T37	91345
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	493259	1			T36	10		T37	6613		T48	4
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1373067	1			T31	48		T36	15		T37	60028
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5142774	1			T30	1		T31	144		T32	27570
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3883978	1			T31	87		T32	27714		T33	21747
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1384945	1			T31	28		T36	44		T37	59886
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1716271	1			T31	36		T36	59		T37	89468
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	493734	1			T36	7		T37	6539		T48	2
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1376412	1			T31	56		T36	14		T37	60471
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5140107	1			T30	1		T31	132		T32	28229
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3882840	1			T31	104		T32	27055		T33	21525
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1387215	1			T31	36		T36	6		T37	61067
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1716448	1			T31	34		T36	61		T37	89534
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	492676	1			T36	4		T37	6141		T48	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1378828	1			T31	45		T36	34		T37	59989
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5143143	1			T30	1		T31	121		T32	28681
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3880804	1			T31	95		T32	26603		T33	24306
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1388570	1			T31	56		T36	2		T37	60962
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1713619	1			T31	38		T36	110		T37	89631
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	491859	1			T36	5		T37	6543		T48	12
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1380119	1			T31	41		T36	19		T37	59848
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5142978	1			T30	1		T31	139		T32	27973
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3885309	1			T31	95		T32	27311		T33	21218
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1387855	1			T31	33		T36	36		T37	59369
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1718530	1			T31	48		T36	55		T37	91320
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	491875	1			T36	5		T37	6480		T20	13
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1371567	1			T31	36		T36	25		T37	59501
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5139079	1			T30	1		T31	144		T32	26935
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3883604	1			T31	96		T32	28349		T33	22689
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1390229	1			T31	32		T36	27		T37	60184
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1714431	1			T31	34		T36	50		T37	89724
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	492844	1			T36	5		T37	6604		T48	8
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1377927	1			T31	45		T36	27		T37	60418
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5136168	1			T30	1		T31	141		T32	27167
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3895130	1			T31	101		T32	28117		T33	22880
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1390025	1			T31	45		T36	49		T37	60458
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1712645	1			T31	32		T36	22		T37	90236
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	492446	1			T36	1		T37	6429		T48	3
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1371700	1			T31	32		T36	4		T37	58160
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5146926	1			T30	1		T31	137		T32	29019
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3879134	1			T31	99		T32	26265		T33	22631
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1385707	1			T31	20		T36	9		T37	60244
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1714136	1			T31	54		T36	86		T37	90412
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	493028	1			T36	8		T37	6540		T48	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1379183	1			T31	41		T36	15		T37	59166
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5144586	1			T30	1		T31	139		T32	30302
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3880960	1			T31	100		T32	24982		T33	24140
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1394817	1			T31	48		T36	23		T37	61661
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1707815	1			T31	36		T36	62		T37	89773
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	493641	1			T36	7		T37	6559		T48	7
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1376295	1			T31	28		T36	16		T37	58942
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5136749	1			T30	1		T31	161		T32	28228
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3884912	1			T31	105		T32	27056		T33	24720
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1391651	1			T31	29		T36	56		T37	59627
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1713796	1			T31	32		T36	30		T37	91174
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	491427	1			T36	6		T37	6378		T48	8
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1379579	1			T31	24		T36	17		T37	59914
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5132948	1			T30	1		T31	141		T32	27900
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3887636	1			T31	105		T32	27384		T33	22362
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1390712	1			T31	37		T36	27		T37	59932
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1717669	1			T31	40		T36	62		T37	90837
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	490805	1			T36	6		T37	6324		T48	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1378344	1			T31	28		T36	17		T37	60727
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5129559	1			T30	1		T31	142		T32	25895
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3890266	1			T31	86		T32	29389		T33	22545
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1387805	1			T31	44		T36	39		T37	60457
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1714421	1			T31	39		T36	46		T37	90163
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	496906	1			T36	10		T37	6338		T20	9
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1379157	1			T31	40		T36	27		T37	59419
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5143145	1			T30	1		T31	130		T32	28411
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3877516	1			T31	92		T32	26873		T33	22085
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1391625	1			T31	42		T36	12		T37	59474
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1711017	1			T31	40		T36	71		T37	90627
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	492449	1			T36	11		T37	6574		T20	17
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1382362	1			T31	47		T36	31		T37	60418
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5140481	1			T30	1		T31	128		T32	30014
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3879130	1			T31	106		T32	25270		T33	22088
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1388194	1			T31	30		T36	31		T37	59522
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1714930	1			T31	32		T36	51		T37	90039
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	494312	1			T36	4		T37	6416		T20	3
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1381067	1			T31	55		T36	16		T37	59124
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5141772	1			T30	1		T31	122		T32	27295
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3881324	1			T31	105		T32	27989		T33	22520
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1393620	1			T31	44		T36	4		T37	60953
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1712254	1			T31	36		T36	104		T37	89542
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	490432	1			T36	14		T37	6347		T48	8
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1378712	1			T31	44		T36	17		T37	60326
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5144815	1			T30	1		T31	142		T32	27973
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3878754	1			T31	87		T32	27311		T33	20651
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1389647	1			T31	26		T36	66		T37	59898
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1713838	1			T31	46		T36	46		T37	90472
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	492248	1			T36	7		T37	6634		T48	7
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1378812	1			T31	50		T36	6		T37	59784

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal