Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[1]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[2]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[3]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[4]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[5]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[6]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[7]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[8]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[9]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[10]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[11]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[12]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[13]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[14]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[15]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[16]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[17]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[18]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[19]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[20]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[21]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[22]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[23]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[24]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[25]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[26]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[27]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[28]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[29]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[30]	13998114	1			T30	1		T31	351		T32	55284
bins_for_gpio_bits[31]	13998114	1			T30	1		T31	351		T32	55284

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263836864

1

T30

32

T31

6852

T32

886769

auto[1]

184102784

1

T31

4380

T32

882319

T33

713821

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263830856

1

T30

32

T31

6841

T32

886769

auto[1]

184108792

1

T31

4391

T32

882319

T33

713821

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7992514	1			T30	1		T31	221		T32	29422
bins_for_gpio_bits[0]	auto[0]	auto[1]	248334	1			T31	9		T36	6		T37	10691
bins_for_gpio_bits[0]	auto[1]	auto[0]	248529	1			T31	9		T36	6		T37	10694
bins_for_gpio_bits[0]	auto[1]	auto[1]	5508737	1			T31	112		T32	25862		T33	22742
bins_for_gpio_bits[1]	auto[0]	auto[0]	7999037	1			T30	1		T31	209		T32	27951
bins_for_gpio_bits[1]	auto[0]	auto[1]	247570	1			T31	8		T36	3		T37	10738
bins_for_gpio_bits[1]	auto[1]	auto[0]	247770	1			T31	9		T36	3		T37	10741
bins_for_gpio_bits[1]	auto[1]	auto[1]	5503737	1			T31	125		T32	27333		T33	22273
bins_for_gpio_bits[2]	auto[0]	auto[0]	7994139	1			T30	1		T31	218		T32	29157
bins_for_gpio_bits[2]	auto[0]	auto[1]	247105	1			T31	10		T36	2		T37	10653
bins_for_gpio_bits[2]	auto[1]	auto[0]	247316	1			T31	11		T36	2		T37	10654
bins_for_gpio_bits[2]	auto[1]	auto[1]	5509554	1			T31	112		T32	26127		T33	22645
bins_for_gpio_bits[3]	auto[0]	auto[0]	7998603	1			T30	1		T31	237		T32	28083
bins_for_gpio_bits[3]	auto[0]	auto[1]	246826	1			T31	7		T36	3		T37	10673
bins_for_gpio_bits[3]	auto[1]	auto[0]	246968	1			T31	7		T36	3		T37	10675
bins_for_gpio_bits[3]	auto[1]	auto[1]	5505717	1			T31	100		T32	27201		T33	21252
bins_for_gpio_bits[4]	auto[0]	auto[0]	7994921	1			T30	1		T31	229		T32	26567
bins_for_gpio_bits[4]	auto[0]	auto[1]	247329	1			T31	6		T36	3		T37	10684
bins_for_gpio_bits[4]	auto[1]	auto[0]	247500	1			T31	6		T36	3		T37	10684
bins_for_gpio_bits[4]	auto[1]	auto[1]	5508364	1			T31	110		T32	28717		T33	21506
bins_for_gpio_bits[5]	auto[0]	auto[0]	8000767	1			T30	1		T31	201		T32	25345
bins_for_gpio_bits[5]	auto[0]	auto[1]	246596	1			T31	7		T36	4		T37	10558
bins_for_gpio_bits[5]	auto[1]	auto[0]	246779	1			T31	7		T36	4		T37	10558
bins_for_gpio_bits[5]	auto[1]	auto[1]	5503972	1			T31	136		T32	29939		T33	22117
bins_for_gpio_bits[6]	auto[0]	auto[0]	7998965	1			T30	1		T31	188		T32	26641
bins_for_gpio_bits[6]	auto[0]	auto[1]	246993	1			T31	12		T36	2		T37	10740
bins_for_gpio_bits[6]	auto[1]	auto[0]	247163	1			T31	12		T36	2		T37	10740
bins_for_gpio_bits[6]	auto[1]	auto[1]	5504993	1			T31	139		T32	28643		T33	21333
bins_for_gpio_bits[7]	auto[0]	auto[0]	8005969	1			T30	1		T31	189		T32	27055
bins_for_gpio_bits[7]	auto[0]	auto[1]	247893	1			T31	13		T36	5		T37	10783
bins_for_gpio_bits[7]	auto[1]	auto[0]	248063	1			T31	13		T36	5		T37	10784
bins_for_gpio_bits[7]	auto[1]	auto[1]	5496189	1			T31	136		T32	28229		T33	21363
bins_for_gpio_bits[8]	auto[0]	auto[0]	8001753	1			T30	1		T31	187		T32	28615
bins_for_gpio_bits[8]	auto[0]	auto[1]	246877	1			T31	12		T36	6		T37	10444
bins_for_gpio_bits[8]	auto[1]	auto[0]	247059	1			T31	13		T36	6		T37	10444
bins_for_gpio_bits[8]	auto[1]	auto[1]	5502425	1			T31	139		T32	26669		T33	23525
bins_for_gpio_bits[9]	auto[0]	auto[0]	7999132	1			T30	1		T31	216		T32	27381
bins_for_gpio_bits[9]	auto[0]	auto[1]	247801	1			T31	9		T36	2		T37	10751
bins_for_gpio_bits[9]	auto[1]	auto[0]	247999	1			T31	9		T36	2		T37	10752
bins_for_gpio_bits[9]	auto[1]	auto[1]	5503182	1			T31	117		T32	27903		T33	21202
bins_for_gpio_bits[10]	auto[0]	auto[0]	7995687	1			T30	1		T31	219		T32	28349
bins_for_gpio_bits[10]	auto[0]	auto[1]	247376	1			T31	8		T36	2		T37	10664
bins_for_gpio_bits[10]	auto[1]	auto[0]	247541	1			T31	8		T36	2		T37	10668
bins_for_gpio_bits[10]	auto[1]	auto[1]	5507510	1			T31	116		T32	26935		T33	21813
bins_for_gpio_bits[11]	auto[0]	auto[0]	7993201	1			T30	1		T31	202		T32	26028
bins_for_gpio_bits[11]	auto[0]	auto[1]	246877	1			T31	9		T36	5		T37	10720
bins_for_gpio_bits[11]	auto[1]	auto[0]	247037	1			T31	10		T36	5		T37	10724
bins_for_gpio_bits[11]	auto[1]	auto[1]	5510999	1			T31	130		T32	29256		T33	22411
bins_for_gpio_bits[12]	auto[0]	auto[0]	8005332	1			T30	1		T31	208		T32	27156
bins_for_gpio_bits[12]	auto[0]	auto[1]	247551	1			T31	11		T36	3		T37	10587
bins_for_gpio_bits[12]	auto[1]	auto[0]	247752	1			T31	11		T36	3		T37	10587
bins_for_gpio_bits[12]	auto[1]	auto[1]	5497479	1			T31	121		T32	28128		T33	22131
bins_for_gpio_bits[13]	auto[0]	auto[0]	8001750	1			T30	1		T31	188		T32	28488
bins_for_gpio_bits[13]	auto[0]	auto[1]	247784	1			T31	12		T36	7		T37	10613
bins_for_gpio_bits[13]	auto[1]	auto[0]	247964	1			T31	12		T36	7		T37	10614
bins_for_gpio_bits[13]	auto[1]	auto[1]	5500616	1			T31	139		T32	26796		T33	20747
bins_for_gpio_bits[14]	auto[0]	auto[0]	7984643	1			T30	1		T31	183		T32	25575
bins_for_gpio_bits[14]	auto[0]	auto[1]	248161	1			T31	11		T36	3		T37	10692
bins_for_gpio_bits[14]	auto[1]	auto[0]	248343	1			T31	11		T36	3		T37	10694
bins_for_gpio_bits[14]	auto[1]	auto[1]	5516967	1			T31	146		T32	29709		T33	22882
bins_for_gpio_bits[15]	auto[0]	auto[0]	7998910	1			T30	1		T31	211		T32	26894
bins_for_gpio_bits[15]	auto[0]	auto[1]	247545	1			T31	8		T36	5		T37	10725
bins_for_gpio_bits[15]	auto[1]	auto[0]	247752	1			T31	9		T36	5		T37	10729
bins_for_gpio_bits[15]	auto[1]	auto[1]	5503907	1			T31	123		T32	28390		T33	22735
bins_for_gpio_bits[16]	auto[0]	auto[0]	8003036	1			T30	1		T31	190		T32	26470
bins_for_gpio_bits[16]	auto[0]	auto[1]	247116	1			T31	9		T36	5		T37	10711
bins_for_gpio_bits[16]	auto[1]	auto[0]	247303	1			T31	9		T36	5		T37	10712
bins_for_gpio_bits[16]	auto[1]	auto[1]	5500659	1			T31	143		T32	28814		T33	23037
bins_for_gpio_bits[17]	auto[0]	auto[0]	7996366	1			T30	1		T31	199		T32	27570
bins_for_gpio_bits[17]	auto[0]	auto[1]	247441	1			T31	9		T36	3		T37	10695
bins_for_gpio_bits[17]	auto[1]	auto[0]	247624	1			T31	9		T36	3		T37	10698
bins_for_gpio_bits[17]	auto[1]	auto[1]	5506683	1			T31	134		T32	27714		T33	21747
bins_for_gpio_bits[18]	auto[0]	auto[0]	7995931	1			T30	1		T31	191		T32	28229
bins_for_gpio_bits[18]	auto[0]	auto[1]	247646	1			T31	10		T36	5		T37	10681
bins_for_gpio_bits[18]	auto[1]	auto[0]	247839	1			T31	11		T36	5		T37	10682
bins_for_gpio_bits[18]	auto[1]	auto[1]	5506698	1			T31	139		T32	27055		T33	21525
bins_for_gpio_bits[19]	auto[0]	auto[0]	7997704	1			T30	1		T31	202		T32	28681
bins_for_gpio_bits[19]	auto[0]	auto[1]	247398	1			T31	12		T36	3		T37	10659
bins_for_gpio_bits[19]	auto[1]	auto[0]	247628	1			T31	13		T36	3		T37	10660
bins_for_gpio_bits[19]	auto[1]	auto[1]	5505384	1			T31	124		T32	26603		T33	24306
bins_for_gpio_bits[20]	auto[0]	auto[0]	8002307	1			T30	1		T31	212		T32	27973
bins_for_gpio_bits[20]	auto[0]	auto[1]	246869	1			T31	8		T36	3		T37	10528
bins_for_gpio_bits[20]	auto[1]	auto[0]	247056	1			T31	8		T36	3		T37	10531
bins_for_gpio_bits[20]	auto[1]	auto[1]	5501882	1			T31	123		T32	27311		T33	21218
bins_for_gpio_bits[21]	auto[0]	auto[0]	7996154	1			T30	1		T31	202		T32	26935
bins_for_gpio_bits[21]	auto[0]	auto[1]	247396	1			T31	7		T36	6		T37	10649
bins_for_gpio_bits[21]	auto[1]	auto[0]	247585	1			T31	8		T36	6		T37	10650
bins_for_gpio_bits[21]	auto[1]	auto[1]	5506979	1			T31	134		T32	28349		T33	22689
bins_for_gpio_bits[22]	auto[0]	auto[0]	7991418	1			T30	1		T31	211		T32	27167
bins_for_gpio_bits[22]	auto[0]	auto[1]	247188	1			T31	7		T36	2		T37	10506
bins_for_gpio_bits[22]	auto[1]	auto[0]	247420	1			T31	7		T36	2		T37	10508
bins_for_gpio_bits[22]	auto[1]	auto[1]	5512088	1			T31	126		T32	28117		T33	22880
bins_for_gpio_bits[23]	auto[0]	auto[0]	7999176	1			T30	1		T31	199		T32	29019
bins_for_gpio_bits[23]	auto[0]	auto[1]	247393	1			T31	11		T36	3		T37	10542
bins_for_gpio_bits[23]	auto[1]	auto[0]	247593	1			T31	12		T36	3		T37	10542
bins_for_gpio_bits[23]	auto[1]	auto[1]	5503952	1			T31	129		T32	26265		T33	22631
bins_for_gpio_bits[24]	auto[0]	auto[0]	7999778	1			T30	1		T31	216		T32	30302
bins_for_gpio_bits[24]	auto[0]	auto[1]	247295	1			T31	7		T36	2		T37	10655
bins_for_gpio_bits[24]	auto[1]	auto[0]	247440	1			T31	7		T36	2		T37	10656
bins_for_gpio_bits[24]	auto[1]	auto[1]	5503601	1			T31	121		T32	24982		T33	24140
bins_for_gpio_bits[25]	auto[0]	auto[0]	7994615	1			T30	1		T31	218		T32	28228
bins_for_gpio_bits[25]	auto[0]	auto[1]	247395	1			T31	4		T36	2		T37	10634
bins_for_gpio_bits[25]	auto[1]	auto[0]	247581	1			T31	4		T36	2		T37	10634
bins_for_gpio_bits[25]	auto[1]	auto[1]	5508523	1			T31	125		T32	27056		T33	24720
bins_for_gpio_bits[26]	auto[0]	auto[0]	7992961	1			T30	1		T31	211		T32	27900
bins_for_gpio_bits[26]	auto[0]	auto[1]	248165	1			T31	7		T36	3		T37	10746
bins_for_gpio_bits[26]	auto[1]	auto[0]	248368	1			T31	7		T36	3		T37	10746
bins_for_gpio_bits[26]	auto[1]	auto[1]	5508620	1			T31	126		T32	27384		T33	22362
bins_for_gpio_bits[27]	auto[0]	auto[0]	7984686	1			T30	1		T31	214		T32	25895
bins_for_gpio_bits[27]	auto[0]	auto[1]	246937	1			T31	11		T36	5		T37	10555
bins_for_gpio_bits[27]	auto[1]	auto[0]	247099	1			T31	11		T36	5		T37	10559
bins_for_gpio_bits[27]	auto[1]	auto[1]	5519392	1			T31	115		T32	29389		T33	22545
bins_for_gpio_bits[28]	auto[0]	auto[0]	7997830	1			T30	1		T31	201		T32	28411
bins_for_gpio_bits[28]	auto[0]	auto[1]	247766	1			T31	10		T36	4		T37	10664
bins_for_gpio_bits[28]	auto[1]	auto[0]	247957	1			T31	11		T36	4		T37	10665
bins_for_gpio_bits[28]	auto[1]	auto[1]	5504561	1			T31	129		T32	26873		T33	22085
bins_for_gpio_bits[29]	auto[0]	auto[0]	7995736	1			T30	1		T31	179		T32	30014
bins_for_gpio_bits[29]	auto[0]	auto[1]	247684	1			T31	10		T36	3		T37	10559
bins_for_gpio_bits[29]	auto[1]	auto[0]	247869	1			T31	11		T36	3		T37	10561
bins_for_gpio_bits[29]	auto[1]	auto[1]	5506825	1			T31	151		T32	25270		T33	22088
bins_for_gpio_bits[30]	auto[0]	auto[0]	7999605	1			T30	1		T31	190		T32	27295
bins_for_gpio_bits[30]	auto[0]	auto[1]	247826	1			T31	12		T36	4		T37	10617
bins_for_gpio_bits[30]	auto[1]	auto[0]	248041	1			T31	12		T36	4		T37	10621
bins_for_gpio_bits[30]	auto[1]	auto[1]	5502642	1			T31	137		T32	27989		T33	22520
bins_for_gpio_bits[31]	auto[0]	auto[0]	8000342	1			T30	1		T31	204		T32	27973
bins_for_gpio_bits[31]	auto[0]	auto[1]	247755	1			T31	10		T36	2		T37	10671
bins_for_gpio_bits[31]	auto[1]	auto[0]	247958	1			T31	10		T36	2		T37	10672
bins_for_gpio_bits[31]	auto[1]	auto[1]	5502059	1			T31	127		T32	27311		T33	20651