Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8182285 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6029005 |
1 |
|
|
T34 |
447 |
|
T35 |
283 |
|
T37 |
283112 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13437619 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
773671 |
1 |
|
|
T34 |
93 |
|
T35 |
39 |
|
T37 |
36516 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8167095 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6044195 |
1 |
|
|
T34 |
443 |
|
T35 |
218 |
|
T37 |
282127 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2637271 |
1 |
|
|
T34 |
246 |
|
T35 |
75 |
|
T37 |
120980 |
| auto[1] |
auto[0] |
auto[1] |
387436 |
1 |
|
|
T34 |
68 |
|
T35 |
14 |
|
T37 |
17919 |
| auto[1] |
auto[1] |
auto[0] |
2633253 |
1 |
|
|
T34 |
104 |
|
T35 |
104 |
|
T37 |
124631 |
| auto[1] |
auto[1] |
auto[1] |
386235 |
1 |
|
|
T34 |
25 |
|
T35 |
25 |
|
T37 |
18597 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8190237 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6021053 |
1 |
|
|
T34 |
704 |
|
T35 |
205 |
|
T37 |
276275 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13441387 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
769903 |
1 |
|
|
T34 |
113 |
|
T35 |
42 |
|
T37 |
36020 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8193723 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6017567 |
1 |
|
|
T34 |
556 |
|
T35 |
219 |
|
T37 |
275820 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2625137 |
1 |
|
|
T34 |
111 |
|
T35 |
78 |
|
T37 |
120587 |
| auto[1] |
auto[0] |
auto[1] |
385051 |
1 |
|
|
T34 |
28 |
|
T35 |
13 |
|
T37 |
18198 |
| auto[1] |
auto[1] |
auto[0] |
2622527 |
1 |
|
|
T34 |
332 |
|
T35 |
99 |
|
T37 |
119213 |
| auto[1] |
auto[1] |
auto[1] |
384852 |
1 |
|
|
T34 |
85 |
|
T35 |
29 |
|
T37 |
17822 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8185067 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6026223 |
1 |
|
|
T34 |
315 |
|
T35 |
323 |
|
T37 |
279574 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13443153 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
768137 |
1 |
|
|
T34 |
121 |
|
T35 |
18 |
|
T37 |
35645 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8204186 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6007104 |
1 |
|
|
T34 |
628 |
|
T35 |
89 |
|
T37 |
275762 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2618499 |
1 |
|
|
T34 |
377 |
|
T35 |
55 |
|
T37 |
119126 |
| auto[1] |
auto[0] |
auto[1] |
383862 |
1 |
|
|
T34 |
85 |
|
T35 |
14 |
|
T37 |
17501 |
| auto[1] |
auto[1] |
auto[0] |
2620468 |
1 |
|
|
T34 |
130 |
|
T35 |
16 |
|
T37 |
120991 |
| auto[1] |
auto[1] |
auto[1] |
384275 |
1 |
|
|
T34 |
36 |
|
T35 |
4 |
|
T37 |
18144 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8185045 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6026245 |
1 |
|
|
T34 |
430 |
|
T35 |
243 |
|
T37 |
274377 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13441426 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
769864 |
1 |
|
|
T34 |
104 |
|
T35 |
66 |
|
T37 |
35332 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8186265 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6025025 |
1 |
|
|
T34 |
530 |
|
T35 |
363 |
|
T37 |
272011 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2622271 |
1 |
|
|
T34 |
252 |
|
T35 |
192 |
|
T37 |
121687 |
| auto[1] |
auto[0] |
auto[1] |
384128 |
1 |
|
|
T34 |
63 |
|
T35 |
45 |
|
T37 |
18379 |
| auto[1] |
auto[1] |
auto[0] |
2632890 |
1 |
|
|
T34 |
174 |
|
T35 |
105 |
|
T37 |
114992 |
| auto[1] |
auto[1] |
auto[1] |
385736 |
1 |
|
|
T34 |
41 |
|
T35 |
21 |
|
T37 |
16953 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8158679 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6052611 |
1 |
|
|
T34 |
654 |
|
T35 |
392 |
|
T37 |
285352 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13448296 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
762994 |
1 |
|
|
T34 |
83 |
|
T35 |
53 |
|
T37 |
35909 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8232823 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
5978467 |
1 |
|
|
T34 |
488 |
|
T35 |
241 |
|
T37 |
276818 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2601185 |
1 |
|
|
T34 |
190 |
|
T35 |
54 |
|
T37 |
115153 |
| auto[1] |
auto[0] |
auto[1] |
380252 |
1 |
|
|
T34 |
35 |
|
T35 |
17 |
|
T37 |
17035 |
| auto[1] |
auto[1] |
auto[0] |
2614288 |
1 |
|
|
T34 |
215 |
|
T35 |
134 |
|
T37 |
125756 |
| auto[1] |
auto[1] |
auto[1] |
382742 |
1 |
|
|
T34 |
48 |
|
T35 |
36 |
|
T37 |
18874 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8180767 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6030523 |
1 |
|
|
T34 |
723 |
|
T35 |
199 |
|
T37 |
285894 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13439624 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
771666 |
1 |
|
|
T34 |
71 |
|
T35 |
63 |
|
T37 |
37028 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8180033 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6031257 |
1 |
|
|
T34 |
427 |
|
T35 |
329 |
|
T37 |
283996 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2625387 |
1 |
|
|
T34 |
86 |
|
T35 |
158 |
|
T37 |
123405 |
| auto[1] |
auto[0] |
auto[1] |
383951 |
1 |
|
|
T34 |
20 |
|
T35 |
41 |
|
T37 |
18454 |
| auto[1] |
auto[1] |
auto[0] |
2634204 |
1 |
|
|
T34 |
270 |
|
T35 |
108 |
|
T37 |
123563 |
| auto[1] |
auto[1] |
auto[1] |
387715 |
1 |
|
|
T34 |
51 |
|
T35 |
22 |
|
T37 |
18574 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8182799 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6028491 |
1 |
|
|
T34 |
469 |
|
T35 |
360 |
|
T37 |
277649 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13441824 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
769466 |
1 |
|
|
T34 |
133 |
|
T35 |
74 |
|
T37 |
36316 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8190130 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6021160 |
1 |
|
|
T34 |
702 |
|
T35 |
337 |
|
T37 |
281462 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2606245 |
1 |
|
|
T34 |
378 |
|
T35 |
106 |
|
T37 |
119857 |
| auto[1] |
auto[0] |
auto[1] |
381170 |
1 |
|
|
T34 |
87 |
|
T35 |
30 |
|
T37 |
17453 |
| auto[1] |
auto[1] |
auto[0] |
2645449 |
1 |
|
|
T34 |
191 |
|
T35 |
157 |
|
T37 |
125289 |
| auto[1] |
auto[1] |
auto[1] |
388296 |
1 |
|
|
T34 |
46 |
|
T35 |
44 |
|
T37 |
18863 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8180113 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6031177 |
1 |
|
|
T34 |
703 |
|
T35 |
201 |
|
T37 |
273307 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13443825 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
767465 |
1 |
|
|
T34 |
92 |
|
T35 |
49 |
|
T37 |
36170 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8208466 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6002824 |
1 |
|
|
T34 |
489 |
|
T35 |
222 |
|
T37 |
281709 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2614766 |
1 |
|
|
T34 |
177 |
|
T35 |
76 |
|
T37 |
124475 |
| auto[1] |
auto[0] |
auto[1] |
382868 |
1 |
|
|
T34 |
42 |
|
T35 |
24 |
|
T37 |
18509 |
| auto[1] |
auto[1] |
auto[0] |
2620593 |
1 |
|
|
T34 |
220 |
|
T35 |
97 |
|
T37 |
121064 |
| auto[1] |
auto[1] |
auto[1] |
384597 |
1 |
|
|
T34 |
50 |
|
T35 |
25 |
|
T37 |
17661 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8159333 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6051957 |
1 |
|
|
T34 |
514 |
|
T35 |
365 |
|
T37 |
281587 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13441842 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
769448 |
1 |
|
|
T34 |
88 |
|
T35 |
81 |
|
T37 |
36560 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8202761 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6008529 |
1 |
|
|
T34 |
452 |
|
T35 |
404 |
|
T37 |
280556 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2616583 |
1 |
|
|
T34 |
197 |
|
T35 |
84 |
|
T37 |
119675 |
| auto[1] |
auto[0] |
auto[1] |
384766 |
1 |
|
|
T34 |
45 |
|
T35 |
21 |
|
T37 |
17884 |
| auto[1] |
auto[1] |
auto[0] |
2622498 |
1 |
|
|
T34 |
167 |
|
T35 |
239 |
|
T37 |
124321 |
| auto[1] |
auto[1] |
auto[1] |
384682 |
1 |
|
|
T34 |
43 |
|
T35 |
60 |
|
T37 |
18676 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8198930 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6012360 |
1 |
|
|
T34 |
636 |
|
T35 |
195 |
|
T37 |
277353 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13441941 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
769349 |
1 |
|
|
T34 |
126 |
|
T35 |
47 |
|
T37 |
36273 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8199184 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6012106 |
1 |
|
|
T34 |
615 |
|
T35 |
214 |
|
T37 |
278606 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2619515 |
1 |
|
|
T34 |
175 |
|
T35 |
100 |
|
T37 |
121511 |
| auto[1] |
auto[0] |
auto[1] |
383433 |
1 |
|
|
T34 |
48 |
|
T35 |
28 |
|
T37 |
18178 |
| auto[1] |
auto[1] |
auto[0] |
2623242 |
1 |
|
|
T34 |
314 |
|
T35 |
67 |
|
T37 |
120822 |
| auto[1] |
auto[1] |
auto[1] |
385916 |
1 |
|
|
T34 |
78 |
|
T35 |
19 |
|
T37 |
18095 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8197534 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6013756 |
1 |
|
|
T34 |
490 |
|
T35 |
297 |
|
T37 |
277234 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13445452 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
765838 |
1 |
|
|
T34 |
51 |
|
T35 |
57 |
|
T37 |
34471 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218236 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
5993054 |
1 |
|
|
T34 |
267 |
|
T35 |
275 |
|
T37 |
268673 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2626571 |
1 |
|
|
T34 |
141 |
|
T35 |
68 |
|
T37 |
119646 |
| auto[1] |
auto[0] |
auto[1] |
385910 |
1 |
|
|
T34 |
35 |
|
T35 |
20 |
|
T37 |
17725 |
| auto[1] |
auto[1] |
auto[0] |
2600645 |
1 |
|
|
T34 |
75 |
|
T35 |
150 |
|
T37 |
114556 |
| auto[1] |
auto[1] |
auto[1] |
379928 |
1 |
|
|
T34 |
16 |
|
T35 |
37 |
|
T37 |
16746 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8219415 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
5991875 |
1 |
|
|
T34 |
701 |
|
T35 |
150 |
|
T37 |
272585 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13440735 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
770555 |
1 |
|
|
T34 |
121 |
|
T35 |
79 |
|
T37 |
35781 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8200145 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6011145 |
1 |
|
|
T34 |
691 |
|
T35 |
370 |
|
T37 |
276222 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2630150 |
1 |
|
|
T34 |
198 |
|
T35 |
219 |
|
T37 |
122683 |
| auto[1] |
auto[0] |
auto[1] |
386390 |
1 |
|
|
T34 |
37 |
|
T35 |
55 |
|
T37 |
18254 |
| auto[1] |
auto[1] |
auto[0] |
2610440 |
1 |
|
|
T34 |
372 |
|
T35 |
72 |
|
T37 |
117758 |
| auto[1] |
auto[1] |
auto[1] |
384165 |
1 |
|
|
T34 |
84 |
|
T35 |
24 |
|
T37 |
17527 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8194400 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6016890 |
1 |
|
|
T34 |
554 |
|
T35 |
354 |
|
T37 |
281084 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13441914 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
769376 |
1 |
|
|
T34 |
124 |
|
T35 |
47 |
|
T37 |
36897 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8193698 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6017592 |
1 |
|
|
T34 |
652 |
|
T35 |
220 |
|
T37 |
284004 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2621472 |
1 |
|
|
T34 |
336 |
|
T35 |
37 |
|
T37 |
123875 |
| auto[1] |
auto[0] |
auto[1] |
383515 |
1 |
|
|
T34 |
76 |
|
T35 |
11 |
|
T37 |
18560 |
| auto[1] |
auto[1] |
auto[0] |
2626744 |
1 |
|
|
T34 |
192 |
|
T35 |
136 |
|
T37 |
123232 |
| auto[1] |
auto[1] |
auto[1] |
385861 |
1 |
|
|
T34 |
48 |
|
T35 |
36 |
|
T37 |
18337 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8182160 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6029130 |
1 |
|
|
T34 |
584 |
|
T35 |
372 |
|
T37 |
278767 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13435368 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
775922 |
1 |
|
|
T34 |
135 |
|
T35 |
55 |
|
T37 |
38080 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8137821 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6073469 |
1 |
|
|
T34 |
711 |
|
T35 |
242 |
|
T37 |
291038 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2660839 |
1 |
|
|
T34 |
292 |
|
T35 |
65 |
|
T37 |
124020 |
| auto[1] |
auto[0] |
auto[1] |
389863 |
1 |
|
|
T34 |
64 |
|
T35 |
21 |
|
T37 |
18766 |
| auto[1] |
auto[1] |
auto[0] |
2636708 |
1 |
|
|
T34 |
284 |
|
T35 |
122 |
|
T37 |
128938 |
| auto[1] |
auto[1] |
auto[1] |
386059 |
1 |
|
|
T34 |
71 |
|
T35 |
34 |
|
T37 |
19314 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8209935 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6001355 |
1 |
|
|
T34 |
621 |
|
T35 |
308 |
|
T37 |
276733 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13441282 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
770008 |
1 |
|
|
T34 |
87 |
|
T35 |
35 |
|
T37 |
35750 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8188317 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6022973 |
1 |
|
|
T34 |
482 |
|
T35 |
186 |
|
T37 |
275487 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2640784 |
1 |
|
|
T34 |
180 |
|
T35 |
87 |
|
T37 |
117757 |
| auto[1] |
auto[0] |
auto[1] |
388033 |
1 |
|
|
T34 |
38 |
|
T35 |
20 |
|
T37 |
17587 |
| auto[1] |
auto[1] |
auto[0] |
2612181 |
1 |
|
|
T34 |
215 |
|
T35 |
64 |
|
T37 |
121980 |
| auto[1] |
auto[1] |
auto[1] |
381975 |
1 |
|
|
T34 |
49 |
|
T35 |
15 |
|
T37 |
18163 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8214773 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
5996517 |
1 |
|
|
T34 |
513 |
|
T35 |
225 |
|
T37 |
287488 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13437074 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
774216 |
1 |
|
|
T34 |
87 |
|
T35 |
82 |
|
T37 |
36576 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8163832 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6047458 |
1 |
|
|
T34 |
458 |
|
T35 |
417 |
|
T37 |
281214 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2637122 |
1 |
|
|
T34 |
260 |
|
T35 |
203 |
|
T37 |
117436 |
| auto[1] |
auto[0] |
auto[1] |
387039 |
1 |
|
|
T34 |
61 |
|
T35 |
49 |
|
T37 |
17261 |
| auto[1] |
auto[1] |
auto[0] |
2636120 |
1 |
|
|
T34 |
111 |
|
T35 |
132 |
|
T37 |
127202 |
| auto[1] |
auto[1] |
auto[1] |
387177 |
1 |
|
|
T34 |
26 |
|
T35 |
33 |
|
T37 |
19315 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8197672 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6013618 |
1 |
|
|
T34 |
596 |
|
T35 |
409 |
|
T37 |
285858 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13441671 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
769619 |
1 |
|
|
T34 |
126 |
|
T35 |
61 |
|
T37 |
35440 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205573 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6005717 |
1 |
|
|
T34 |
695 |
|
T35 |
330 |
|
T37 |
274686 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2629885 |
1 |
|
|
T34 |
269 |
|
T35 |
62 |
|
T37 |
117371 |
| auto[1] |
auto[0] |
auto[1] |
386043 |
1 |
|
|
T34 |
50 |
|
T35 |
11 |
|
T37 |
17093 |
| auto[1] |
auto[1] |
auto[0] |
2606213 |
1 |
|
|
T34 |
300 |
|
T35 |
207 |
|
T37 |
121875 |
| auto[1] |
auto[1] |
auto[1] |
383576 |
1 |
|
|
T34 |
76 |
|
T35 |
50 |
|
T37 |
18347 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8162211 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6049079 |
1 |
|
|
T34 |
501 |
|
T35 |
388 |
|
T37 |
279742 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13447732 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
763558 |
1 |
|
|
T34 |
110 |
|
T35 |
50 |
|
T37 |
36060 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8237761 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
5973529 |
1 |
|
|
T34 |
618 |
|
T35 |
210 |
|
T37 |
276016 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2596733 |
1 |
|
|
T34 |
191 |
|
T35 |
49 |
|
T37 |
123268 |
| auto[1] |
auto[0] |
auto[1] |
379717 |
1 |
|
|
T34 |
41 |
|
T35 |
12 |
|
T37 |
18500 |
| auto[1] |
auto[1] |
auto[0] |
2613238 |
1 |
|
|
T34 |
317 |
|
T35 |
111 |
|
T37 |
116688 |
| auto[1] |
auto[1] |
auto[1] |
383841 |
1 |
|
|
T34 |
69 |
|
T35 |
38 |
|
T37 |
17560 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218380 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
5992910 |
1 |
|
|
T34 |
728 |
|
T35 |
320 |
|
T37 |
284994 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13439899 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
771391 |
1 |
|
|
T34 |
73 |
|
T35 |
61 |
|
T37 |
37524 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8181298 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6029992 |
1 |
|
|
T34 |
382 |
|
T35 |
310 |
|
T37 |
287189 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2648655 |
1 |
|
|
T34 |
110 |
|
T35 |
126 |
|
T37 |
124165 |
| auto[1] |
auto[0] |
auto[1] |
388498 |
1 |
|
|
T34 |
24 |
|
T35 |
31 |
|
T37 |
18755 |
| auto[1] |
auto[1] |
auto[0] |
2609946 |
1 |
|
|
T34 |
199 |
|
T35 |
123 |
|
T37 |
125500 |
| auto[1] |
auto[1] |
auto[1] |
382893 |
1 |
|
|
T34 |
49 |
|
T35 |
30 |
|
T37 |
18769 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8163829 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6047461 |
1 |
|
|
T34 |
609 |
|
T35 |
234 |
|
T37 |
287992 |