Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13439803 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
771487 |
1 |
|
|
T34 |
109 |
|
T35 |
83 |
|
T37 |
36438 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8175261 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
| auto[1] |
6036029 |
1 |
|
|
T34 |
567 |
|
T35 |
406 |
|
T37 |
280694 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2622707 |
1 |
|
|
T34 |
165 |
|
T35 |
194 |
|
T37 |
119973 |
| auto[1] |
auto[0] |
auto[1] |
384600 |
1 |
|
|
T34 |
38 |
|
T35 |
54 |
|
T37 |
17725 |
| auto[1] |
auto[1] |
auto[0] |
2641835 |
1 |
|
|
T34 |
293 |
|
T35 |
129 |
|
T37 |
124283 |
| auto[1] |
auto[1] |
auto[1] |
386887 |
1 |
|
|
T34 |
71 |
|
T35 |
29 |
|
T37 |
18713 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |