Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8180113 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
auto[1] |
6031177 |
1 |
|
|
T34 |
703 |
|
T35 |
201 |
|
T37 |
273307 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11703856 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
auto[1] |
2507434 |
1 |
|
|
T34 |
309 |
|
T35 |
125 |
|
T37 |
104803 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8204565 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
auto[1] |
6006725 |
1 |
|
|
T34 |
627 |
|
T35 |
231 |
|
T37 |
277536 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1732170 |
1 |
|
|
T34 |
121 |
|
T35 |
77 |
|
T37 |
87474 |
auto[1] |
auto[0] |
auto[1] |
1245474 |
1 |
|
|
T34 |
145 |
|
T35 |
103 |
|
T37 |
53511 |
auto[1] |
auto[1] |
auto[0] |
1767121 |
1 |
|
|
T34 |
197 |
|
T35 |
29 |
|
T37 |
85259 |
auto[1] |
auto[1] |
auto[1] |
1261960 |
1 |
|
|
T34 |
164 |
|
T35 |
22 |
|
T37 |
51292 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |