Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8162211 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
auto[1] |
6049079 |
1 |
|
|
T34 |
501 |
|
T35 |
388 |
|
T37 |
279742 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11679939 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
auto[1] |
2531351 |
1 |
|
|
T34 |
335 |
|
T35 |
139 |
|
T37 |
106005 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8148708 |
1 |
|
|
T30 |
1 |
|
T31 |
273 |
|
T32 |
55284 |
auto[1] |
6062582 |
1 |
|
|
T34 |
604 |
|
T35 |
296 |
|
T37 |
280876 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1757892 |
1 |
|
|
T34 |
140 |
|
T35 |
59 |
|
T37 |
87238 |
auto[1] |
auto[0] |
auto[1] |
1269304 |
1 |
|
|
T34 |
171 |
|
T35 |
50 |
|
T37 |
51991 |
auto[1] |
auto[1] |
auto[0] |
1773339 |
1 |
|
|
T34 |
129 |
|
T35 |
98 |
|
T37 |
87633 |
auto[1] |
auto[1] |
auto[1] |
1262047 |
1 |
|
|
T34 |
164 |
|
T35 |
89 |
|
T37 |
54014 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |