Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
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T763 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1236812640 Jul 25 04:43:43 PM PDT 24 Jul 25 04:43:44 PM PDT 24 11944474 ps
T52 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3024663087 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:03 PM PDT 24 808453183 ps
T764 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.425635260 Jul 25 04:43:38 PM PDT 24 Jul 25 04:43:40 PM PDT 24 24663366 ps
T765 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.134063503 Jul 25 04:43:58 PM PDT 24 Jul 25 04:44:00 PM PDT 24 87672814 ps
T766 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2206830386 Jul 25 04:43:57 PM PDT 24 Jul 25 04:43:58 PM PDT 24 66362621 ps
T767 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3736203389 Jul 25 04:43:53 PM PDT 24 Jul 25 04:43:54 PM PDT 24 25455901 ps
T93 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4275980723 Jul 25 04:43:56 PM PDT 24 Jul 25 04:43:57 PM PDT 24 16585341 ps
T768 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3521325432 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:02 PM PDT 24 21993704 ps
T769 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1713745339 Jul 25 04:43:47 PM PDT 24 Jul 25 04:43:47 PM PDT 24 24319871 ps
T770 /workspace/coverage/cover_reg_top/22.gpio_intr_test.656054863 Jul 25 04:44:31 PM PDT 24 Jul 25 04:44:31 PM PDT 24 23302910 ps
T82 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3073233331 Jul 25 04:43:55 PM PDT 24 Jul 25 04:43:56 PM PDT 24 86430209 ps
T50 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2678050147 Jul 25 04:43:57 PM PDT 24 Jul 25 04:43:59 PM PDT 24 421724801 ps
T771 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4063255930 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:50 PM PDT 24 19572588 ps
T772 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2624506268 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:00 PM PDT 24 38087934 ps
T773 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1368923941 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:56 PM PDT 24 425780576 ps
T94 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3407227983 Jul 25 04:43:53 PM PDT 24 Jul 25 04:43:54 PM PDT 24 113620805 ps
T774 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1317570466 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:02 PM PDT 24 237278304 ps
T775 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.4226100845 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:01 PM PDT 24 407918650 ps
T776 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1041097175 Jul 25 04:44:03 PM PDT 24 Jul 25 04:44:04 PM PDT 24 152501772 ps
T777 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.246494833 Jul 25 04:43:56 PM PDT 24 Jul 25 04:43:57 PM PDT 24 166484857 ps
T778 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.582053596 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:55 PM PDT 24 93731603 ps
T779 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2492943558 Jul 25 04:44:43 PM PDT 24 Jul 25 04:44:44 PM PDT 24 17327604 ps
T780 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2432804374 Jul 25 04:43:57 PM PDT 24 Jul 25 04:43:58 PM PDT 24 30953780 ps
T781 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1404205527 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:55 PM PDT 24 20250516 ps
T782 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3843709874 Jul 25 04:43:50 PM PDT 24 Jul 25 04:43:51 PM PDT 24 231410021 ps
T783 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3729746156 Jul 25 04:43:56 PM PDT 24 Jul 25 04:43:57 PM PDT 24 59311555 ps
T784 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1118988857 Jul 25 04:43:50 PM PDT 24 Jul 25 04:43:51 PM PDT 24 85410660 ps
T83 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1377549080 Jul 25 04:44:22 PM PDT 24 Jul 25 04:44:22 PM PDT 24 45891838 ps
T785 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2410726691 Jul 25 04:43:57 PM PDT 24 Jul 25 04:43:57 PM PDT 24 12337668 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4230372438 Jul 25 04:43:43 PM PDT 24 Jul 25 04:43:44 PM PDT 24 36620058 ps
T787 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2596578924 Jul 25 04:43:58 PM PDT 24 Jul 25 04:43:59 PM PDT 24 13875743 ps
T788 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2758159273 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:55 PM PDT 24 83594737 ps
T789 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.946781875 Jul 25 04:44:18 PM PDT 24 Jul 25 04:44:25 PM PDT 24 40552307 ps
T790 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1837099339 Jul 25 04:43:55 PM PDT 24 Jul 25 04:43:57 PM PDT 24 25393898 ps
T791 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.222237130 Jul 25 04:43:47 PM PDT 24 Jul 25 04:43:48 PM PDT 24 147277209 ps
T792 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3872295093 Jul 25 04:43:52 PM PDT 24 Jul 25 04:43:53 PM PDT 24 108492055 ps
T793 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3909392985 Jul 25 04:43:56 PM PDT 24 Jul 25 04:43:56 PM PDT 24 12822103 ps
T794 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3769581785 Jul 25 04:43:50 PM PDT 24 Jul 25 04:43:51 PM PDT 24 86026616 ps
T795 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1477988468 Jul 25 04:43:57 PM PDT 24 Jul 25 04:43:58 PM PDT 24 134444120 ps
T796 /workspace/coverage/cover_reg_top/42.gpio_intr_test.744962208 Jul 25 04:44:02 PM PDT 24 Jul 25 04:44:03 PM PDT 24 19790692 ps
T797 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1620119740 Jul 25 04:43:53 PM PDT 24 Jul 25 04:43:54 PM PDT 24 191940842 ps
T798 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.886453841 Jul 25 04:43:43 PM PDT 24 Jul 25 04:43:45 PM PDT 24 61134493 ps
T799 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1030939273 Jul 25 04:43:56 PM PDT 24 Jul 25 04:43:57 PM PDT 24 24257958 ps
T800 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2269839791 Jul 25 04:43:27 PM PDT 24 Jul 25 04:43:29 PM PDT 24 97940331 ps
T801 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.673457949 Jul 25 04:43:52 PM PDT 24 Jul 25 04:43:53 PM PDT 24 32020494 ps
T802 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3731165072 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:00 PM PDT 24 17615613 ps
T803 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2646241260 Jul 25 04:44:02 PM PDT 24 Jul 25 04:44:03 PM PDT 24 19086114 ps
T804 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1028657964 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:03 PM PDT 24 409724773 ps
T805 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1187492486 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:02 PM PDT 24 53668200 ps
T806 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.359450952 Jul 25 04:43:38 PM PDT 24 Jul 25 04:43:39 PM PDT 24 62857135 ps
T807 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.712087497 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:01 PM PDT 24 18373581 ps
T808 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.435503738 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:45 PM PDT 24 14727902 ps
T809 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2848629879 Jul 25 04:43:57 PM PDT 24 Jul 25 04:43:59 PM PDT 24 25768597 ps
T810 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4129716087 Jul 25 04:44:09 PM PDT 24 Jul 25 04:44:10 PM PDT 24 16047632 ps
T811 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1083866192 Jul 25 04:43:53 PM PDT 24 Jul 25 04:43:54 PM PDT 24 77192988 ps
T812 /workspace/coverage/cover_reg_top/24.gpio_intr_test.33307228 Jul 25 04:44:28 PM PDT 24 Jul 25 04:44:29 PM PDT 24 33308764 ps
T813 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1202348311 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:00 PM PDT 24 37121896 ps
T814 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1310593058 Jul 25 04:43:57 PM PDT 24 Jul 25 04:43:58 PM PDT 24 328844199 ps
T84 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3581344565 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:52 PM PDT 24 81275202 ps
T85 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.626920286 Jul 25 04:44:19 PM PDT 24 Jul 25 04:44:20 PM PDT 24 16690758 ps
T815 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1770586689 Jul 25 04:43:47 PM PDT 24 Jul 25 04:43:47 PM PDT 24 47750678 ps
T816 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1669644344 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:00 PM PDT 24 35142410 ps
T817 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1471332244 Jul 25 04:44:04 PM PDT 24 Jul 25 04:44:05 PM PDT 24 17515843 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3470288867 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:00 PM PDT 24 71339767 ps
T819 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3054183445 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:57 PM PDT 24 90628022 ps
T86 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3958998840 Jul 25 04:44:29 PM PDT 24 Jul 25 04:44:30 PM PDT 24 16458171 ps
T820 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2821342180 Jul 25 04:43:44 PM PDT 24 Jul 25 04:43:48 PM PDT 24 629294292 ps
T87 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3942023189 Jul 25 04:43:48 PM PDT 24 Jul 25 04:43:49 PM PDT 24 61388274 ps
T821 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3377626883 Jul 25 04:43:50 PM PDT 24 Jul 25 04:43:53 PM PDT 24 118285705 ps
T822 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2811278588 Jul 25 04:43:56 PM PDT 24 Jul 25 04:43:59 PM PDT 24 97491897 ps
T823 /workspace/coverage/cover_reg_top/18.gpio_intr_test.860342032 Jul 25 04:44:30 PM PDT 24 Jul 25 04:44:31 PM PDT 24 35470554 ps
T824 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3941220597 Jul 25 04:43:58 PM PDT 24 Jul 25 04:43:59 PM PDT 24 127730338 ps
T825 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3686543173 Jul 25 04:44:04 PM PDT 24 Jul 25 04:44:05 PM PDT 24 21984080 ps
T826 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3753818678 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:55 PM PDT 24 24383108 ps
T827 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3254613540 Jul 25 04:43:56 PM PDT 24 Jul 25 04:43:57 PM PDT 24 16219651 ps
T828 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2025003946 Jul 25 04:43:49 PM PDT 24 Jul 25 04:43:51 PM PDT 24 416021959 ps
T88 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3826209636 Jul 25 04:43:54 PM PDT 24 Jul 25 04:43:55 PM PDT 24 13558675 ps
T89 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3147018323 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:00 PM PDT 24 21670915 ps
T829 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.159117465 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:05 PM PDT 24 84155031 ps
T830 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2404934170 Jul 25 04:44:05 PM PDT 24 Jul 25 04:44:05 PM PDT 24 77910385 ps
T831 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1815679958 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:01 PM PDT 24 64724511 ps
T832 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.114605220 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:06 PM PDT 24 37206465 ps
T833 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1220464661 Jul 25 04:44:14 PM PDT 24 Jul 25 04:44:15 PM PDT 24 40056572 ps
T834 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3128336476 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:01 PM PDT 24 110641315 ps
T835 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1273078786 Jul 25 04:44:38 PM PDT 24 Jul 25 04:44:40 PM PDT 24 29609770 ps
T836 /workspace/coverage/cover_reg_top/11.gpio_intr_test.304130361 Jul 25 04:43:58 PM PDT 24 Jul 25 04:43:59 PM PDT 24 25183026 ps
T837 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1046049253 Jul 25 04:44:13 PM PDT 24 Jul 25 04:44:16 PM PDT 24 250110197 ps
T838 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3469229326 Jul 25 04:43:58 PM PDT 24 Jul 25 04:43:59 PM PDT 24 46021379 ps
T839 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4008779476 Jul 25 04:43:57 PM PDT 24 Jul 25 04:43:59 PM PDT 24 173080849 ps
T840 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3667740650 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:02 PM PDT 24 33090509 ps
T841 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3681336023 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:02 PM PDT 24 49850879 ps
T842 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.708690377 Jul 25 04:43:56 PM PDT 24 Jul 25 04:44:00 PM PDT 24 260101422 ps
T843 /workspace/coverage/cover_reg_top/7.gpio_intr_test.197879869 Jul 25 04:43:48 PM PDT 24 Jul 25 04:43:49 PM PDT 24 44744082 ps
T844 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3446240817 Jul 25 04:44:08 PM PDT 24 Jul 25 04:44:10 PM PDT 24 35236998 ps
T845 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4276774262 Jul 25 04:44:27 PM PDT 24 Jul 25 04:44:29 PM PDT 24 41920112 ps
T846 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1004237150 Jul 25 04:44:09 PM PDT 24 Jul 25 04:44:11 PM PDT 24 73595241 ps
T847 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.743502963 Jul 25 04:44:26 PM PDT 24 Jul 25 04:44:27 PM PDT 24 94982618 ps
T848 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2293940560 Jul 25 04:44:44 PM PDT 24 Jul 25 04:44:45 PM PDT 24 493723157 ps
T849 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4152847303 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:02 PM PDT 24 237985894 ps
T850 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1213483501 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:03 PM PDT 24 195811392 ps
T851 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1560024584 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:05 PM PDT 24 134009846 ps
T852 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.171619683 Jul 25 04:44:35 PM PDT 24 Jul 25 04:44:36 PM PDT 24 144993330 ps
T853 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1806264123 Jul 25 04:44:32 PM PDT 24 Jul 25 04:44:33 PM PDT 24 794216330 ps
T854 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1416183314 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:01 PM PDT 24 283939314 ps
T855 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.189442773 Jul 25 04:44:08 PM PDT 24 Jul 25 04:44:10 PM PDT 24 229555179 ps
T856 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.109767409 Jul 25 04:44:16 PM PDT 24 Jul 25 04:44:17 PM PDT 24 96967924 ps
T857 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4177308547 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:03 PM PDT 24 570623793 ps
T858 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.825970285 Jul 25 04:44:09 PM PDT 24 Jul 25 04:44:10 PM PDT 24 128459197 ps
T859 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2086767292 Jul 25 04:44:29 PM PDT 24 Jul 25 04:44:30 PM PDT 24 50561494 ps
T860 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3833174781 Jul 25 04:44:47 PM PDT 24 Jul 25 04:44:48 PM PDT 24 35504292 ps
T861 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2742212570 Jul 25 04:44:08 PM PDT 24 Jul 25 04:44:09 PM PDT 24 159134452 ps
T862 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2342437792 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:01 PM PDT 24 108317944 ps
T863 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.224350001 Jul 25 04:44:48 PM PDT 24 Jul 25 04:44:49 PM PDT 24 36479030 ps
T864 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3028684672 Jul 25 04:44:42 PM PDT 24 Jul 25 04:44:44 PM PDT 24 60124283 ps
T865 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3602777565 Jul 25 04:44:57 PM PDT 24 Jul 25 04:44:58 PM PDT 24 152338882 ps
T866 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1597073850 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:02 PM PDT 24 70964322 ps
T867 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1897947578 Jul 25 04:43:57 PM PDT 24 Jul 25 04:43:58 PM PDT 24 40414950 ps
T868 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.983534552 Jul 25 04:44:47 PM PDT 24 Jul 25 04:44:48 PM PDT 24 74132740 ps
T869 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.282187660 Jul 25 04:44:42 PM PDT 24 Jul 25 04:44:43 PM PDT 24 76042603 ps
T870 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1852610116 Jul 25 04:44:02 PM PDT 24 Jul 25 04:44:04 PM PDT 24 73039177 ps
T871 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2304305753 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:00 PM PDT 24 38514898 ps
T872 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.520338423 Jul 25 04:44:16 PM PDT 24 Jul 25 04:44:17 PM PDT 24 50367989 ps
T873 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1792820746 Jul 25 04:44:30 PM PDT 24 Jul 25 04:44:32 PM PDT 24 50490088 ps
T874 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2710890103 Jul 25 04:44:39 PM PDT 24 Jul 25 04:44:40 PM PDT 24 67279145 ps
T875 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1950648963 Jul 25 04:44:21 PM PDT 24 Jul 25 04:44:23 PM PDT 24 143985144 ps
T876 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2531709654 Jul 25 04:44:02 PM PDT 24 Jul 25 04:44:04 PM PDT 24 723563096 ps
T877 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.391047274 Jul 25 04:44:05 PM PDT 24 Jul 25 04:44:07 PM PDT 24 75379373 ps
T878 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.76555359 Jul 25 04:44:09 PM PDT 24 Jul 25 04:44:10 PM PDT 24 207471350 ps
T879 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1990372738 Jul 25 04:44:35 PM PDT 24 Jul 25 04:44:36 PM PDT 24 179622029 ps
T880 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3068787696 Jul 25 04:44:34 PM PDT 24 Jul 25 04:44:36 PM PDT 24 59538320 ps
T881 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3011887802 Jul 25 04:44:40 PM PDT 24 Jul 25 04:44:41 PM PDT 24 49767557 ps
T882 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3914106508 Jul 25 04:44:28 PM PDT 24 Jul 25 04:44:30 PM PDT 24 144017032 ps
T883 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2222764616 Jul 25 04:44:31 PM PDT 24 Jul 25 04:44:32 PM PDT 24 190511022 ps
T884 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.159214968 Jul 25 04:44:22 PM PDT 24 Jul 25 04:44:23 PM PDT 24 48613200 ps
T885 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1302289032 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:02 PM PDT 24 45231528 ps
T886 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1888454599 Jul 25 04:44:27 PM PDT 24 Jul 25 04:44:29 PM PDT 24 39150772 ps
T887 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3485491903 Jul 25 04:44:36 PM PDT 24 Jul 25 04:44:37 PM PDT 24 61561644 ps
T888 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3362036796 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:03 PM PDT 24 50048933 ps
T889 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3843815179 Jul 25 04:44:12 PM PDT 24 Jul 25 04:44:14 PM PDT 24 282504874 ps
T890 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2475597358 Jul 25 04:44:40 PM PDT 24 Jul 25 04:44:41 PM PDT 24 23967383 ps
T891 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1607852077 Jul 25 04:44:03 PM PDT 24 Jul 25 04:44:04 PM PDT 24 212810525 ps
T892 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.204821715 Jul 25 04:44:29 PM PDT 24 Jul 25 04:44:31 PM PDT 24 84044752 ps
T893 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1855473390 Jul 25 04:44:36 PM PDT 24 Jul 25 04:44:37 PM PDT 24 714609341 ps
T894 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.811005787 Jul 25 04:44:48 PM PDT 24 Jul 25 04:44:48 PM PDT 24 30497034 ps
T895 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1606560111 Jul 25 04:44:04 PM PDT 24 Jul 25 04:44:11 PM PDT 24 75751919 ps
T896 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3777982028 Jul 25 04:43:59 PM PDT 24 Jul 25 04:44:01 PM PDT 24 42512265 ps
T897 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.557164815 Jul 25 04:44:02 PM PDT 24 Jul 25 04:44:04 PM PDT 24 205842763 ps
T898 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3381327054 Jul 25 04:44:02 PM PDT 24 Jul 25 04:44:03 PM PDT 24 150892703 ps
T899 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2950914464 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:02 PM PDT 24 142030772 ps
T900 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3476901354 Jul 25 04:44:38 PM PDT 24 Jul 25 04:44:39 PM PDT 24 418462360 ps
T901 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.673430871 Jul 25 04:44:03 PM PDT 24 Jul 25 04:44:04 PM PDT 24 54865139 ps
T902 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1031433962 Jul 25 04:44:38 PM PDT 24 Jul 25 04:44:40 PM PDT 24 539930936 ps
T903 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2265779270 Jul 25 04:44:15 PM PDT 24 Jul 25 04:44:16 PM PDT 24 58608480 ps
T904 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2636479853 Jul 25 04:44:04 PM PDT 24 Jul 25 04:44:06 PM PDT 24 41410434 ps
T905 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.65458813 Jul 25 04:44:03 PM PDT 24 Jul 25 04:44:04 PM PDT 24 682983078 ps
T906 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3586700776 Jul 25 04:44:10 PM PDT 24 Jul 25 04:44:11 PM PDT 24 52704588 ps
T907 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1093737032 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:03 PM PDT 24 186177455 ps
T908 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1122945920 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:02 PM PDT 24 128478992 ps
T909 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3222669889 Jul 25 04:44:36 PM PDT 24 Jul 25 04:44:38 PM PDT 24 281482265 ps
T910 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3388422368 Jul 25 04:44:04 PM PDT 24 Jul 25 04:44:05 PM PDT 24 244250481 ps
T911 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2069822887 Jul 25 04:44:20 PM PDT 24 Jul 25 04:44:21 PM PDT 24 32864062 ps
T912 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249728021 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:01 PM PDT 24 52446151 ps
T913 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3884303815 Jul 25 04:44:35 PM PDT 24 Jul 25 04:44:36 PM PDT 24 38706596 ps
T914 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4134883060 Jul 25 04:44:53 PM PDT 24 Jul 25 04:44:55 PM PDT 24 22414144 ps
T915 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4062871162 Jul 25 04:44:05 PM PDT 24 Jul 25 04:44:07 PM PDT 24 49999598 ps
T916 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1812919152 Jul 25 04:44:29 PM PDT 24 Jul 25 04:44:30 PM PDT 24 56089912 ps
T917 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1057450704 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:02 PM PDT 24 98461586 ps
T918 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.304111115 Jul 25 04:44:00 PM PDT 24 Jul 25 04:44:02 PM PDT 24 76311900 ps
T919 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3587161132 Jul 25 04:44:26 PM PDT 24 Jul 25 04:44:28 PM PDT 24 315586771 ps
T920 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3527464960 Jul 25 04:44:15 PM PDT 24 Jul 25 04:44:16 PM PDT 24 21834940 ps
T921 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3931498768 Jul 25 04:44:16 PM PDT 24 Jul 25 04:44:18 PM PDT 24 54879490 ps
T922 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2943626210 Jul 25 04:44:41 PM PDT 24 Jul 25 04:44:42 PM PDT 24 190261219 ps
T923 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3813099356 Jul 25 04:43:58 PM PDT 24 Jul 25 04:44:00 PM PDT 24 97410011 ps
T924 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.193938928 Jul 25 04:44:45 PM PDT 24 Jul 25 04:44:46 PM PDT 24 39414878 ps
T925 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3354943972 Jul 25 04:44:08 PM PDT 24 Jul 25 04:44:09 PM PDT 24 85987480 ps
T926 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2884010051 Jul 25 04:44:20 PM PDT 24 Jul 25 04:44:21 PM PDT 24 84610041 ps
T927 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3346470468 Jul 25 04:44:30 PM PDT 24 Jul 25 04:44:31 PM PDT 24 536164732 ps
T928 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2125923739 Jul 25 04:44:03 PM PDT 24 Jul 25 04:44:04 PM PDT 24 187624676 ps
T929 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4239501828 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:03 PM PDT 24 61551799 ps
T930 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.32285517 Jul 25 04:44:32 PM PDT 24 Jul 25 04:44:34 PM PDT 24 55777034 ps
T931 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2274852674 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:03 PM PDT 24 231116816 ps
T932 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1299247854 Jul 25 04:44:10 PM PDT 24 Jul 25 04:44:11 PM PDT 24 400699747 ps
T933 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.834552250 Jul 25 04:44:02 PM PDT 24 Jul 25 04:44:04 PM PDT 24 292458163 ps
T934 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.978237392 Jul 25 04:44:02 PM PDT 24 Jul 25 04:44:04 PM PDT 24 71419711 ps
T935 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2507724740 Jul 25 04:43:58 PM PDT 24 Jul 25 04:44:00 PM PDT 24 45278753 ps
T936 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1040887642 Jul 25 04:44:46 PM PDT 24 Jul 25 04:44:47 PM PDT 24 314729034 ps
T937 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.227537981 Jul 25 04:44:33 PM PDT 24 Jul 25 04:44:34 PM PDT 24 110305892 ps
T938 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2439036438 Jul 25 04:44:05 PM PDT 24 Jul 25 04:44:07 PM PDT 24 290694470 ps
T939 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1529557035 Jul 25 04:44:41 PM PDT 24 Jul 25 04:44:43 PM PDT 24 53969963 ps
T940 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.801536884 Jul 25 04:44:44 PM PDT 24 Jul 25 04:44:45 PM PDT 24 64121122 ps
T941 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.275710957 Jul 25 04:44:01 PM PDT 24 Jul 25 04:44:03 PM PDT 24 321081150 ps
T942 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3993838371 Jul 25 04:44:02 PM PDT 24 Jul 25 04:44:04 PM PDT 24 126905742 ps
T943 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1272820777 Jul 25 04:44:33 PM PDT 24 Jul 25 04:44:34 PM PDT 24 126196418 ps

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2088141848
Short name T37
Test name
Test status
Simulation time 247865760330 ps
CPU time 1812.49 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 05:17:45 PM PDT 24
Peak memory 198732 kb
Host smart-32c04f09-d42b-43dc-9c26-2069eebfb5c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2088141848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2088141848
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.992684612
Short name T98
Test name
Test status
Simulation time 84918227 ps
CPU time 3.25 seconds
Started Jul 25 04:47:19 PM PDT 24
Finished Jul 25 04:47:22 PM PDT 24
Peak memory 198608 kb
Host smart-848414d9-29e3-45f5-83af-533606be311c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992684612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.992684612
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1587192090
Short name T30
Test name
Test status
Simulation time 49682021 ps
CPU time 0.59 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 194560 kb
Host smart-9f18c5ab-3aa6-4105-9af1-10cababc52e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587192090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1587192090
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3086123120
Short name T44
Test name
Test status
Simulation time 200921815 ps
CPU time 1.48 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 198292 kb
Host smart-4cb1b788-818e-4a01-8798-ce150c0d2f9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086123120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3086123120
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.630794467
Short name T81
Test name
Test status
Simulation time 24953659 ps
CPU time 0.58 seconds
Started Jul 25 04:44:09 PM PDT 24
Finished Jul 25 04:44:10 PM PDT 24
Peak memory 195172 kb
Host smart-7d446497-5406-4e16-8050-73de09566120
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630794467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.630794467
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3926863965
Short name T1
Test name
Test status
Simulation time 333419522 ps
CPU time 4.53 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:43 PM PDT 24
Peak memory 198488 kb
Host smart-8e5df94f-b716-4351-95b6-6f71f03f8b8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926863965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3926863965
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2827816372
Short name T74
Test name
Test status
Simulation time 48843755 ps
CPU time 0.71 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 196140 kb
Host smart-8226d4ae-d3a3-495c-9db1-de0aaefbbfae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827816372 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2827816372
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1014613547
Short name T47
Test name
Test status
Simulation time 2520374851 ps
CPU time 1.59 seconds
Started Jul 25 04:46:19 PM PDT 24
Finished Jul 25 04:46:21 PM PDT 24
Peak memory 215612 kb
Host smart-b1d92f22-3bc3-4c7d-91c1-1e9700892038
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014613547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1014613547
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2203481662
Short name T97
Test name
Test status
Simulation time 75075792 ps
CPU time 1.21 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 198308 kb
Host smart-5659ba78-85f9-4ca0-86f5-21fa754ab9d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203481662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2203481662
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2758159273
Short name T788
Test name
Test status
Simulation time 83594737 ps
CPU time 1.14 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 198316 kb
Host smart-c57f03e4-e26a-49f0-8a94-80f8d3466a73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758159273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2758159273
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2269839791
Short name T800
Test name
Test status
Simulation time 97940331 ps
CPU time 0.79 seconds
Started Jul 25 04:43:27 PM PDT 24
Finished Jul 25 04:43:29 PM PDT 24
Peak memory 196840 kb
Host smart-4a0ea989-4fb4-41d4-85a2-b4f213c049d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269839791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2269839791
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2821342180
Short name T820
Test name
Test status
Simulation time 629294292 ps
CPU time 3.42 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:48 PM PDT 24
Peak memory 198260 kb
Host smart-2ba656ef-1173-4a85-9710-79588872d305
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821342180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2821342180
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4063255930
Short name T771
Test name
Test status
Simulation time 19572588 ps
CPU time 0.62 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:50 PM PDT 24
Peak memory 195468 kb
Host smart-070fc1cc-c4c7-4c61-8f58-01b3c442c218
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063255930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4063255930
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1579474328
Short name T760
Test name
Test status
Simulation time 27630495 ps
CPU time 0.71 seconds
Started Jul 25 04:43:48 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 198060 kb
Host smart-27f8b4b4-119b-4eae-8b3e-00d8f48e7a1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579474328 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1579474328
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3942023189
Short name T87
Test name
Test status
Simulation time 61388274 ps
CPU time 0.66 seconds
Started Jul 25 04:43:48 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 195856 kb
Host smart-d1eb7270-8930-4313-9b7d-b6df7c44d081
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942023189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3942023189
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.148615532
Short name T728
Test name
Test status
Simulation time 12783583 ps
CPU time 0.59 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 194644 kb
Host smart-c629d26b-556b-46ea-84a8-0f59363585df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148615532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.148615532
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4230372438
Short name T786
Test name
Test status
Simulation time 36620058 ps
CPU time 0.86 seconds
Started Jul 25 04:43:43 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 196472 kb
Host smart-754a95c4-179f-43db-a5b9-ad19d968de3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230372438 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.4230372438
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.855652800
Short name T725
Test name
Test status
Simulation time 157128548 ps
CPU time 2.1 seconds
Started Jul 25 04:43:53 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 198240 kb
Host smart-be27885e-ccab-49d7-9009-5ae19309ae51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855652800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.855652800
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2025003946
Short name T828
Test name
Test status
Simulation time 416021959 ps
CPU time 0.87 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:51 PM PDT 24
Peak memory 197980 kb
Host smart-97c35e80-a440-4eb0-89be-03bdb9cfc20a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025003946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2025003946
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.435503738
Short name T808
Test name
Test status
Simulation time 14727902 ps
CPU time 0.66 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 194620 kb
Host smart-fb54bafb-144f-445f-8d4c-22dcfa24d6dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435503738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.435503738
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.708690377
Short name T842
Test name
Test status
Simulation time 260101422 ps
CPU time 3.13 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 197404 kb
Host smart-589f413d-edab-4e54-96b3-dfb11bb6836d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708690377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.708690377
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3084561442
Short name T73
Test name
Test status
Simulation time 16005224 ps
CPU time 0.63 seconds
Started Jul 25 04:43:36 PM PDT 24
Finished Jul 25 04:43:37 PM PDT 24
Peak memory 195568 kb
Host smart-74c63c0e-27c6-4553-922a-8dcdaadbab1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084561442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3084561442
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3703720043
Short name T736
Test name
Test status
Simulation time 212995633 ps
CPU time 0.88 seconds
Started Jul 25 04:43:41 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 198168 kb
Host smart-1f228cc1-3926-4667-8e3c-214159b9e01c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703720043 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3703720043
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1236812640
Short name T763
Test name
Test status
Simulation time 11944474 ps
CPU time 0.61 seconds
Started Jul 25 04:43:43 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 194852 kb
Host smart-889d93ac-50d4-47fc-9c57-0365ada8e559
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236812640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1236812640
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2325226920
Short name T737
Test name
Test status
Simulation time 44226264 ps
CPU time 0.65 seconds
Started Jul 25 04:43:25 PM PDT 24
Finished Jul 25 04:43:26 PM PDT 24
Peak memory 194064 kb
Host smart-efd23ded-cfba-48a3-be33-3f5f1bb4298d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325226920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2325226920
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.359450952
Short name T806
Test name
Test status
Simulation time 62857135 ps
CPU time 0.63 seconds
Started Jul 25 04:43:38 PM PDT 24
Finished Jul 25 04:43:39 PM PDT 24
Peak memory 194940 kb
Host smart-4022c4ed-0746-4ff1-a282-dac37e51f94d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359450952 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.359450952
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.425635260
Short name T764
Test name
Test status
Simulation time 24663366 ps
CPU time 1.16 seconds
Started Jul 25 04:43:38 PM PDT 24
Finished Jul 25 04:43:40 PM PDT 24
Peak memory 198288 kb
Host smart-ba4a5442-9f7e-4702-ae78-49efb5c3b50f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425635260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.425635260
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1118988857
Short name T784
Test name
Test status
Simulation time 85410660 ps
CPU time 0.88 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:51 PM PDT 24
Peak memory 197496 kb
Host smart-14a32c9c-aae9-451e-aaad-0fb8b7485c2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118988857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1118988857
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.755303018
Short name T735
Test name
Test status
Simulation time 20524340 ps
CPU time 0.75 seconds
Started Jul 25 04:43:43 PM PDT 24
Finished Jul 25 04:43:44 PM PDT 24
Peak memory 198188 kb
Host smart-ee8aa48f-b950-49b3-b802-f2a2a80dc1fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755303018 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.755303018
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2410726691
Short name T785
Test name
Test status
Simulation time 12337668 ps
CPU time 0.57 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 194592 kb
Host smart-469ac86a-b12a-47c6-8493-37e57b429a72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410726691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2410726691
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3063463306
Short name T727
Test name
Test status
Simulation time 13170608 ps
CPU time 0.58 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 194592 kb
Host smart-37e5d614-e609-4e93-886a-d9aa738fb0ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063463306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3063463306
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1083866192
Short name T811
Test name
Test status
Simulation time 77192988 ps
CPU time 0.83 seconds
Started Jul 25 04:43:53 PM PDT 24
Finished Jul 25 04:43:54 PM PDT 24
Peak memory 196652 kb
Host smart-2601dd88-f004-477b-b115-6c4e3fdc0f2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083866192 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1083866192
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4148507893
Short name T761
Test name
Test status
Simulation time 270723835 ps
CPU time 2.68 seconds
Started Jul 25 04:43:53 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 198288 kb
Host smart-cf4b8478-77d9-4c78-b951-ce7c0aa1b537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148507893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4148507893
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2678050147
Short name T50
Test name
Test status
Simulation time 421724801 ps
CPU time 1.12 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 198324 kb
Host smart-aebf6938-18d7-4a29-a902-fb26044600b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678050147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2678050147
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.125616918
Short name T748
Test name
Test status
Simulation time 313680205 ps
CPU time 0.94 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 198108 kb
Host smart-f86b31fc-a174-4d59-a8ed-a38c29fbfcd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125616918 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.125616918
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.304130361
Short name T836
Test name
Test status
Simulation time 25183026 ps
CPU time 0.59 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 194628 kb
Host smart-8beb382a-bc50-4851-96ae-9ceae3660215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304130361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.304130361
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1373897618
Short name T92
Test name
Test status
Simulation time 154562040 ps
CPU time 0.82 seconds
Started Jul 25 04:43:55 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 196620 kb
Host smart-90cd4480-e209-4e7c-a938-2ca06546e257
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373897618 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1373897618
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1028657964
Short name T804
Test name
Test status
Simulation time 409724773 ps
CPU time 2.16 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 198320 kb
Host smart-d8e178e6-12dc-47ab-9a7d-9ef4c14f4154
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028657964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1028657964
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.946781875
Short name T789
Test name
Test status
Simulation time 40552307 ps
CPU time 1.84 seconds
Started Jul 25 04:44:18 PM PDT 24
Finished Jul 25 04:44:25 PM PDT 24
Peak memory 198284 kb
Host smart-9f55b30d-5f2b-45e8-8475-8667aeefd488
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946781875 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.946781875
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1707451211
Short name T75
Test name
Test status
Simulation time 46211539 ps
CPU time 0.58 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 195000 kb
Host smart-a57ab687-803a-46e3-93a4-8b32b861b2ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707451211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1707451211
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1837099339
Short name T790
Test name
Test status
Simulation time 25393898 ps
CPU time 0.59 seconds
Started Jul 25 04:43:55 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 194680 kb
Host smart-41938b12-2c17-469c-9270-1cc44f30a94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837099339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1837099339
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3753818678
Short name T826
Test name
Test status
Simulation time 24383108 ps
CPU time 1.25 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 198288 kb
Host smart-73bb2620-1496-45fd-8222-973132c95c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753818678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3753818678
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3941220597
Short name T824
Test name
Test status
Simulation time 127730338 ps
CPU time 1.09 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 198272 kb
Host smart-4dbb10c5-02df-4ae5-a16e-adb8ed340b98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941220597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3941220597
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1200384856
Short name T714
Test name
Test status
Simulation time 165895992 ps
CPU time 0.67 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 198064 kb
Host smart-996f6447-f731-4c87-8df6-8e2e82e48114
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200384856 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1200384856
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.712087497
Short name T807
Test name
Test status
Simulation time 18373581 ps
CPU time 0.55 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 194864 kb
Host smart-4dadee45-693b-43f1-9716-808595d28ff9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712087497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.712087497
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2889365401
Short name T756
Test name
Test status
Simulation time 14944325 ps
CPU time 0.59 seconds
Started Jul 25 04:43:52 PM PDT 24
Finished Jul 25 04:43:53 PM PDT 24
Peak memory 193964 kb
Host smart-8539d3d8-af8b-4b70-831e-94c65251530d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889365401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2889365401
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1030939273
Short name T799
Test name
Test status
Simulation time 24257958 ps
CPU time 0.65 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 194708 kb
Host smart-5c30e94d-1e33-48c7-acc1-07d285b47e48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030939273 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1030939273
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2848629879
Short name T809
Test name
Test status
Simulation time 25768597 ps
CPU time 1.27 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 198136 kb
Host smart-014d7d05-0dfc-4a31-9a7c-c296b1bf43ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848629879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2848629879
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.582053596
Short name T778
Test name
Test status
Simulation time 93731603 ps
CPU time 1.31 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 198300 kb
Host smart-46c39476-1bf2-4be8-8415-003ab6107997
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582053596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.582053596
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1982205090
Short name T744
Test name
Test status
Simulation time 28169540 ps
CPU time 0.78 seconds
Started Jul 25 04:44:29 PM PDT 24
Finished Jul 25 04:44:34 PM PDT 24
Peak memory 198204 kb
Host smart-16d50cbc-3b29-4991-9559-5a6c073c5b3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982205090 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1982205090
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.7652038
Short name T752
Test name
Test status
Simulation time 11473376 ps
CPU time 0.58 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 193548 kb
Host smart-04e0f390-6520-4672-b4c6-d9da72fb3f81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7652038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ
=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_c
sr_rw.7652038
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4129716087
Short name T810
Test name
Test status
Simulation time 16047632 ps
CPU time 0.58 seconds
Started Jul 25 04:44:09 PM PDT 24
Finished Jul 25 04:44:10 PM PDT 24
Peak memory 194612 kb
Host smart-172eebfb-c5d7-4a65-862b-580df08e56e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129716087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4129716087
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.4275980723
Short name T93
Test name
Test status
Simulation time 16585341 ps
CPU time 0.65 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 195168 kb
Host smart-5d5ab1e0-63fd-40de-8b02-6f8cf2c6d40d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275980723 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.4275980723
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2811278588
Short name T822
Test name
Test status
Simulation time 97491897 ps
CPU time 2.58 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 198296 kb
Host smart-01eeed49-662a-449d-84f0-df39918bb0a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811278588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2811278588
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1310593058
Short name T814
Test name
Test status
Simulation time 328844199 ps
CPU time 1.14 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 198240 kb
Host smart-261f54db-9d51-4c19-ac8b-89f59ac029c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310593058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1310593058
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1775337876
Short name T716
Test name
Test status
Simulation time 232911239 ps
CPU time 1.07 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 198184 kb
Host smart-0c0a2e47-1c07-453d-8e34-656237531d7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775337876 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1775337876
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3958998840
Short name T86
Test name
Test status
Simulation time 16458171 ps
CPU time 0.59 seconds
Started Jul 25 04:44:29 PM PDT 24
Finished Jul 25 04:44:30 PM PDT 24
Peak memory 194544 kb
Host smart-7e8956a4-07ac-4a11-bb57-f6f8214ec4dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958998840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3958998840
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.357808760
Short name T741
Test name
Test status
Simulation time 25710289 ps
CPU time 0.59 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 194628 kb
Host smart-e984902a-ded7-4bb1-894e-f1806e5a9477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357808760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.357808760
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2646241260
Short name T803
Test name
Test status
Simulation time 19086114 ps
CPU time 0.65 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 194724 kb
Host smart-7ec86fc4-f00b-437d-b1a2-02c8978fc33b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646241260 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2646241260
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.114605220
Short name T832
Test name
Test status
Simulation time 37206465 ps
CPU time 1.83 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:06 PM PDT 24
Peak memory 198264 kb
Host smart-ae70c435-c3ed-41aa-b8ba-9233b2e6b678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114605220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.114605220
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.4226100845
Short name T775
Test name
Test status
Simulation time 407918650 ps
CPU time 1.4 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 198292 kb
Host smart-8a90f494-732f-4e30-8df5-4ff5da99ab38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226100845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.4226100845
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1197508385
Short name T746
Test name
Test status
Simulation time 20528626 ps
CPU time 1.04 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 198164 kb
Host smart-e335ffd9-e8c5-4604-a5ea-bef238f3ebd7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197508385 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1197508385
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1471332244
Short name T817
Test name
Test status
Simulation time 17515843 ps
CPU time 0.58 seconds
Started Jul 25 04:44:04 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 195004 kb
Host smart-c3f01050-790e-4d70-9a1a-e19c6cfba0a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471332244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1471332244
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3638077228
Short name T755
Test name
Test status
Simulation time 24497373 ps
CPU time 0.58 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 194608 kb
Host smart-fe5c9d61-44b3-4113-95e1-fdfbf420ea31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638077228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3638077228
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2343641677
Short name T72
Test name
Test status
Simulation time 237936482 ps
CPU time 0.82 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 197284 kb
Host smart-baf933c8-08c2-4fa1-93ed-fc53201c6fe5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343641677 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2343641677
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1046049253
Short name T837
Test name
Test status
Simulation time 250110197 ps
CPU time 3.07 seconds
Started Jul 25 04:44:13 PM PDT 24
Finished Jul 25 04:44:16 PM PDT 24
Peak memory 198292 kb
Host smart-a236ad40-30a1-407e-91ec-97a315e1ebf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046049253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1046049253
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3016268136
Short name T42
Test name
Test status
Simulation time 92658121 ps
CPU time 0.82 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 197188 kb
Host smart-5b3aeafc-9b7b-45e9-9f44-3790ee08d837
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016268136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3016268136
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2206830386
Short name T766
Test name
Test status
Simulation time 66362621 ps
CPU time 1.06 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 198340 kb
Host smart-dd9ee68e-2c5f-44a3-b38e-7fbd375adb34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206830386 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2206830386
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1377549080
Short name T83
Test name
Test status
Simulation time 45891838 ps
CPU time 0.58 seconds
Started Jul 25 04:44:22 PM PDT 24
Finished Jul 25 04:44:22 PM PDT 24
Peak memory 195200 kb
Host smart-697250fa-bed2-4859-ad33-a3cf814eb85a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377549080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1377549080
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2112187760
Short name T751
Test name
Test status
Simulation time 15994946 ps
CPU time 0.6 seconds
Started Jul 25 04:44:03 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 193976 kb
Host smart-092d729f-2dd6-42d0-9b08-a21ab31ac8a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112187760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2112187760
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3002544559
Short name T91
Test name
Test status
Simulation time 35490197 ps
CPU time 0.88 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:08 PM PDT 24
Peak memory 197368 kb
Host smart-f21afe3d-480b-49ec-a7e6-cee7868e3550
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002544559 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3002544559
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2165903426
Short name T757
Test name
Test status
Simulation time 323568936 ps
CPU time 1.77 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 198296 kb
Host smart-3a8d4f95-ebff-4d49-b503-1531e4cd921d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165903426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2165903426
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.265296519
Short name T43
Test name
Test status
Simulation time 121023935 ps
CPU time 1.41 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 198276 kb
Host smart-5184f924-ce12-4d97-80c0-bcb6a5da5c90
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265296519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.265296519
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3469229326
Short name T838
Test name
Test status
Simulation time 46021379 ps
CPU time 1.14 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 198412 kb
Host smart-f6a87821-2a58-4418-b3f3-6df8f916934c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469229326 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3469229326
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.626920286
Short name T85
Test name
Test status
Simulation time 16690758 ps
CPU time 0.57 seconds
Started Jul 25 04:44:19 PM PDT 24
Finished Jul 25 04:44:20 PM PDT 24
Peak memory 194848 kb
Host smart-89a045ac-0fc9-40ba-ad3b-2d2f7897c768
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626920286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.626920286
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.860342032
Short name T823
Test name
Test status
Simulation time 35470554 ps
CPU time 0.64 seconds
Started Jul 25 04:44:30 PM PDT 24
Finished Jul 25 04:44:31 PM PDT 24
Peak memory 194060 kb
Host smart-19db979a-0636-4914-933f-832252bec60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860342032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.860342032
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.500199626
Short name T90
Test name
Test status
Simulation time 33731697 ps
CPU time 0.79 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 196448 kb
Host smart-0ebda7a1-957e-4887-968e-b52a831aa882
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500199626 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.500199626
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.315426944
Short name T719
Test name
Test status
Simulation time 128588252 ps
CPU time 2.56 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 198300 kb
Host smart-2f6d2245-d6fa-4aa6-9408-f9005d5e9c98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315426944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.315426944
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2310217545
Short name T49
Test name
Test status
Simulation time 86953336 ps
CPU time 0.88 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 198100 kb
Host smart-a37faef1-26ac-4c93-a8aa-528f81f8483e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310217545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2310217545
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1220464661
Short name T833
Test name
Test status
Simulation time 40056572 ps
CPU time 0.76 seconds
Started Jul 25 04:44:14 PM PDT 24
Finished Jul 25 04:44:15 PM PDT 24
Peak memory 198168 kb
Host smart-9e031ed1-4937-4c58-9d36-6bf89ea76ce5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220464661 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1220464661
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3826209636
Short name T88
Test name
Test status
Simulation time 13558675 ps
CPU time 0.57 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 193400 kb
Host smart-b167d202-c456-4051-b493-f09a445b2831
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826209636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3826209636
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2011855036
Short name T721
Test name
Test status
Simulation time 23505028 ps
CPU time 0.59 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 194584 kb
Host smart-edad767f-1429-48a9-a959-608e79ae24be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011855036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2011855036
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2404934170
Short name T830
Test name
Test status
Simulation time 77910385 ps
CPU time 0.7 seconds
Started Jul 25 04:44:05 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 195252 kb
Host smart-b23384aa-a96b-4ac5-8848-2e91f05e33ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404934170 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2404934170
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.134063503
Short name T765
Test name
Test status
Simulation time 87672814 ps
CPU time 2.46 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 198268 kb
Host smart-b79d0210-242b-47e2-bfe8-94724c8a2fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134063503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.134063503
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3024663087
Short name T52
Test name
Test status
Simulation time 808453183 ps
CPU time 1.14 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 197928 kb
Host smart-7d2b8f5b-a1a5-411a-9766-6ff4cf706908
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024663087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3024663087
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3565119460
Short name T79
Test name
Test status
Simulation time 38587680 ps
CPU time 0.96 seconds
Started Jul 25 04:43:41 PM PDT 24
Finished Jul 25 04:43:42 PM PDT 24
Peak memory 196644 kb
Host smart-6d599c08-b515-4ca5-8796-9ccc4bf02885
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565119460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3565119460
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3843709874
Short name T782
Test name
Test status
Simulation time 231410021 ps
CPU time 1.47 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:51 PM PDT 24
Peak memory 197488 kb
Host smart-c334de57-9e29-49a2-a594-554f1c124c7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843709874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3843709874
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2679749494
Short name T95
Test name
Test status
Simulation time 16951879 ps
CPU time 0.62 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 194592 kb
Host smart-1f255ccf-6f4c-43d4-a842-d8c7403a3e82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679749494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2679749494
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1620119740
Short name T797
Test name
Test status
Simulation time 191940842 ps
CPU time 0.81 seconds
Started Jul 25 04:43:53 PM PDT 24
Finished Jul 25 04:43:54 PM PDT 24
Peak memory 198196 kb
Host smart-86e55635-244c-443f-bd53-2e07477278e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620119740 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1620119740
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1713745339
Short name T769
Test name
Test status
Simulation time 24319871 ps
CPU time 0.61 seconds
Started Jul 25 04:43:47 PM PDT 24
Finished Jul 25 04:43:47 PM PDT 24
Peak memory 194864 kb
Host smart-7e8d8c15-376f-4d90-b02e-a222b96cb20d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713745339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1713745339
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1770586689
Short name T815
Test name
Test status
Simulation time 47750678 ps
CPU time 0.59 seconds
Started Jul 25 04:43:47 PM PDT 24
Finished Jul 25 04:43:47 PM PDT 24
Peak memory 193956 kb
Host smart-1e32b675-52a3-4dfd-881d-0acb186b8658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770586689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1770586689
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1400927389
Short name T76
Test name
Test status
Simulation time 52386773 ps
CPU time 0.77 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 196408 kb
Host smart-f62ad81d-0b57-4add-846e-2793759935cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400927389 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1400927389
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.673457949
Short name T801
Test name
Test status
Simulation time 32020494 ps
CPU time 1.59 seconds
Started Jul 25 04:43:52 PM PDT 24
Finished Jul 25 04:43:53 PM PDT 24
Peak memory 198276 kb
Host smart-c23103f2-e8bb-4284-8b1d-425304f76bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673457949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.673457949
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.699556885
Short name T41
Test name
Test status
Simulation time 133216364 ps
CPU time 1.04 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 198320 kb
Host smart-887fc47e-9d02-407b-b7b8-037042dded48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699556885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.699556885
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3521325432
Short name T768
Test name
Test status
Simulation time 21993704 ps
CPU time 0.56 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 193928 kb
Host smart-16a929b9-3c1f-4bbd-bd28-49cd19a83436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521325432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3521325432
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.571296125
Short name T734
Test name
Test status
Simulation time 43053061 ps
CPU time 0.57 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 193952 kb
Host smart-474dcfae-9d49-4d68-8a6f-53092191dae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571296125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.571296125
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.656054863
Short name T770
Test name
Test status
Simulation time 23302910 ps
CPU time 0.58 seconds
Started Jul 25 04:44:31 PM PDT 24
Finished Jul 25 04:44:31 PM PDT 24
Peak memory 194008 kb
Host smart-f28edf0d-736b-4695-9705-d073a0ee214f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656054863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.656054863
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1404351283
Short name T729
Test name
Test status
Simulation time 16209293 ps
CPU time 0.59 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 194696 kb
Host smart-d7f0e14e-0b54-4ceb-ab90-8a3570c59e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404351283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1404351283
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.33307228
Short name T812
Test name
Test status
Simulation time 33308764 ps
CPU time 0.58 seconds
Started Jul 25 04:44:28 PM PDT 24
Finished Jul 25 04:44:29 PM PDT 24
Peak memory 194016 kb
Host smart-8cc550d6-b42f-4474-9a03-5373fd455514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.33307228
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.448068355
Short name T723
Test name
Test status
Simulation time 39397743 ps
CPU time 0.58 seconds
Started Jul 25 04:44:43 PM PDT 24
Finished Jul 25 04:44:54 PM PDT 24
Peak memory 193996 kb
Host smart-8a5ce3df-ed26-4c1f-93de-2a178f2f2910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448068355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.448068355
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3905677483
Short name T742
Test name
Test status
Simulation time 42918231 ps
CPU time 0.6 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 194688 kb
Host smart-a6fc251d-2e14-4ab5-b76e-c4243025d65c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905677483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3905677483
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1766579699
Short name T732
Test name
Test status
Simulation time 29004667 ps
CPU time 0.6 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 194748 kb
Host smart-829aeeb4-e1a2-415d-9d73-040adfbd4dfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766579699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1766579699
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2596578924
Short name T787
Test name
Test status
Simulation time 13875743 ps
CPU time 0.58 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 194644 kb
Host smart-bab0851a-d579-468c-8e15-5ecfa5482a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596578924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2596578924
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1187492486
Short name T805
Test name
Test status
Simulation time 53668200 ps
CPU time 0.6 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 193988 kb
Host smart-135a830b-504b-464e-bb8c-37b3d9c653a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187492486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1187492486
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3470288867
Short name T818
Test name
Test status
Simulation time 71339767 ps
CPU time 0.69 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 195628 kb
Host smart-62d7bd11-a7da-433d-bd52-ff3918749296
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470288867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3470288867
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3581344565
Short name T84
Test name
Test status
Simulation time 81275202 ps
CPU time 2.91 seconds
Started Jul 25 04:43:49 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 197420 kb
Host smart-b68a6751-fbcc-4889-b29e-a945f3e0bcbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581344565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3581344565
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2513899931
Short name T759
Test name
Test status
Simulation time 40783887 ps
CPU time 0.61 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 194652 kb
Host smart-b298c9a1-ea39-418e-9824-405fbcc4e6c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513899931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2513899931
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3091584480
Short name T715
Test name
Test status
Simulation time 37726177 ps
CPU time 0.72 seconds
Started Jul 25 04:44:04 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 198096 kb
Host smart-ea9a3aa0-b378-4cd6-b051-a9c32fd05823
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091584480 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3091584480
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2890558571
Short name T96
Test name
Test status
Simulation time 14833052 ps
CPU time 0.62 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 195084 kb
Host smart-73509b75-b456-4908-9d4f-d0f474472de7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890558571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2890558571
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2730396951
Short name T720
Test name
Test status
Simulation time 66112166 ps
CPU time 0.59 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 194652 kb
Host smart-a9dd7406-a871-4174-8b8b-0c5a33d478dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730396951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2730396951
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.246494833
Short name T777
Test name
Test status
Simulation time 166484857 ps
CPU time 0.85 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 196608 kb
Host smart-d238087e-488b-4a1a-ac4e-e7598791cf79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246494833 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.246494833
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3377626883
Short name T821
Test name
Test status
Simulation time 118285705 ps
CPU time 2.24 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:53 PM PDT 24
Peak memory 198240 kb
Host smart-ae925469-39f5-471e-9bc8-d4b9f046eab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377626883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3377626883
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1815679958
Short name T831
Test name
Test status
Simulation time 64724511 ps
CPU time 0.57 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 193992 kb
Host smart-4fdabb39-60b0-48d1-8c4b-0a183fb612a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815679958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1815679958
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3356400192
Short name T726
Test name
Test status
Simulation time 24286675 ps
CPU time 0.59 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 194708 kb
Host smart-6d683276-b2b4-4c2d-b1b9-d417e2f9fd69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356400192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3356400192
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1017159999
Short name T731
Test name
Test status
Simulation time 55985943 ps
CPU time 0.62 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 194056 kb
Host smart-db5402d1-0eb1-435c-aa5f-df7bc88a9556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017159999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1017159999
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2492943558
Short name T779
Test name
Test status
Simulation time 17327604 ps
CPU time 0.61 seconds
Started Jul 25 04:44:43 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 193960 kb
Host smart-d83af619-c641-4806-969b-5a8fc6736df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492943558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2492943558
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1202348311
Short name T813
Test name
Test status
Simulation time 37121896 ps
CPU time 0.56 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 193972 kb
Host smart-e3060c21-11cb-4b5c-8c82-684f07b549f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202348311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1202348311
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.4292979554
Short name T758
Test name
Test status
Simulation time 23992820 ps
CPU time 0.63 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 194048 kb
Host smart-e6784e36-5fbe-4836-ab43-046f374317f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292979554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.4292979554
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3731165072
Short name T802
Test name
Test status
Simulation time 17615613 ps
CPU time 0.6 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 193928 kb
Host smart-c907580b-fdeb-49ad-9f7a-1063863b6fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731165072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3731165072
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3681336023
Short name T841
Test name
Test status
Simulation time 49850879 ps
CPU time 0.59 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 194028 kb
Host smart-5295f836-c717-4155-8547-0934e344c0a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681336023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3681336023
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3128336476
Short name T834
Test name
Test status
Simulation time 110641315 ps
CPU time 0.59 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 193996 kb
Host smart-faee28c5-73e3-4755-8060-f3bfecc32591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128336476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3128336476
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2624506268
Short name T772
Test name
Test status
Simulation time 38087934 ps
CPU time 0.6 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 194084 kb
Host smart-387c2a73-84f3-4d80-a4a0-e93b1e10d221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624506268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2624506268
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3073233331
Short name T82
Test name
Test status
Simulation time 86430209 ps
CPU time 0.72 seconds
Started Jul 25 04:43:55 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 196156 kb
Host smart-3232b8a9-ec64-4cde-88d9-a7a9eb5c3767
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073233331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3073233331
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2739473767
Short name T78
Test name
Test status
Simulation time 310081436 ps
CPU time 2.89 seconds
Started Jul 25 04:43:51 PM PDT 24
Finished Jul 25 04:43:54 PM PDT 24
Peak memory 197436 kb
Host smart-490a70cf-f371-4759-81bc-e937958a9817
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739473767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2739473767
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2120294446
Short name T749
Test name
Test status
Simulation time 32405927 ps
CPU time 0.6 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 195584 kb
Host smart-e91b9dad-3c00-449b-aaa2-d6efcf8de0d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120294446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2120294446
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3901771118
Short name T745
Test name
Test status
Simulation time 35016930 ps
CPU time 0.87 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 198148 kb
Host smart-7d8a7a25-c1cb-4bdc-90af-8b60bb1444e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901771118 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3901771118
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3736203389
Short name T767
Test name
Test status
Simulation time 25455901 ps
CPU time 0.61 seconds
Started Jul 25 04:43:53 PM PDT 24
Finished Jul 25 04:43:54 PM PDT 24
Peak memory 194664 kb
Host smart-d3e9e134-27f7-413d-85ec-e8ff70a6b8ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736203389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3736203389
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1230954989
Short name T740
Test name
Test status
Simulation time 16477284 ps
CPU time 0.56 seconds
Started Jul 25 04:43:55 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 193948 kb
Host smart-865dd182-6402-427c-af16-d25a13495661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230954989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1230954989
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3769581785
Short name T794
Test name
Test status
Simulation time 86026616 ps
CPU time 0.73 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:51 PM PDT 24
Peak memory 194732 kb
Host smart-2c10356a-1c5d-4d3b-a0e8-57f858d7c41f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769581785 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3769581785
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.886453841
Short name T798
Test name
Test status
Simulation time 61134493 ps
CPU time 1.22 seconds
Started Jul 25 04:43:43 PM PDT 24
Finished Jul 25 04:43:45 PM PDT 24
Peak memory 198288 kb
Host smart-73953fbf-0523-403e-892d-9bfd1450d1ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886453841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.886453841
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4008779476
Short name T839
Test name
Test status
Simulation time 173080849 ps
CPU time 1.17 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 198356 kb
Host smart-74949352-b2ec-4319-b77a-29cdfabdb02a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008779476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.4008779476
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.4228621304
Short name T722
Test name
Test status
Simulation time 25748705 ps
CPU time 0.59 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 193940 kb
Host smart-7873c3b7-c750-46bd-9698-d701d2ae9b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228621304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.4228621304
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.930713433
Short name T738
Test name
Test status
Simulation time 14287337 ps
CPU time 0.64 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 194608 kb
Host smart-ba6a420e-1e08-43a4-ab29-de9b272b625a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930713433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.930713433
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.744962208
Short name T796
Test name
Test status
Simulation time 19790692 ps
CPU time 0.59 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 194016 kb
Host smart-e8c70537-34c7-4195-891c-b65ee1c15e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744962208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.744962208
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3686543173
Short name T825
Test name
Test status
Simulation time 21984080 ps
CPU time 0.58 seconds
Started Jul 25 04:44:04 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 194556 kb
Host smart-39936888-5ac5-4ed9-a50c-6259f0cfc273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686543173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3686543173
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.784864897
Short name T747
Test name
Test status
Simulation time 11386960 ps
CPU time 0.59 seconds
Started Jul 25 04:44:37 PM PDT 24
Finished Jul 25 04:44:38 PM PDT 24
Peak memory 194088 kb
Host smart-af29dd80-1dc4-4dda-b1cb-fa135b644a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784864897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.784864897
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1041097175
Short name T776
Test name
Test status
Simulation time 152501772 ps
CPU time 0.6 seconds
Started Jul 25 04:44:03 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 194636 kb
Host smart-1aadaf5c-a07a-401f-ab62-86a0b885ac6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041097175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1041097175
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1623026741
Short name T733
Test name
Test status
Simulation time 19642345 ps
CPU time 0.6 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:43:59 PM PDT 24
Peak memory 194012 kb
Host smart-ac6928ac-3813-4362-b3d1-289157232e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623026741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1623026741
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2023971094
Short name T717
Test name
Test status
Simulation time 15964163 ps
CPU time 0.58 seconds
Started Jul 25 04:44:07 PM PDT 24
Finished Jul 25 04:44:07 PM PDT 24
Peak memory 194020 kb
Host smart-4ac57377-55b5-4a0f-bf65-633c15deac00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023971094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2023971094
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1669644344
Short name T816
Test name
Test status
Simulation time 35142410 ps
CPU time 0.57 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 194612 kb
Host smart-9e541101-7ab0-4e30-b865-da7eabca53b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669644344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1669644344
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1414509276
Short name T724
Test name
Test status
Simulation time 18254534 ps
CPU time 0.58 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 193952 kb
Host smart-b30029f4-fee4-47b2-951c-57a9dc0af530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414509276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1414509276
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3870100284
Short name T753
Test name
Test status
Simulation time 22181281 ps
CPU time 0.66 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 197472 kb
Host smart-791b722f-f50b-4e92-804a-d937a948fe12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870100284 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3870100284
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3909392985
Short name T793
Test name
Test status
Simulation time 12822103 ps
CPU time 0.58 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 195140 kb
Host smart-0681d7bf-3ce4-430f-ad95-2753e5136746
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909392985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3909392985
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2210139637
Short name T730
Test name
Test status
Simulation time 26972248 ps
CPU time 0.6 seconds
Started Jul 25 04:43:42 PM PDT 24
Finished Jul 25 04:43:43 PM PDT 24
Peak memory 193940 kb
Host smart-97e25aaa-65c3-4ab2-b6a5-ee6fed83f1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210139637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2210139637
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3709078357
Short name T77
Test name
Test status
Simulation time 29946251 ps
CPU time 0.68 seconds
Started Jul 25 04:43:55 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 195192 kb
Host smart-247f1616-6022-4779-9337-3d3747c139f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709078357 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3709078357
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3054183445
Short name T819
Test name
Test status
Simulation time 90628022 ps
CPU time 2.6 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 198308 kb
Host smart-7c6944a0-9598-4833-b05a-19b93c74729f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054183445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3054183445
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3967459429
Short name T718
Test name
Test status
Simulation time 17722352 ps
CPU time 0.85 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 198140 kb
Host smart-963b85d8-28ed-4382-aff6-35fec9195db0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967459429 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3967459429
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1404205527
Short name T781
Test name
Test status
Simulation time 20250516 ps
CPU time 0.59 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 194928 kb
Host smart-fde61cc5-067a-446e-8f75-e6e3694e0dd1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404205527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1404205527
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3667740650
Short name T840
Test name
Test status
Simulation time 33090509 ps
CPU time 0.59 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 194612 kb
Host smart-19c6c73f-229b-41e5-b630-c19ba4144108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667740650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3667740650
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3407227983
Short name T94
Test name
Test status
Simulation time 113620805 ps
CPU time 0.72 seconds
Started Jul 25 04:43:53 PM PDT 24
Finished Jul 25 04:43:54 PM PDT 24
Peak memory 196824 kb
Host smart-d35b6ca4-85b3-4c81-8341-775b0aab5f69
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407227983 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3407227983
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1320297900
Short name T743
Test name
Test status
Simulation time 26877489 ps
CPU time 1.45 seconds
Started Jul 25 04:43:48 PM PDT 24
Finished Jul 25 04:43:50 PM PDT 24
Peak memory 198260 kb
Host smart-ef806da3-feeb-406d-bb71-5b28e9d99a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320297900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1320297900
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1368923941
Short name T773
Test name
Test status
Simulation time 425780576 ps
CPU time 1.34 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:56 PM PDT 24
Peak memory 198312 kb
Host smart-af186694-6b7e-44bf-af6c-7b4dffeb46f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368923941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1368923941
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3872295093
Short name T792
Test name
Test status
Simulation time 108492055 ps
CPU time 1.3 seconds
Started Jul 25 04:43:52 PM PDT 24
Finished Jul 25 04:43:53 PM PDT 24
Peak memory 198328 kb
Host smart-d88e052f-4d78-4fcb-b9dc-06e91aaddfae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872295093 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3872295093
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3147018323
Short name T89
Test name
Test status
Simulation time 21670915 ps
CPU time 0.58 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 194864 kb
Host smart-ad0fad08-5554-449b-89c6-f1c42df2840f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147018323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3147018323
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.197879869
Short name T843
Test name
Test status
Simulation time 44744082 ps
CPU time 0.61 seconds
Started Jul 25 04:43:48 PM PDT 24
Finished Jul 25 04:43:49 PM PDT 24
Peak memory 194036 kb
Host smart-cb0ca081-9274-4021-9a49-ea06eea9d5da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197879869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.197879869
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2432804374
Short name T780
Test name
Test status
Simulation time 30953780 ps
CPU time 0.74 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 196268 kb
Host smart-2c9c14cd-078b-4df5-86f6-e56268a334f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432804374 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2432804374
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1273078786
Short name T835
Test name
Test status
Simulation time 29609770 ps
CPU time 1.75 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:40 PM PDT 24
Peak memory 198304 kb
Host smart-c9e60af0-3df6-48df-b6d0-eeb7f7b0ec6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273078786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1273078786
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1477988468
Short name T795
Test name
Test status
Simulation time 134444120 ps
CPU time 0.81 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 197380 kb
Host smart-b46bf26b-923c-436a-bc64-c8351e16dae0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477988468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1477988468
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3322558700
Short name T739
Test name
Test status
Simulation time 29241989 ps
CPU time 0.8 seconds
Started Jul 25 04:43:51 PM PDT 24
Finished Jul 25 04:43:52 PM PDT 24
Peak memory 198076 kb
Host smart-050a17f6-dd6d-49c7-b162-46923aa53826
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322558700 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3322558700
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2213190827
Short name T80
Test name
Test status
Simulation time 13408856 ps
CPU time 0.63 seconds
Started Jul 25 04:43:50 PM PDT 24
Finished Jul 25 04:43:51 PM PDT 24
Peak memory 195396 kb
Host smart-461f49fc-79a7-4734-8ae8-b238603904a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213190827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2213190827
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3254613540
Short name T827
Test name
Test status
Simulation time 16219651 ps
CPU time 0.58 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 193936 kb
Host smart-5936164f-f60a-400d-8219-babd79d56d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254613540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3254613540
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1885595071
Short name T71
Test name
Test status
Simulation time 281778424 ps
CPU time 0.83 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:44:08 PM PDT 24
Peak memory 196424 kb
Host smart-06eaaa8c-e96a-4e06-ad7b-9a74bffcfdeb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885595071 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1885595071
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.369094705
Short name T762
Test name
Test status
Simulation time 61017918 ps
CPU time 1.28 seconds
Started Jul 25 04:43:53 PM PDT 24
Finished Jul 25 04:43:54 PM PDT 24
Peak memory 198296 kb
Host smart-56a38960-fbe0-4159-84bb-16a5fa76ef2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369094705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.369094705
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1776831139
Short name T51
Test name
Test status
Simulation time 131052567 ps
CPU time 1.5 seconds
Started Jul 25 04:43:44 PM PDT 24
Finished Jul 25 04:43:46 PM PDT 24
Peak memory 198308 kb
Host smart-97697e88-e8e8-4d16-8b35-4a10cf786a50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776831139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1776831139
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.159117465
Short name T829
Test name
Test status
Simulation time 84155031 ps
CPU time 0.89 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 198228 kb
Host smart-187c4ec4-dc53-4a7a-9442-9c9a1fe56179
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159117465 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.159117465
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4147295515
Short name T754
Test name
Test status
Simulation time 26190205 ps
CPU time 0.56 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 194692 kb
Host smart-e358cd90-d3f1-463f-85d4-3a6f10b40e79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147295515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.4147295515
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1253942821
Short name T750
Test name
Test status
Simulation time 16496852 ps
CPU time 0.61 seconds
Started Jul 25 04:43:54 PM PDT 24
Finished Jul 25 04:43:55 PM PDT 24
Peak memory 194644 kb
Host smart-abe209ac-d6ac-43b3-a69e-18d70eb0090f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253942821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1253942821
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3729746156
Short name T783
Test name
Test status
Simulation time 59311555 ps
CPU time 0.69 seconds
Started Jul 25 04:43:56 PM PDT 24
Finished Jul 25 04:43:57 PM PDT 24
Peak memory 195040 kb
Host smart-2a5890af-8604-4520-97fa-2a59e22ec8b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729746156 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3729746156
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1317570466
Short name T774
Test name
Test status
Simulation time 237278304 ps
CPU time 1.49 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 198272 kb
Host smart-5069e7f9-3b22-4263-983a-93baed79782b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317570466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1317570466
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.222237130
Short name T791
Test name
Test status
Simulation time 147277209 ps
CPU time 1.26 seconds
Started Jul 25 04:43:47 PM PDT 24
Finished Jul 25 04:43:48 PM PDT 24
Peak memory 198312 kb
Host smart-cdc3b793-ffbe-44db-9a8e-640e17d3cf31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222237130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.222237130
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1626807521
Short name T331
Test name
Test status
Simulation time 13713194 ps
CPU time 0.58 seconds
Started Jul 25 04:46:11 PM PDT 24
Finished Jul 25 04:46:11 PM PDT 24
Peak memory 194448 kb
Host smart-5ac048d6-46fd-4583-97b7-6d2573c54d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626807521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1626807521
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2983896654
Short name T673
Test name
Test status
Simulation time 38423491 ps
CPU time 0.73 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 194616 kb
Host smart-c937f82d-14fc-426e-960b-813e77ceaff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983896654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2983896654
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.336567153
Short name T586
Test name
Test status
Simulation time 126168633 ps
CPU time 5.85 seconds
Started Jul 25 04:46:09 PM PDT 24
Finished Jul 25 04:46:15 PM PDT 24
Peak memory 196680 kb
Host smart-d3a61866-7da7-4669-8aa4-d43c307bfe32
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336567153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.336567153
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2887342368
Short name T369
Test name
Test status
Simulation time 66506913 ps
CPU time 0.76 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:28 PM PDT 24
Peak memory 196384 kb
Host smart-ceab396f-6562-448b-ad21-ad1714451c1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887342368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2887342368
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1405310813
Short name T124
Test name
Test status
Simulation time 278318129 ps
CPU time 1.17 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:28 PM PDT 24
Peak memory 196960 kb
Host smart-0df91792-bb2d-4bfe-b0f2-ee0fe530ccb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405310813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1405310813
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1170065412
Short name T644
Test name
Test status
Simulation time 304901201 ps
CPU time 2.94 seconds
Started Jul 25 04:46:19 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 198520 kb
Host smart-3671b5c4-6f7e-47e1-985e-73f263dc26c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170065412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1170065412
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1862052173
Short name T145
Test name
Test status
Simulation time 291611992 ps
CPU time 2.44 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 198524 kb
Host smart-b61710a3-c1cd-4023-a76d-2bc66aa6992f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862052173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1862052173
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1572201930
Short name T408
Test name
Test status
Simulation time 181844844 ps
CPU time 0.99 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 196540 kb
Host smart-10d65232-22a4-427a-aefd-dfb5c4915dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572201930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1572201930
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2911048870
Short name T660
Test name
Test status
Simulation time 125577290 ps
CPU time 1.28 seconds
Started Jul 25 04:46:19 PM PDT 24
Finished Jul 25 04:46:20 PM PDT 24
Peak memory 196200 kb
Host smart-7376b888-5a10-407d-9821-4d4b2d4cc8a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911048870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2911048870
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1448590985
Short name T170
Test name
Test status
Simulation time 386612737 ps
CPU time 3.28 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 198448 kb
Host smart-fc5cfb9f-f1f4-4dd6-8802-72a7164e174c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448590985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1448590985
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.3370529224
Short name T535
Test name
Test status
Simulation time 129679353 ps
CPU time 1.23 seconds
Started Jul 25 04:46:06 PM PDT 24
Finished Jul 25 04:46:07 PM PDT 24
Peak memory 197228 kb
Host smart-95210d28-788b-4553-9119-38b92266f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370529224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3370529224
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1705305468
Short name T687
Test name
Test status
Simulation time 152765138 ps
CPU time 1.34 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 198452 kb
Host smart-937f9144-e5eb-4fa9-9a74-ab5ed5a80bb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705305468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1705305468
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2029606273
Short name T17
Test name
Test status
Simulation time 7667708253 ps
CPU time 101.26 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:48:06 PM PDT 24
Peak memory 198620 kb
Host smart-34ec7c16-dee3-4396-ae44-d0bfcc3e2651
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029606273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2029606273
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3943112779
Short name T70
Test name
Test status
Simulation time 33574327052 ps
CPU time 364.7 seconds
Started Jul 25 04:46:22 PM PDT 24
Finished Jul 25 04:52:27 PM PDT 24
Peak memory 198676 kb
Host smart-73a71515-a4c0-4bfa-8d95-866ee7253bf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3943112779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3943112779
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.135713496
Short name T333
Test name
Test status
Simulation time 14960436 ps
CPU time 0.57 seconds
Started Jul 25 04:46:22 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 194372 kb
Host smart-64d6bdf2-313f-4416-bfc9-4ef17be56f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135713496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.135713496
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.509454096
Short name T394
Test name
Test status
Simulation time 198966700 ps
CPU time 0.87 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 196760 kb
Host smart-96c258f3-321c-4b67-89e0-83e3f156f87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509454096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.509454096
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2077920209
Short name T509
Test name
Test status
Simulation time 5469233488 ps
CPU time 17.26 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:46:43 PM PDT 24
Peak memory 197200 kb
Host smart-41e98d15-04b4-47fd-9577-a8300c4be537
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077920209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2077920209
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1551581942
Short name T693
Test name
Test status
Simulation time 138997608 ps
CPU time 1.03 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 197028 kb
Host smart-69938a80-775f-45ab-ac8d-5a4d45e90ffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551581942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1551581942
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2239308502
Short name T594
Test name
Test status
Simulation time 1539508039 ps
CPU time 1.26 seconds
Started Jul 25 04:46:29 PM PDT 24
Finished Jul 25 04:46:31 PM PDT 24
Peak memory 197720 kb
Host smart-71a530e9-e1ca-4496-b076-f6dd76484b55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239308502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2239308502
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3857004052
Short name T38
Test name
Test status
Simulation time 66377069 ps
CPU time 2.4 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:34 PM PDT 24
Peak memory 198416 kb
Host smart-71ee2f07-1446-4014-9c83-f8fcc96bac7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857004052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3857004052
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2343341769
Short name T267
Test name
Test status
Simulation time 249522640 ps
CPU time 2.03 seconds
Started Jul 25 04:46:24 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 197656 kb
Host smart-976a1581-511b-4bc7-9b15-2000f68ddf05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343341769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2343341769
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2998297638
Short name T373
Test name
Test status
Simulation time 32077006 ps
CPU time 0.74 seconds
Started Jul 25 04:46:16 PM PDT 24
Finished Jul 25 04:46:16 PM PDT 24
Peak memory 195912 kb
Host smart-5ff9df0a-bb16-433b-bd73-1e76cfdad9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998297638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2998297638
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1522053919
Short name T59
Test name
Test status
Simulation time 42241867 ps
CPU time 1.14 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 197568 kb
Host smart-69fa4bc1-8874-4f9b-ad1f-37679bd22304
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522053919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1522053919
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3015366580
Short name T645
Test name
Test status
Simulation time 104936823 ps
CPU time 4.72 seconds
Started Jul 25 04:46:22 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 198480 kb
Host smart-339304af-3395-490a-89e0-be9012e67c83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015366580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3015366580
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1170269929
Short name T53
Test name
Test status
Simulation time 80402328 ps
CPU time 0.96 seconds
Started Jul 25 04:46:37 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 217124 kb
Host smart-2c9722c5-e723-4a48-8f12-10ebc8db10ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170269929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1170269929
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2153721478
Short name T489
Test name
Test status
Simulation time 102769845 ps
CPU time 1.04 seconds
Started Jul 25 04:46:19 PM PDT 24
Finished Jul 25 04:46:20 PM PDT 24
Peak memory 196212 kb
Host smart-c1703f34-fddd-41a1-b430-4394820d2c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153721478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2153721478
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2159184817
Short name T593
Test name
Test status
Simulation time 54884884 ps
CPU time 1.08 seconds
Started Jul 25 04:46:15 PM PDT 24
Finished Jul 25 04:46:17 PM PDT 24
Peak memory 196288 kb
Host smart-78a8716e-4ea7-4a0c-968d-0c4a1b8cb026
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159184817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2159184817
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2124210983
Short name T242
Test name
Test status
Simulation time 4602256553 ps
CPU time 118.17 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:48:19 PM PDT 24
Peak memory 198568 kb
Host smart-da4dc508-c781-42d5-aab5-90293abe8d47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124210983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2124210983
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2809441734
Short name T160
Test name
Test status
Simulation time 17483032 ps
CPU time 0.54 seconds
Started Jul 25 04:46:36 PM PDT 24
Finished Jul 25 04:46:41 PM PDT 24
Peak memory 194332 kb
Host smart-08b67b66-b05d-4d80-a370-c8116c464c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809441734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2809441734
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3800778572
Short name T554
Test name
Test status
Simulation time 96532271 ps
CPU time 0.7 seconds
Started Jul 25 04:46:23 PM PDT 24
Finished Jul 25 04:46:24 PM PDT 24
Peak memory 194612 kb
Host smart-61743fc0-439d-4fa0-9c8a-e13655cf7d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800778572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3800778572
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1615779443
Short name T606
Test name
Test status
Simulation time 1700695793 ps
CPU time 17.1 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:49 PM PDT 24
Peak memory 196716 kb
Host smart-d8a7b9a0-e3af-46c3-8c5b-807ec4513e12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615779443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1615779443
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2749460278
Short name T592
Test name
Test status
Simulation time 115176739 ps
CPU time 0.95 seconds
Started Jul 25 04:46:42 PM PDT 24
Finished Jul 25 04:46:43 PM PDT 24
Peak memory 196960 kb
Host smart-aa3796fc-4fd6-4e1a-8db4-9e11d4219865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749460278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2749460278
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2306299593
Short name T125
Test name
Test status
Simulation time 98344392 ps
CPU time 0.98 seconds
Started Jul 25 04:46:27 PM PDT 24
Finished Jul 25 04:46:28 PM PDT 24
Peak memory 197164 kb
Host smart-b4163ea9-1ea5-46c4-8e16-8dd3decb58ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306299593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2306299593
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3453781156
Short name T176
Test name
Test status
Simulation time 138514241 ps
CPU time 2.8 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 198600 kb
Host smart-a77033fd-da79-46a7-b0cc-2953c40df29a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453781156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3453781156
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2294175024
Short name T15
Test name
Test status
Simulation time 141071475 ps
CPU time 1.1 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:36 PM PDT 24
Peak memory 196700 kb
Host smart-7e04b693-3a6d-40cb-bd0b-fa9c08aa498d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294175024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2294175024
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3848612434
Short name T268
Test name
Test status
Simulation time 56040768 ps
CPU time 0.8 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 197044 kb
Host smart-5ffc9223-6ee5-449c-9df2-9942ade20177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848612434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3848612434
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2508628627
Short name T195
Test name
Test status
Simulation time 50268919 ps
CPU time 1.18 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 197352 kb
Host smart-2c7989a8-602a-4f6d-8f9c-531f5531723b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508628627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2508628627
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.935399014
Short name T433
Test name
Test status
Simulation time 1266507087 ps
CPU time 4.95 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 198420 kb
Host smart-946dc402-1200-4081-9365-4c7bbd29d004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935399014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.935399014
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1974140265
Short name T101
Test name
Test status
Simulation time 124957344 ps
CPU time 0.97 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:30 PM PDT 24
Peak memory 196252 kb
Host smart-8c64bef0-bd45-473c-a8b7-0b67388bfe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974140265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1974140265
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.375442138
Short name T439
Test name
Test status
Simulation time 53153261 ps
CPU time 0.83 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 197528 kb
Host smart-21d8c771-6ef9-411a-b578-2770c7b65a04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375442138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.375442138
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.4124613558
Short name T436
Test name
Test status
Simulation time 20670788799 ps
CPU time 133.84 seconds
Started Jul 25 04:46:50 PM PDT 24
Finished Jul 25 04:49:04 PM PDT 24
Peak memory 198548 kb
Host smart-1c84dd07-034e-4595-9edf-c67c8d098cf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124613558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.4124613558
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1902540144
Short name T67
Test name
Test status
Simulation time 1492334243275 ps
CPU time 1633.54 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 05:13:43 PM PDT 24
Peak memory 206964 kb
Host smart-2d6bd13f-8200-4826-b97a-12ae95f43dc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1902540144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1902540144
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3706612737
Short name T383
Test name
Test status
Simulation time 15914478 ps
CPU time 0.57 seconds
Started Jul 25 04:46:40 PM PDT 24
Finished Jul 25 04:46:41 PM PDT 24
Peak memory 194552 kb
Host smart-5baf3c0a-4241-4985-aceb-c628366a889a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706612737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3706612737
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2645252385
Short name T416
Test name
Test status
Simulation time 65620455 ps
CPU time 0.76 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:47:00 PM PDT 24
Peak memory 195804 kb
Host smart-d2b3b3ad-8b9f-467a-bfe6-29bfeeaf0a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645252385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2645252385
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2832277200
Short name T361
Test name
Test status
Simulation time 2115299027 ps
CPU time 26.87 seconds
Started Jul 25 04:46:44 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 197328 kb
Host smart-b7c652dd-13b5-437f-8500-da56154f5b9a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832277200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2832277200
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1917196232
Short name T380
Test name
Test status
Simulation time 111594590 ps
CPU time 0.7 seconds
Started Jul 25 04:46:42 PM PDT 24
Finished Jul 25 04:46:43 PM PDT 24
Peak memory 195084 kb
Host smart-ac35c649-a9e5-4a3e-93be-8d5536476f28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917196232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1917196232
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1136690310
Short name T458
Test name
Test status
Simulation time 162262689 ps
CPU time 0.78 seconds
Started Jul 25 04:46:51 PM PDT 24
Finished Jul 25 04:46:52 PM PDT 24
Peak memory 196688 kb
Host smart-d926d020-6849-4d7e-b225-a9f8fd5ba507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136690310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1136690310
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1679123255
Short name T200
Test name
Test status
Simulation time 129272723 ps
CPU time 2.45 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 198464 kb
Host smart-5325cf7a-a697-4c37-918f-fbe730384c9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679123255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1679123255
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2268609845
Short name T60
Test name
Test status
Simulation time 555011371 ps
CPU time 1.43 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:46 PM PDT 24
Peak memory 197396 kb
Host smart-1dd5454c-02c1-493a-8787-deb85bad086b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268609845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2268609845
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3280789247
Short name T328
Test name
Test status
Simulation time 23322158 ps
CPU time 0.82 seconds
Started Jul 25 04:46:47 PM PDT 24
Finished Jul 25 04:46:48 PM PDT 24
Peak memory 197032 kb
Host smart-bc9fe1aa-f5ce-483b-9753-137cfab1bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280789247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3280789247
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.4265536890
Short name T217
Test name
Test status
Simulation time 28818533 ps
CPU time 1.05 seconds
Started Jul 25 04:46:39 PM PDT 24
Finished Jul 25 04:46:41 PM PDT 24
Peak memory 196268 kb
Host smart-73d0d66a-fdfa-40d5-ac9c-8d2397599c7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265536890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.4265536890
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2327765831
Short name T247
Test name
Test status
Simulation time 26506063 ps
CPU time 1.27 seconds
Started Jul 25 04:46:39 PM PDT 24
Finished Jul 25 04:46:40 PM PDT 24
Peak memory 198504 kb
Host smart-57684b4a-c1c5-4615-9850-b4e3d32df87e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327765831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2327765831
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3582569656
Short name T595
Test name
Test status
Simulation time 35242561 ps
CPU time 0.93 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 196176 kb
Host smart-e6913789-4e40-44ee-bc8e-52734b65bbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582569656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3582569656
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.164346741
Short name T337
Test name
Test status
Simulation time 70970938 ps
CPU time 1.19 seconds
Started Jul 25 04:46:37 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 196284 kb
Host smart-af39ffba-a518-4c80-abb2-54f5d38dbd42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164346741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.164346741
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1648734397
Short name T513
Test name
Test status
Simulation time 1484080435 ps
CPU time 20.32 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:56 PM PDT 24
Peak memory 198548 kb
Host smart-ab115208-cfd5-4b4d-9ef6-f589057aea1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648734397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1648734397
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1194596875
Short name T258
Test name
Test status
Simulation time 40039001 ps
CPU time 0.56 seconds
Started Jul 25 04:46:44 PM PDT 24
Finished Jul 25 04:46:45 PM PDT 24
Peak memory 194576 kb
Host smart-1bdfb6f6-d491-4b59-8c36-c370b38a255d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194596875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1194596875
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.807177960
Short name T229
Test name
Test status
Simulation time 278779453 ps
CPU time 0.69 seconds
Started Jul 25 04:46:39 PM PDT 24
Finished Jul 25 04:46:40 PM PDT 24
Peak memory 194656 kb
Host smart-da916236-bc95-4c20-8275-e6c30acde9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807177960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.807177960
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.4039790481
Short name T571
Test name
Test status
Simulation time 238581153 ps
CPU time 5.78 seconds
Started Jul 25 04:46:46 PM PDT 24
Finished Jul 25 04:46:52 PM PDT 24
Peak memory 196008 kb
Host smart-3daf8108-264e-4869-a011-44525352f087
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039790481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.4039790481
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2824170484
Short name T568
Test name
Test status
Simulation time 213100079 ps
CPU time 0.92 seconds
Started Jul 25 04:46:36 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 197088 kb
Host smart-5437de6a-bf24-4626-924b-1b0dae140492
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824170484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2824170484
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2127659603
Short name T563
Test name
Test status
Simulation time 37629334 ps
CPU time 0.71 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 195772 kb
Host smart-52577cda-dd55-4fb5-a86b-b7afa81b8b23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127659603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2127659603
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.643970196
Short name T550
Test name
Test status
Simulation time 91698641 ps
CPU time 1.89 seconds
Started Jul 25 04:46:44 PM PDT 24
Finished Jul 25 04:46:46 PM PDT 24
Peak memory 197016 kb
Host smart-bfdf9879-4e0c-4242-b8a1-9fa77469965b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643970196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.643970196
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.24120697
Short name T496
Test name
Test status
Simulation time 131237185 ps
CPU time 2.43 seconds
Started Jul 25 04:46:47 PM PDT 24
Finished Jul 25 04:46:50 PM PDT 24
Peak memory 196256 kb
Host smart-1e971ac4-beb0-4cab-bcf4-9116d0ac1859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24120697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.24120697
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3865284202
Short name T140
Test name
Test status
Simulation time 40314430 ps
CPU time 0.98 seconds
Started Jul 25 04:46:47 PM PDT 24
Finished Jul 25 04:46:48 PM PDT 24
Peak memory 197216 kb
Host smart-2c1f8164-ad27-4791-b442-fd3af0f500a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865284202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3865284202
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3570418534
Short name T646
Test name
Test status
Simulation time 134929128 ps
CPU time 0.83 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:36 PM PDT 24
Peak memory 196336 kb
Host smart-5efa0e4f-6c2e-49d1-b0d3-46df07e651ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570418534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3570418534
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2825503774
Short name T464
Test name
Test status
Simulation time 369109341 ps
CPU time 3.87 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:42 PM PDT 24
Peak memory 198392 kb
Host smart-5fe8b350-f1b9-44d8-a41d-1e49f8cd7519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825503774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2825503774
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.851114700
Short name T577
Test name
Test status
Simulation time 51534923 ps
CPU time 1.35 seconds
Started Jul 25 04:46:51 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 197204 kb
Host smart-3673a5d1-2885-45ff-8195-87fbb11dd738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851114700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.851114700
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.4032462324
Short name T419
Test name
Test status
Simulation time 255398564 ps
CPU time 1.29 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 197424 kb
Host smart-2bc393de-ccea-4731-924d-bd6ba0c6f7d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032462324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.4032462324
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3428963249
Short name T549
Test name
Test status
Simulation time 10388673583 ps
CPU time 144.25 seconds
Started Jul 25 04:47:07 PM PDT 24
Finished Jul 25 04:49:31 PM PDT 24
Peak memory 198524 kb
Host smart-2f83077a-ac45-4e11-a4ce-c5bccc88d91b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428963249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3428963249
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1195542669
Short name T678
Test name
Test status
Simulation time 48999713 ps
CPU time 0.54 seconds
Started Jul 25 04:47:20 PM PDT 24
Finished Jul 25 04:47:21 PM PDT 24
Peak memory 194408 kb
Host smart-c802e2e4-4369-4827-863b-32a77cb9352b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195542669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1195542669
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1123455356
Short name T326
Test name
Test status
Simulation time 39399601 ps
CPU time 0.58 seconds
Started Jul 25 04:46:36 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 194420 kb
Host smart-dbe1b40f-0022-46d8-ad23-7a06f0219ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123455356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1123455356
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3771274652
Short name T666
Test name
Test status
Simulation time 130858648 ps
CPU time 3.28 seconds
Started Jul 25 04:46:46 PM PDT 24
Finished Jul 25 04:46:50 PM PDT 24
Peak memory 196272 kb
Host smart-acb39255-e014-48c8-9e1a-fc4f1dd7426e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771274652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3771274652
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3295180534
Short name T667
Test name
Test status
Simulation time 111393117 ps
CPU time 0.86 seconds
Started Jul 25 04:46:41 PM PDT 24
Finished Jul 25 04:46:47 PM PDT 24
Peak memory 196456 kb
Host smart-5e0a6374-0eb5-4ff6-a718-1b8c7b6f4ab5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295180534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3295180534
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2111030648
Short name T498
Test name
Test status
Simulation time 36160591 ps
CPU time 1.05 seconds
Started Jul 25 04:46:45 PM PDT 24
Finished Jul 25 04:46:46 PM PDT 24
Peak memory 196456 kb
Host smart-323188af-86da-4068-b5a6-a1cb5a0a6b84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111030648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2111030648
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.515632823
Short name T338
Test name
Test status
Simulation time 53768913 ps
CPU time 1.34 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 198364 kb
Host smart-8fa05e5f-a23a-43bc-a255-f0bc9b2b7724
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515632823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.515632823
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.935659842
Short name T114
Test name
Test status
Simulation time 891397242 ps
CPU time 2.42 seconds
Started Jul 25 04:46:42 PM PDT 24
Finished Jul 25 04:46:45 PM PDT 24
Peak memory 197696 kb
Host smart-57c2b6b0-81b2-4f56-987b-7498671b0329
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935659842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
935659842
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3313315251
Short name T226
Test name
Test status
Simulation time 57890734 ps
CPU time 0.7 seconds
Started Jul 25 04:46:37 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 194712 kb
Host smart-879d4737-8bb5-41be-a653-9351ebd4a5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313315251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3313315251
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1743631379
Short name T297
Test name
Test status
Simulation time 25006703 ps
CPU time 0.77 seconds
Started Jul 25 04:46:42 PM PDT 24
Finished Jul 25 04:46:43 PM PDT 24
Peak memory 195864 kb
Host smart-156433e9-8d1d-4fc3-9f44-75057bd5db8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743631379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1743631379
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3014069820
Short name T12
Test name
Test status
Simulation time 71018854 ps
CPU time 1.85 seconds
Started Jul 25 04:47:09 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 198472 kb
Host smart-b2bf6264-d8f1-4694-a854-a0cc7a4056a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014069820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3014069820
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3547333339
Short name T128
Test name
Test status
Simulation time 232232417 ps
CPU time 0.75 seconds
Started Jul 25 04:46:36 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 195600 kb
Host smart-1e5fd5f5-848f-4a54-89dd-e6a0cdb3196c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547333339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3547333339
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3859960348
Short name T427
Test name
Test status
Simulation time 70048619 ps
CPU time 1.07 seconds
Started Jul 25 04:46:57 PM PDT 24
Finished Jul 25 04:46:58 PM PDT 24
Peak memory 195996 kb
Host smart-87208621-99ff-45c6-a37a-5e587b31284c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859960348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3859960348
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.372560282
Short name T120
Test name
Test status
Simulation time 7897808615 ps
CPU time 107.52 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:48:52 PM PDT 24
Peak memory 198576 kb
Host smart-c8796c57-c8c2-476a-8b46-f3ea43a46573
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372560282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.372560282
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1534494164
Short name T501
Test name
Test status
Simulation time 43590922 ps
CPU time 0.53 seconds
Started Jul 25 04:46:37 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 195112 kb
Host smart-c39af1f7-e5fb-4cf7-9bbb-fc3f6df1811f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534494164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1534494164
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.805091737
Short name T315
Test name
Test status
Simulation time 38518401 ps
CPU time 0.9 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:34 PM PDT 24
Peak memory 197736 kb
Host smart-5a433190-90d7-4871-8db8-72aedeba5f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805091737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.805091737
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1391925283
Short name T163
Test name
Test status
Simulation time 135653317 ps
CPU time 3.16 seconds
Started Jul 25 04:46:42 PM PDT 24
Finished Jul 25 04:46:45 PM PDT 24
Peak memory 196416 kb
Host smart-888a4ab3-7455-4d08-a1d3-b50c1bc60aea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391925283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1391925283
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1408876557
Short name T166
Test name
Test status
Simulation time 57890814 ps
CPU time 0.84 seconds
Started Jul 25 04:46:46 PM PDT 24
Finished Jul 25 04:46:47 PM PDT 24
Peak memory 197084 kb
Host smart-ec11d5f1-2663-4e47-b631-6b37acc65d1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408876557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1408876557
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1467811582
Short name T319
Test name
Test status
Simulation time 21665364 ps
CPU time 0.68 seconds
Started Jul 25 04:46:39 PM PDT 24
Finished Jul 25 04:46:40 PM PDT 24
Peak memory 194792 kb
Host smart-304f5339-4d96-4b47-bc92-98998e931a1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467811582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1467811582
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3394120594
Short name T382
Test name
Test status
Simulation time 124622938 ps
CPU time 2.55 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 198664 kb
Host smart-4b3466cc-bd00-43bb-97fa-7045a07ac380
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394120594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3394120594
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1653946168
Short name T320
Test name
Test status
Simulation time 107566365 ps
CPU time 1.35 seconds
Started Jul 25 04:46:57 PM PDT 24
Finished Jul 25 04:46:58 PM PDT 24
Peak memory 197120 kb
Host smart-ba77c953-a1c5-402d-b126-3387609a47d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653946168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1653946168
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.837229291
Short name T706
Test name
Test status
Simulation time 47836340 ps
CPU time 0.92 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 197200 kb
Host smart-4c73f09f-5431-43f4-8abc-21305bc589f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837229291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.837229291
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.19630050
Short name T580
Test name
Test status
Simulation time 37889811 ps
CPU time 0.93 seconds
Started Jul 25 04:46:43 PM PDT 24
Finished Jul 25 04:46:44 PM PDT 24
Peak memory 196568 kb
Host smart-088d8559-84fc-4135-b9af-aa3abeb440ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19630050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup_
pulldown.19630050
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_smoke.3735187044
Short name T525
Test name
Test status
Simulation time 192993056 ps
CPU time 0.91 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 197636 kb
Host smart-2af5b8a4-041d-4664-a137-062515937446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735187044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3735187044
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.404411542
Short name T121
Test name
Test status
Simulation time 122510519 ps
CPU time 0.92 seconds
Started Jul 25 04:46:58 PM PDT 24
Finished Jul 25 04:46:59 PM PDT 24
Peak memory 196960 kb
Host smart-e31260cf-3ba2-4cce-9ff8-c7436fafcede
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404411542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.404411542
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1676756729
Short name T453
Test name
Test status
Simulation time 2146394917 ps
CPU time 45.88 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:47:23 PM PDT 24
Peak memory 198432 kb
Host smart-a52dd154-9cfb-479c-9505-a4ec9fd8a210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676756729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1676756729
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2605957821
Short name T6
Test name
Test status
Simulation time 154457961591 ps
CPU time 486.26 seconds
Started Jul 25 04:46:29 PM PDT 24
Finished Jul 25 04:54:36 PM PDT 24
Peak memory 198704 kb
Host smart-6c895963-20b7-4dbe-b204-82490187e96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2605957821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2605957821
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.659333166
Short name T291
Test name
Test status
Simulation time 20243512 ps
CPU time 0.59 seconds
Started Jul 25 04:46:36 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 194552 kb
Host smart-f58e3e97-85ec-4e33-9f4e-a6326a314e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659333166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.659333166
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2900670498
Short name T100
Test name
Test status
Simulation time 94392159 ps
CPU time 0.86 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:34 PM PDT 24
Peak memory 197452 kb
Host smart-b1767b11-63fb-44df-a4aa-de0f7b064de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900670498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2900670498
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2727285810
Short name T271
Test name
Test status
Simulation time 1642791075 ps
CPU time 9.93 seconds
Started Jul 25 04:46:42 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 197276 kb
Host smart-6307079e-6eb9-4a0f-934e-a8bf3c26b84b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727285810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2727285810
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.400354260
Short name T241
Test name
Test status
Simulation time 69516302 ps
CPU time 0.6 seconds
Started Jul 25 04:46:43 PM PDT 24
Finished Jul 25 04:46:44 PM PDT 24
Peak memory 194872 kb
Host smart-4b699da4-eccd-4821-8973-b2d55d59a1e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400354260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.400354260
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.4287408455
Short name T307
Test name
Test status
Simulation time 25086259 ps
CPU time 0.84 seconds
Started Jul 25 04:47:23 PM PDT 24
Finished Jul 25 04:47:24 PM PDT 24
Peak memory 196736 kb
Host smart-4bfaecd8-2d29-47e9-991d-bbdf525c4b5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287408455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.4287408455
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.4221317866
Short name T658
Test name
Test status
Simulation time 56127145 ps
CPU time 2.18 seconds
Started Jul 25 04:46:45 PM PDT 24
Finished Jul 25 04:46:47 PM PDT 24
Peak memory 196776 kb
Host smart-5bba6998-3ee0-4dfb-ba43-c8f487a734a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221317866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.4221317866
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1420633118
Short name T632
Test name
Test status
Simulation time 112306045 ps
CPU time 3.22 seconds
Started Jul 25 04:46:57 PM PDT 24
Finished Jul 25 04:47:01 PM PDT 24
Peak memory 198560 kb
Host smart-a79ac8a8-bf26-44b3-9093-46c491a42d02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420633118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1420633118
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.746325198
Short name T707
Test name
Test status
Simulation time 51782412 ps
CPU time 1 seconds
Started Jul 25 04:46:44 PM PDT 24
Finished Jul 25 04:46:46 PM PDT 24
Peak memory 196324 kb
Host smart-6d90c527-063a-469f-8279-0bf41ed96df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746325198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.746325198
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3761319665
Short name T378
Test name
Test status
Simulation time 81213945 ps
CPU time 0.88 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:36 PM PDT 24
Peak memory 196344 kb
Host smart-42247bd8-de02-4d85-ba65-72009af34cb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761319665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3761319665
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1111680593
Short name T579
Test name
Test status
Simulation time 242946253 ps
CPU time 2.72 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:41 PM PDT 24
Peak memory 198468 kb
Host smart-ee341130-5460-42ba-9eb7-468e765ce55e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111680593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1111680593
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.91982094
Short name T444
Test name
Test status
Simulation time 138164469 ps
CPU time 1.3 seconds
Started Jul 25 04:46:52 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 198456 kb
Host smart-3fcc667b-e6ed-41d3-aac7-000f162074fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91982094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.91982094
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2076989615
Short name T57
Test name
Test status
Simulation time 39131816 ps
CPU time 0.85 seconds
Started Jul 25 04:46:37 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 195752 kb
Host smart-4366c2a2-4c0c-433a-a915-bff156145e17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076989615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2076989615
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2225256187
Short name T287
Test name
Test status
Simulation time 12262381979 ps
CPU time 179.61 seconds
Started Jul 25 04:46:51 PM PDT 24
Finished Jul 25 04:49:51 PM PDT 24
Peak memory 198612 kb
Host smart-8cd2c098-d9b9-44ad-b6b8-c0790eeda661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225256187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2225256187
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3054319334
Short name T414
Test name
Test status
Simulation time 132104469159 ps
CPU time 401.79 seconds
Started Jul 25 04:46:37 PM PDT 24
Finished Jul 25 04:53:19 PM PDT 24
Peak memory 207072 kb
Host smart-753a5c3d-5044-42e9-818d-83d874f572ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3054319334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3054319334
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1854523695
Short name T186
Test name
Test status
Simulation time 39251153 ps
CPU time 0.53 seconds
Started Jul 25 04:46:48 PM PDT 24
Finished Jul 25 04:46:49 PM PDT 24
Peak memory 195088 kb
Host smart-db7d677f-adf2-444b-b319-d986c3348e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854523695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1854523695
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2225642608
Short name T206
Test name
Test status
Simulation time 268767279 ps
CPU time 0.86 seconds
Started Jul 25 04:47:09 PM PDT 24
Finished Jul 25 04:47:10 PM PDT 24
Peak memory 197752 kb
Host smart-bebcaf89-92d3-498d-ab37-e21c71766d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225642608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2225642608
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.834225933
Short name T356
Test name
Test status
Simulation time 1940905018 ps
CPU time 17.12 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:47 PM PDT 24
Peak memory 196720 kb
Host smart-9e4800f5-7fa3-4b29-a46e-321a0d5a6924
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834225933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.834225933
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3787421713
Short name T583
Test name
Test status
Simulation time 16120230 ps
CPU time 0.62 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 194852 kb
Host smart-ff450c23-b9cd-46d4-9eb3-a2190e4a2368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787421713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3787421713
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2869877566
Short name T584
Test name
Test status
Simulation time 85170846 ps
CPU time 0.82 seconds
Started Jul 25 04:46:43 PM PDT 24
Finished Jul 25 04:46:44 PM PDT 24
Peak memory 196664 kb
Host smart-920c8bd0-319f-424d-a2e8-70584255cc99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869877566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2869877566
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3234582212
Short name T198
Test name
Test status
Simulation time 87876038 ps
CPU time 2.45 seconds
Started Jul 25 04:46:36 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 198420 kb
Host smart-7075b8a3-34e7-4053-9da4-e0ce89bec72e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234582212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3234582212
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1490312101
Short name T474
Test name
Test status
Simulation time 158260758 ps
CPU time 1.07 seconds
Started Jul 25 04:46:36 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 196228 kb
Host smart-8c3be384-604a-44da-9497-747fa5e050c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490312101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1490312101
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1532399846
Short name T168
Test name
Test status
Simulation time 81075532 ps
CPU time 0.9 seconds
Started Jul 25 04:47:18 PM PDT 24
Finished Jul 25 04:47:19 PM PDT 24
Peak memory 196280 kb
Host smart-a87db022-c32e-4b0a-82f7-854b6a5d107b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532399846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1532399846
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.159525673
Short name T330
Test name
Test status
Simulation time 45635670 ps
CPU time 0.69 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 196540 kb
Host smart-0c63eb4b-c15f-4c7a-a6e1-06f01e9f4893
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159525673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.159525673
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3655692524
Short name T245
Test name
Test status
Simulation time 373006303 ps
CPU time 3.74 seconds
Started Jul 25 04:46:54 PM PDT 24
Finished Jul 25 04:46:58 PM PDT 24
Peak memory 198484 kb
Host smart-c20f36d5-e892-4d83-8c1c-5972e96c3e1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655692524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3655692524
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.747567549
Short name T21
Test name
Test status
Simulation time 32813587 ps
CPU time 0.78 seconds
Started Jul 25 04:46:39 PM PDT 24
Finished Jul 25 04:46:40 PM PDT 24
Peak memory 196484 kb
Host smart-34bc1252-0573-4561-a2b9-6debefcb7883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747567549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.747567549
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3506808133
Short name T130
Test name
Test status
Simulation time 593677422 ps
CPU time 1.12 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 196004 kb
Host smart-137c4eaf-9399-4fb8-9dc7-873bead790b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506808133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3506808133
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1923146348
Short name T162
Test name
Test status
Simulation time 11847470200 ps
CPU time 84.88 seconds
Started Jul 25 04:46:39 PM PDT 24
Finished Jul 25 04:48:19 PM PDT 24
Peak memory 198592 kb
Host smart-80022962-7278-4a11-a8b4-b807d993139d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923146348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1923146348
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2948394592
Short name T640
Test name
Test status
Simulation time 496343205133 ps
CPU time 2351.3 seconds
Started Jul 25 04:46:49 PM PDT 24
Finished Jul 25 05:26:01 PM PDT 24
Peak memory 198720 kb
Host smart-ac7ce11d-b85b-4e00-adc3-379cd23ca477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2948394592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2948394592
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3082232917
Short name T664
Test name
Test status
Simulation time 62138018 ps
CPU time 0.55 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:26 PM PDT 24
Peak memory 194444 kb
Host smart-f84f02ce-a213-40a0-9707-690cbd9fe9a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082232917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3082232917
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3789596416
Short name T153
Test name
Test status
Simulation time 42874087 ps
CPU time 0.81 seconds
Started Jul 25 04:46:48 PM PDT 24
Finished Jul 25 04:46:49 PM PDT 24
Peak memory 196880 kb
Host smart-e44eb8d7-04a1-4133-9cb2-82037d963016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789596416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3789596416
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2957505937
Short name T165
Test name
Test status
Simulation time 2790120460 ps
CPU time 11.57 seconds
Started Jul 25 04:47:07 PM PDT 24
Finished Jul 25 04:47:19 PM PDT 24
Peak memory 197276 kb
Host smart-13620bc6-dca5-4961-81a7-ef33e098facd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957505937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2957505937
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3120405936
Short name T467
Test name
Test status
Simulation time 130625467 ps
CPU time 0.66 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:34 PM PDT 24
Peak memory 195128 kb
Host smart-52488ad6-3d32-4e0b-85a2-adb499019f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120405936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3120405936
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2059055089
Short name T696
Test name
Test status
Simulation time 22394592 ps
CPU time 0.76 seconds
Started Jul 25 04:46:36 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 196032 kb
Host smart-462d4ebe-87d9-480b-aa0b-9636e6158823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059055089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2059055089
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2119628180
Short name T603
Test name
Test status
Simulation time 191520156 ps
CPU time 1.09 seconds
Started Jul 25 04:46:42 PM PDT 24
Finished Jul 25 04:46:44 PM PDT 24
Peak memory 197544 kb
Host smart-b557e526-d10c-4517-9e4f-20d97416d9a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119628180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2119628180
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3414297862
Short name T663
Test name
Test status
Simulation time 106086476 ps
CPU time 1.36 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:47:01 PM PDT 24
Peak memory 196296 kb
Host smart-f1bbaf8f-1314-43de-9504-62fc5907e690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414297862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3414297862
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.588136732
Short name T569
Test name
Test status
Simulation time 33752355 ps
CPU time 0.83 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 195980 kb
Host smart-e7a440c7-c4b0-4669-a134-e1bfcd334860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588136732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.588136732
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3952432589
Short name T237
Test name
Test status
Simulation time 30182024 ps
CPU time 0.81 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 196944 kb
Host smart-be84a8ec-dad4-4caf-9b4c-1d7415e33516
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952432589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3952432589
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1467132366
Short name T691
Test name
Test status
Simulation time 89430499 ps
CPU time 2.21 seconds
Started Jul 25 04:46:52 PM PDT 24
Finished Jul 25 04:46:54 PM PDT 24
Peak memory 198480 kb
Host smart-e81664a1-1c29-40c2-bf1b-8c38ac1bba3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467132366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1467132366
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1763251517
Short name T602
Test name
Test status
Simulation time 148720473 ps
CPU time 0.97 seconds
Started Jul 25 04:46:43 PM PDT 24
Finished Jul 25 04:46:44 PM PDT 24
Peak memory 196684 kb
Host smart-dba723f0-4627-4212-a7e3-5701c5306df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763251517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1763251517
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2384397375
Short name T370
Test name
Test status
Simulation time 79995202 ps
CPU time 1.19 seconds
Started Jul 25 04:47:00 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 196852 kb
Host smart-6d12f230-50a1-438d-886b-5fee810d1e5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384397375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2384397375
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.4111527997
Short name T197
Test name
Test status
Simulation time 21490508772 ps
CPU time 114.68 seconds
Started Jul 25 04:47:07 PM PDT 24
Finished Jul 25 04:49:02 PM PDT 24
Peak memory 198580 kb
Host smart-3fe8f12b-d2a2-4681-bbe5-7dbc5d1062ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111527997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.4111527997
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1640198839
Short name T404
Test name
Test status
Simulation time 11316234 ps
CPU time 0.56 seconds
Started Jul 25 04:46:52 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 194384 kb
Host smart-60350cf0-8afe-4584-89bb-6d2d385a9105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640198839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1640198839
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2323710420
Short name T651
Test name
Test status
Simulation time 41639445 ps
CPU time 0.65 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:36 PM PDT 24
Peak memory 195212 kb
Host smart-daade35e-5018-4c6a-a587-26b70a94a9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323710420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2323710420
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1392974433
Short name T102
Test name
Test status
Simulation time 1687362696 ps
CPU time 21.06 seconds
Started Jul 25 04:46:50 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 198460 kb
Host smart-8fe08d39-0ad9-45d6-aed4-bd0432ece072
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392974433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1392974433
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.87617120
Short name T376
Test name
Test status
Simulation time 305996297 ps
CPU time 0.74 seconds
Started Jul 25 04:47:14 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 196204 kb
Host smart-34746499-1860-4576-a184-f7ca05895855
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87617120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.87617120
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2913676299
Short name T151
Test name
Test status
Simulation time 216963655 ps
CPU time 1.09 seconds
Started Jul 25 04:46:41 PM PDT 24
Finished Jul 25 04:46:42 PM PDT 24
Peak memory 196532 kb
Host smart-3d0a9a65-547b-4620-a923-89d4c0ed6990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913676299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2913676299
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.682077982
Short name T375
Test name
Test status
Simulation time 31999888 ps
CPU time 1.24 seconds
Started Jul 25 04:46:56 PM PDT 24
Finished Jul 25 04:46:57 PM PDT 24
Peak memory 197404 kb
Host smart-9fc6eae4-7afb-4001-a802-dd22417d8695
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682077982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.682077982
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2434006195
Short name T155
Test name
Test status
Simulation time 297142041 ps
CPU time 1.92 seconds
Started Jul 25 04:46:41 PM PDT 24
Finished Jul 25 04:46:43 PM PDT 24
Peak memory 198516 kb
Host smart-a1a6f757-9de6-4bae-8e27-fa1ceb3b034c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434006195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2434006195
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2146158628
Short name T318
Test name
Test status
Simulation time 31545845 ps
CPU time 0.8 seconds
Started Jul 25 04:46:47 PM PDT 24
Finished Jul 25 04:46:48 PM PDT 24
Peak memory 197036 kb
Host smart-27f3dfa8-b755-4b5b-b2bc-fd1c50ba528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146158628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2146158628
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1633549780
Short name T395
Test name
Test status
Simulation time 24820338 ps
CPU time 0.89 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 196292 kb
Host smart-4ff1dab3-c8d5-441d-804b-21f5a9a1590c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633549780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1633549780
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1290197685
Short name T598
Test name
Test status
Simulation time 356601522 ps
CPU time 4.18 seconds
Started Jul 25 04:46:49 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 198408 kb
Host smart-30ffbdbd-aae1-4110-b2ee-3f44dfbd5d96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290197685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1290197685
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1052645374
Short name T386
Test name
Test status
Simulation time 86496941 ps
CPU time 0.9 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 196804 kb
Host smart-83d647ee-96ef-4d2c-a5bf-8d42ab9c7722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052645374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1052645374
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1794142131
Short name T316
Test name
Test status
Simulation time 65097761 ps
CPU time 1.02 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 196280 kb
Host smart-5908fe87-1a9b-4791-bf28-8b9d6716ccde
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794142131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1794142131
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.575555338
Short name T329
Test name
Test status
Simulation time 13059078492 ps
CPU time 170.04 seconds
Started Jul 25 04:46:41 PM PDT 24
Finished Jul 25 04:49:31 PM PDT 24
Peak memory 198580 kb
Host smart-3053da06-4bf6-47a3-bf81-b0344fcf04ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575555338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.575555338
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.683581600
Short name T65
Test name
Test status
Simulation time 32068260756 ps
CPU time 806.58 seconds
Started Jul 25 04:46:49 PM PDT 24
Finished Jul 25 05:00:16 PM PDT 24
Peak memory 198728 kb
Host smart-f26f7aa4-995b-4200-afb6-96752092c614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=683581600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.683581600
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1821280701
Short name T354
Test name
Test status
Simulation time 44416012 ps
CPU time 0.57 seconds
Started Jul 25 04:46:37 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 195276 kb
Host smart-5eff9406-25c4-452d-8868-898049449307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821280701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1821280701
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.159919757
Short name T368
Test name
Test status
Simulation time 148505532 ps
CPU time 0.89 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 196952 kb
Host smart-f9467a8a-57ec-47e2-aa1c-2bec39c413a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159919757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.159919757
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.590914908
Short name T514
Test name
Test status
Simulation time 4147539685 ps
CPU time 21.3 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 197016 kb
Host smart-f18ec9cf-6c29-409c-868a-51767749ff0b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590914908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.590914908
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2279307218
Short name T553
Test name
Test status
Simulation time 152261083 ps
CPU time 0.76 seconds
Started Jul 25 04:46:44 PM PDT 24
Finished Jul 25 04:46:45 PM PDT 24
Peak memory 196992 kb
Host smart-ed32b5e2-9ebd-4e7c-92dd-4ed132298b48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279307218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2279307218
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.4241576969
Short name T537
Test name
Test status
Simulation time 179657983 ps
CPU time 1.24 seconds
Started Jul 25 04:46:36 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 198492 kb
Host smart-b464ed05-2a38-4f7d-b210-9c7f6d4fd627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241576969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.4241576969
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.442987092
Short name T589
Test name
Test status
Simulation time 37370025 ps
CPU time 0.9 seconds
Started Jul 25 04:46:53 PM PDT 24
Finished Jul 25 04:46:54 PM PDT 24
Peak memory 197328 kb
Host smart-44b5f998-cc83-446f-b581-75613793420e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442987092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.442987092
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3275043644
Short name T55
Test name
Test status
Simulation time 164014589 ps
CPU time 2.91 seconds
Started Jul 25 04:46:52 PM PDT 24
Finished Jul 25 04:46:55 PM PDT 24
Peak memory 197308 kb
Host smart-2219c905-db25-46f9-a200-d43bc647f8e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275043644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3275043644
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1522045484
Short name T303
Test name
Test status
Simulation time 19108675 ps
CPU time 0.74 seconds
Started Jul 25 04:46:57 PM PDT 24
Finished Jul 25 04:46:58 PM PDT 24
Peak memory 195920 kb
Host smart-181053bf-eeb9-4f5a-9fd5-66c6839dbefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522045484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1522045484
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1445426780
Short name T648
Test name
Test status
Simulation time 31712539 ps
CPU time 1.09 seconds
Started Jul 25 04:47:09 PM PDT 24
Finished Jul 25 04:47:10 PM PDT 24
Peak memory 197396 kb
Host smart-51a970f3-24cf-4a42-9e26-3e67c5c276a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445426780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1445426780
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2006149337
Short name T381
Test name
Test status
Simulation time 2949812682 ps
CPU time 4.18 seconds
Started Jul 25 04:47:06 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 198508 kb
Host smart-1b38baac-0262-41ac-9bea-13166fe703c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006149337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2006149337
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2932687704
Short name T284
Test name
Test status
Simulation time 73032477 ps
CPU time 1.13 seconds
Started Jul 25 04:47:13 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 196172 kb
Host smart-e815b035-c5f2-40d7-8f5b-ed0ef2aaed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932687704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2932687704
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1411786242
Short name T127
Test name
Test status
Simulation time 126275736 ps
CPU time 1.27 seconds
Started Jul 25 04:47:09 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 197240 kb
Host smart-08ffbb22-66d4-4a80-9258-317a6ee38e91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411786242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1411786242
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1815758823
Short name T629
Test name
Test status
Simulation time 26882301602 ps
CPU time 142.76 seconds
Started Jul 25 04:46:44 PM PDT 24
Finished Jul 25 04:49:07 PM PDT 24
Peak memory 198640 kb
Host smart-0c633877-ab13-4e78-ade7-7b728b703cef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815758823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1815758823
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.4119556104
Short name T540
Test name
Test status
Simulation time 162420139991 ps
CPU time 1640.38 seconds
Started Jul 25 04:47:13 PM PDT 24
Finished Jul 25 05:14:34 PM PDT 24
Peak memory 198732 kb
Host smart-c86fd81c-be0a-4c70-bdee-29d8d1c36ef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4119556104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.4119556104
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2115646517
Short name T626
Test name
Test status
Simulation time 11929584 ps
CPU time 0.57 seconds
Started Jul 25 04:46:30 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 194376 kb
Host smart-2d64bb60-9044-4bc8-bf48-c4877c365d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115646517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2115646517
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2608535077
Short name T401
Test name
Test status
Simulation time 46814988 ps
CPU time 0.71 seconds
Started Jul 25 04:46:27 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 194688 kb
Host smart-2a477f87-f699-454f-9053-881f31e3a967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608535077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2608535077
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2830911442
Short name T430
Test name
Test status
Simulation time 715991703 ps
CPU time 18.82 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:46:40 PM PDT 24
Peak memory 197460 kb
Host smart-8d7e0ddb-cca2-4326-8620-c03e45de9571
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830911442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2830911442
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4260234926
Short name T177
Test name
Test status
Simulation time 173069589 ps
CPU time 0.72 seconds
Started Jul 25 04:46:19 PM PDT 24
Finished Jul 25 04:46:20 PM PDT 24
Peak memory 196296 kb
Host smart-156717f3-4134-46a4-a154-f36af1b0b172
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260234926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4260234926
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3271293931
Short name T519
Test name
Test status
Simulation time 70812034 ps
CPU time 1 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 196244 kb
Host smart-98d7fdd6-844c-4273-a6fd-405dd251b302
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271293931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3271293931
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1522625974
Short name T236
Test name
Test status
Simulation time 697043714 ps
CPU time 3.24 seconds
Started Jul 25 04:46:18 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 198384 kb
Host smart-23b723e1-17c1-4e17-b8ec-c11d1dc7e119
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522625974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1522625974
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.882621440
Short name T28
Test name
Test status
Simulation time 126546744 ps
CPU time 1.67 seconds
Started Jul 25 04:46:24 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 196616 kb
Host smart-881d3078-ffc4-4840-85a3-d9166487a7a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882621440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.882621440
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1542082507
Short name T282
Test name
Test status
Simulation time 150202376 ps
CPU time 1.09 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:36 PM PDT 24
Peak memory 197484 kb
Host smart-273d4017-3167-4c98-b36d-d486f5d17206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542082507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1542082507
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3009586559
Short name T689
Test name
Test status
Simulation time 17725629 ps
CPU time 0.76 seconds
Started Jul 25 04:46:16 PM PDT 24
Finished Jul 25 04:46:17 PM PDT 24
Peak memory 195860 kb
Host smart-8ff931bb-3f7b-4165-ab25-acf9b72869c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009586559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3009586559
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.245129115
Short name T111
Test name
Test status
Simulation time 58066930 ps
CPU time 1.19 seconds
Started Jul 25 04:46:09 PM PDT 24
Finished Jul 25 04:46:11 PM PDT 24
Peak memory 198244 kb
Host smart-fc95c588-723e-405a-90b3-ef35d459fcb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245129115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.245129115
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1887398727
Short name T45
Test name
Test status
Simulation time 432031357 ps
CPU time 0.92 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 215408 kb
Host smart-b76a81a0-d881-46ff-bde6-c2701bfd877e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887398727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1887398727
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3034006409
Short name T448
Test name
Test status
Simulation time 155576854 ps
CPU time 1.16 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 196996 kb
Host smart-a3ff9b1b-03ee-4085-9bb4-853bb463244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034006409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3034006409
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2420880541
Short name T392
Test name
Test status
Simulation time 30387178 ps
CPU time 0.94 seconds
Started Jul 25 04:46:22 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 195832 kb
Host smart-f5de9592-2b3a-4c39-a4cc-034d9d2c1ad1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420880541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2420880541
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2976879104
Short name T470
Test name
Test status
Simulation time 9886188214 ps
CPU time 125.62 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:48:39 PM PDT 24
Peak memory 198532 kb
Host smart-aab4f2e9-3b4b-4041-b11c-0b44aec553d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976879104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2976879104
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2507898106
Short name T491
Test name
Test status
Simulation time 16928088 ps
CPU time 0.56 seconds
Started Jul 25 04:46:50 PM PDT 24
Finished Jul 25 04:46:50 PM PDT 24
Peak memory 194388 kb
Host smart-343a2c6b-d17e-46be-b593-cd07e3315db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507898106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2507898106
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.244737502
Short name T613
Test name
Test status
Simulation time 65646463 ps
CPU time 0.85 seconds
Started Jul 25 04:47:11 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 195872 kb
Host smart-af3894ec-8286-475d-a8ca-9ace97d9ca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244737502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.244737502
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1208609093
Short name T19
Test name
Test status
Simulation time 72541550 ps
CPU time 4.05 seconds
Started Jul 25 04:46:53 PM PDT 24
Finished Jul 25 04:46:57 PM PDT 24
Peak memory 196284 kb
Host smart-c3847153-021f-4c08-a12e-13e8bfb44c3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208609093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1208609093
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2033621526
Short name T548
Test name
Test status
Simulation time 127107837 ps
CPU time 0.93 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:29 PM PDT 24
Peak memory 197592 kb
Host smart-b8059363-eb0c-453a-ba2c-b2f540db7cb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033621526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2033621526
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2587628456
Short name T135
Test name
Test status
Simulation time 164593617 ps
CPU time 0.94 seconds
Started Jul 25 04:46:56 PM PDT 24
Finished Jul 25 04:46:58 PM PDT 24
Peak memory 196264 kb
Host smart-825b5f00-c398-4149-aca5-d7c936cdb75b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587628456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2587628456
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1242077315
Short name T372
Test name
Test status
Simulation time 210418708 ps
CPU time 2.29 seconds
Started Jul 25 04:47:23 PM PDT 24
Finished Jul 25 04:47:25 PM PDT 24
Peak memory 198588 kb
Host smart-17c6aff0-c2cc-458f-81da-a50ebd89d5ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242077315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1242077315
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2751824047
Short name T157
Test name
Test status
Simulation time 60046581 ps
CPU time 0.97 seconds
Started Jul 25 04:47:14 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 196736 kb
Host smart-5ab2ac74-4674-456d-8a7c-c2962148757d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751824047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2751824047
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.565825622
Short name T118
Test name
Test status
Simulation time 47652900 ps
CPU time 0.95 seconds
Started Jul 25 04:47:05 PM PDT 24
Finished Jul 25 04:47:06 PM PDT 24
Peak memory 196300 kb
Host smart-64aa91fc-3210-452a-a12f-66cfdc57547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565825622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.565825622
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2329379068
Short name T249
Test name
Test status
Simulation time 156533009 ps
CPU time 0.93 seconds
Started Jul 25 04:46:46 PM PDT 24
Finished Jul 25 04:46:47 PM PDT 24
Peak memory 196380 kb
Host smart-1d4f9308-601b-4378-a430-93e52317a3bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329379068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2329379068
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.579805074
Short name T582
Test name
Test status
Simulation time 282563403 ps
CPU time 1.12 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:26 PM PDT 24
Peak memory 198484 kb
Host smart-f0ed9433-ba09-4e83-8985-c44f796116b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579805074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.579805074
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1617228915
Short name T506
Test name
Test status
Simulation time 71414043 ps
CPU time 0.71 seconds
Started Jul 25 04:46:52 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 194620 kb
Host smart-2a924471-6715-4953-a14c-ef8c11183108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617228915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1617228915
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1428290538
Short name T636
Test name
Test status
Simulation time 77740672 ps
CPU time 0.95 seconds
Started Jul 25 04:46:49 PM PDT 24
Finished Jul 25 04:46:50 PM PDT 24
Peak memory 196120 kb
Host smart-7e8959b9-3812-42c6-a0ce-3544abba93fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428290538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1428290538
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2629342595
Short name T466
Test name
Test status
Simulation time 4734887562 ps
CPU time 110.59 seconds
Started Jul 25 04:47:07 PM PDT 24
Finished Jul 25 04:48:57 PM PDT 24
Peak memory 198588 kb
Host smart-1c9b9a40-7e5c-4dd8-83b4-85ea7e6a84b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629342595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2629342595
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.1465139520
Short name T447
Test name
Test status
Simulation time 14716390883 ps
CPU time 494.61 seconds
Started Jul 25 04:46:58 PM PDT 24
Finished Jul 25 04:55:13 PM PDT 24
Peak memory 206916 kb
Host smart-31294109-5a57-47e2-981f-b92a30036f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1465139520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.1465139520
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3964749061
Short name T446
Test name
Test status
Simulation time 37920152 ps
CPU time 0.55 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:29 PM PDT 24
Peak memory 194396 kb
Host smart-0474c3ff-7092-4884-86b6-374d47670b4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964749061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3964749061
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3868154874
Short name T240
Test name
Test status
Simulation time 41586036 ps
CPU time 0.68 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:05 PM PDT 24
Peak memory 194588 kb
Host smart-3e505c92-4528-46c1-b838-d90a2dce3040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868154874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3868154874
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.581971659
Short name T396
Test name
Test status
Simulation time 5693829670 ps
CPU time 27.81 seconds
Started Jul 25 04:46:56 PM PDT 24
Finished Jul 25 04:47:24 PM PDT 24
Peak memory 197308 kb
Host smart-559a3214-5b8e-45c4-9c8f-95e27bbcc4a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581971659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.581971659
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2821753154
Short name T201
Test name
Test status
Simulation time 259533356 ps
CPU time 0.9 seconds
Started Jul 25 04:46:52 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 197712 kb
Host smart-1a8e4c93-9cd0-421d-b25e-6f587e1bd8cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821753154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2821753154
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3103193585
Short name T131
Test name
Test status
Simulation time 289171029 ps
CPU time 1.15 seconds
Started Jul 25 04:47:13 PM PDT 24
Finished Jul 25 04:47:14 PM PDT 24
Peak memory 196620 kb
Host smart-9e8697d1-0d24-41be-8868-41fef6729c9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103193585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3103193585
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.128743939
Short name T612
Test name
Test status
Simulation time 182081801 ps
CPU time 1.46 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:45 PM PDT 24
Peak memory 197084 kb
Host smart-2c6ae6ca-e686-4cc3-9a3e-70a3e6b69759
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128743939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.128743939
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2470762287
Short name T441
Test name
Test status
Simulation time 95319003 ps
CPU time 1.63 seconds
Started Jul 25 04:46:55 PM PDT 24
Finished Jul 25 04:46:57 PM PDT 24
Peak memory 196572 kb
Host smart-78067da4-f9d1-4bf0-9fe1-d4ef13607e2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470762287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2470762287
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3284594960
Short name T413
Test name
Test status
Simulation time 42538095 ps
CPU time 1.02 seconds
Started Jul 25 04:47:20 PM PDT 24
Finished Jul 25 04:47:21 PM PDT 24
Peak memory 196244 kb
Host smart-c29ca999-4955-4af7-9edf-7ee292fdbdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284594960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3284594960
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3004834081
Short name T167
Test name
Test status
Simulation time 77483013 ps
CPU time 1.29 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 197488 kb
Host smart-b30f0a57-fdbb-4fd7-93b1-6997c51b299e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004834081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3004834081
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.217249508
Short name T505
Test name
Test status
Simulation time 2225217953 ps
CPU time 5.37 seconds
Started Jul 25 04:47:13 PM PDT 24
Finished Jul 25 04:47:18 PM PDT 24
Peak memory 198560 kb
Host smart-ca301b8a-7ae2-482e-8487-b3c98267823b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217249508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.217249508
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2236655095
Short name T345
Test name
Test status
Simulation time 175026148 ps
CPU time 0.92 seconds
Started Jul 25 04:47:19 PM PDT 24
Finished Jul 25 04:47:20 PM PDT 24
Peak memory 196960 kb
Host smart-3185ace3-cb01-46ee-9992-75247bfc1aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236655095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2236655095
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4283120188
Short name T298
Test name
Test status
Simulation time 53651359 ps
CPU time 0.97 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:05 PM PDT 24
Peak memory 196852 kb
Host smart-0c1cc53c-babe-400c-b121-003983002b6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283120188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4283120188
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3677512239
Short name T545
Test name
Test status
Simulation time 15877615413 ps
CPU time 145 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:49:38 PM PDT 24
Peak memory 198592 kb
Host smart-2c1d97cc-f94e-410b-88f7-a495877222c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677512239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3677512239
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.489382842
Short name T159
Test name
Test status
Simulation time 92534891 ps
CPU time 0.57 seconds
Started Jul 25 04:46:46 PM PDT 24
Finished Jul 25 04:46:47 PM PDT 24
Peak memory 194332 kb
Host smart-d9d3df4e-dee2-4a5d-8e0f-990d74d2ef20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489382842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.489382842
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3222501702
Short name T367
Test name
Test status
Simulation time 32503178 ps
CPU time 0.79 seconds
Started Jul 25 04:47:15 PM PDT 24
Finished Jul 25 04:47:16 PM PDT 24
Peak memory 196484 kb
Host smart-04ab7fd9-ee24-4757-b634-d31f3778a67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222501702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3222501702
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.662301832
Short name T682
Test name
Test status
Simulation time 637381196 ps
CPU time 5.35 seconds
Started Jul 25 04:46:44 PM PDT 24
Finished Jul 25 04:46:50 PM PDT 24
Peak memory 197436 kb
Host smart-f1aedb2e-b736-4216-af8c-53f6ec3ef101
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662301832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.662301832
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2182361370
Short name T266
Test name
Test status
Simulation time 217838381 ps
CPU time 0.88 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:47:00 PM PDT 24
Peak memory 196532 kb
Host smart-fe642b7c-77ea-4c1b-a6d7-e90b2503811f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182361370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2182361370
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2057801584
Short name T182
Test name
Test status
Simulation time 156878452 ps
CPU time 0.81 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:05 PM PDT 24
Peak memory 196000 kb
Host smart-32814b67-59d3-4cbe-84a4-9d2562f9f870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057801584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2057801584
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2042990982
Short name T618
Test name
Test status
Simulation time 174994181 ps
CPU time 2.87 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:41 PM PDT 24
Peak memory 198632 kb
Host smart-c522a2ba-992e-40e2-b05b-0a195cd2d94f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042990982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2042990982
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1442827659
Short name T475
Test name
Test status
Simulation time 1554851884 ps
CPU time 2.48 seconds
Started Jul 25 04:47:07 PM PDT 24
Finished Jul 25 04:47:09 PM PDT 24
Peak memory 197680 kb
Host smart-8e8c3180-b185-4d9c-9139-6114582a71c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442827659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1442827659
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.4250843690
Short name T254
Test name
Test status
Simulation time 94709911 ps
CPU time 1.06 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:47:00 PM PDT 24
Peak memory 196224 kb
Host smart-17957447-4407-4616-9bbd-1be1f8549131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250843690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.4250843690
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3787937369
Short name T196
Test name
Test status
Simulation time 91239084 ps
CPU time 1.06 seconds
Started Jul 25 04:47:23 PM PDT 24
Finished Jul 25 04:47:24 PM PDT 24
Peak memory 196464 kb
Host smart-102802d8-e6d4-48b9-8953-7df88b8c381c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787937369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3787937369
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.306692716
Short name T264
Test name
Test status
Simulation time 93795266 ps
CPU time 4.08 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:30 PM PDT 24
Peak memory 198436 kb
Host smart-3c709067-b84c-4390-802f-ef8df545ae00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306692716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.306692716
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2045359218
Short name T572
Test name
Test status
Simulation time 581521268 ps
CPU time 1.1 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:14 PM PDT 24
Peak memory 196316 kb
Host smart-5e25df97-c2f8-42da-83b9-4d88abcb521b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045359218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2045359218
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.821813785
Short name T425
Test name
Test status
Simulation time 78059763 ps
CPU time 1.06 seconds
Started Jul 25 04:46:57 PM PDT 24
Finished Jul 25 04:46:58 PM PDT 24
Peak memory 196052 kb
Host smart-7ad3548b-0b28-465f-b05d-c5288ea236f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821813785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.821813785
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3068490390
Short name T421
Test name
Test status
Simulation time 10405110957 ps
CPU time 120.19 seconds
Started Jul 25 04:46:50 PM PDT 24
Finished Jul 25 04:48:55 PM PDT 24
Peak memory 198608 kb
Host smart-87fd25c9-a323-4646-a04c-c7bfbbfc33b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068490390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3068490390
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1979884591
Short name T66
Test name
Test status
Simulation time 31166234771 ps
CPU time 890.44 seconds
Started Jul 25 04:46:51 PM PDT 24
Finished Jul 25 05:01:46 PM PDT 24
Peak memory 198736 kb
Host smart-f54b79a8-3215-4c76-8795-275039931e84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1979884591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1979884591
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2874765132
Short name T656
Test name
Test status
Simulation time 32101206 ps
CPU time 0.53 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 194388 kb
Host smart-3981cb32-e630-49b7-8963-bce1dece6de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874765132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2874765132
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2387941219
Short name T522
Test name
Test status
Simulation time 27210348 ps
CPU time 0.7 seconds
Started Jul 25 04:47:22 PM PDT 24
Finished Jul 25 04:47:23 PM PDT 24
Peak memory 194676 kb
Host smart-851342ff-609c-4c5e-aef1-c783dc66bc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387941219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2387941219
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1752300907
Short name T24
Test name
Test status
Simulation time 1461420073 ps
CPU time 12.53 seconds
Started Jul 25 04:46:40 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 197520 kb
Host smart-01176ea4-f540-456b-a1a1-7ba7d85fbc27
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752300907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1752300907
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1247131830
Short name T126
Test name
Test status
Simulation time 97535586 ps
CPU time 0.9 seconds
Started Jul 25 04:47:13 PM PDT 24
Finished Jul 25 04:47:14 PM PDT 24
Peak memory 196496 kb
Host smart-e20c3a4e-8974-4561-9564-a4387dbe3118
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247131830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1247131830
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4039285904
Short name T510
Test name
Test status
Simulation time 25027157 ps
CPU time 0.8 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:30 PM PDT 24
Peak memory 195860 kb
Host smart-a0879d57-8f35-449b-9c2f-42154a6c17a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039285904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4039285904
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3867818655
Short name T397
Test name
Test status
Simulation time 83026782 ps
CPU time 2.47 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:06 PM PDT 24
Peak memory 198588 kb
Host smart-103b69a3-e64d-4b6c-bdf6-a486bdb37680
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867818655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3867818655
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.670998304
Short name T690
Test name
Test status
Simulation time 1038759058 ps
CPU time 2.35 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:30 PM PDT 24
Peak memory 197556 kb
Host smart-9f80071e-f72c-4813-ae31-03c878de880a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670998304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
670998304
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.558248642
Short name T27
Test name
Test status
Simulation time 210601054 ps
CPU time 1.14 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:05 PM PDT 24
Peak memory 196600 kb
Host smart-72ba26a0-feeb-4e2c-ad86-ec9d0ab0f6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558248642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.558248642
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1490650861
Short name T189
Test name
Test status
Simulation time 84446260 ps
CPU time 1.1 seconds
Started Jul 25 04:46:57 PM PDT 24
Finished Jul 25 04:46:59 PM PDT 24
Peak memory 196360 kb
Host smart-cfafc876-90df-4e4e-9a01-7b7e0d5f13cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490650861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1490650861
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1550696372
Short name T461
Test name
Test status
Simulation time 24093687 ps
CPU time 1.12 seconds
Started Jul 25 04:46:42 PM PDT 24
Finished Jul 25 04:46:43 PM PDT 24
Peak memory 198452 kb
Host smart-61641fbb-8431-4c42-ae8a-7b799d8961ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550696372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1550696372
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2986529059
Short name T655
Test name
Test status
Simulation time 428549533 ps
CPU time 0.93 seconds
Started Jul 25 04:46:53 PM PDT 24
Finished Jul 25 04:46:54 PM PDT 24
Peak memory 196736 kb
Host smart-7993388a-c4b4-485e-93b4-81fc932eab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986529059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2986529059
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1918841869
Short name T366
Test name
Test status
Simulation time 153163208 ps
CPU time 1.09 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 196192 kb
Host smart-ffafc300-c8b5-4e14-bcef-4c38f4e593af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918841869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1918841869
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1090358771
Short name T587
Test name
Test status
Simulation time 8862956848 ps
CPU time 102.84 seconds
Started Jul 25 04:47:07 PM PDT 24
Finished Jul 25 04:48:50 PM PDT 24
Peak memory 198568 kb
Host smart-08c79733-c6c6-45fe-a250-c10b7577ac60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090358771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1090358771
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.932884839
Short name T627
Test name
Test status
Simulation time 15031447 ps
CPU time 0.57 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:47:00 PM PDT 24
Peak memory 194556 kb
Host smart-a2e9698d-e667-420b-bb5a-fdba88b296fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932884839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.932884839
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.4182616082
Short name T344
Test name
Test status
Simulation time 264520800 ps
CPU time 0.68 seconds
Started Jul 25 04:46:55 PM PDT 24
Finished Jul 25 04:47:00 PM PDT 24
Peak memory 195312 kb
Host smart-47cfc4ca-f37c-4161-8b7f-e55908741709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182616082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.4182616082
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3262204504
Short name T253
Test name
Test status
Simulation time 1090225954 ps
CPU time 10.81 seconds
Started Jul 25 04:47:48 PM PDT 24
Finished Jul 25 04:48:04 PM PDT 24
Peak memory 195912 kb
Host smart-69845cd3-9ffa-4ece-9657-37ce6228774f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262204504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3262204504
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.10121358
Short name T238
Test name
Test status
Simulation time 271846951 ps
CPU time 0.88 seconds
Started Jul 25 04:46:52 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 197560 kb
Host smart-2f05075d-bb7d-49ff-8036-6b3177cfb2c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10121358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.10121358
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3500755769
Short name T659
Test name
Test status
Simulation time 111525630 ps
CPU time 0.78 seconds
Started Jul 25 04:46:51 PM PDT 24
Finished Jul 25 04:46:52 PM PDT 24
Peak memory 196056 kb
Host smart-5610d117-487d-4cfa-9c2c-06082e247c1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500755769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3500755769
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.85510619
Short name T340
Test name
Test status
Simulation time 66519783 ps
CPU time 1.37 seconds
Started Jul 25 04:47:03 PM PDT 24
Finished Jul 25 04:47:04 PM PDT 24
Peak memory 198636 kb
Host smart-85d2548c-a253-482c-beb1-7c0a28bc5be9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85510619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.gpio_intr_with_filter_rand_intr_event.85510619
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3281880650
Short name T187
Test name
Test status
Simulation time 150120458 ps
CPU time 2.29 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:47:01 PM PDT 24
Peak memory 197444 kb
Host smart-d99b517b-2fe6-4ad9-951f-78ab96b13ca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281880650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3281880650
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.616884840
Short name T485
Test name
Test status
Simulation time 114568361 ps
CPU time 0.89 seconds
Started Jul 25 04:46:39 PM PDT 24
Finished Jul 25 04:46:40 PM PDT 24
Peak memory 196276 kb
Host smart-ea57f582-cb60-4a52-82b8-aa52a5183a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616884840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.616884840
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3392478251
Short name T528
Test name
Test status
Simulation time 228993047 ps
CPU time 1.06 seconds
Started Jul 25 04:46:58 PM PDT 24
Finished Jul 25 04:46:59 PM PDT 24
Peak memory 196564 kb
Host smart-7a89dd70-452b-4e09-acd5-868aeaa73c9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392478251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3392478251
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4088182776
Short name T8
Test name
Test status
Simulation time 2443823102 ps
CPU time 3.4 seconds
Started Jul 25 04:47:01 PM PDT 24
Finished Jul 25 04:47:05 PM PDT 24
Peak memory 198628 kb
Host smart-81b6cedf-66b0-42c2-a67d-1bb6254804ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088182776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4088182776
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2807204600
Short name T256
Test name
Test status
Simulation time 585207321 ps
CPU time 1.36 seconds
Started Jul 25 04:47:02 PM PDT 24
Finished Jul 25 04:47:03 PM PDT 24
Peak memory 196004 kb
Host smart-03205114-1f58-45b3-8b76-fbd6c733a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807204600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2807204600
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2822011739
Short name T604
Test name
Test status
Simulation time 628231276 ps
CPU time 1.08 seconds
Started Jul 25 04:47:06 PM PDT 24
Finished Jul 25 04:47:07 PM PDT 24
Peak memory 195992 kb
Host smart-7209a900-c2ec-4c05-94a1-84ee5690e936
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822011739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2822011739
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2084159237
Short name T639
Test name
Test status
Simulation time 4339538626 ps
CPU time 106.57 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 04:48:57 PM PDT 24
Peak memory 198576 kb
Host smart-633554dd-f51c-4e32-ae8f-cc7b5af77025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084159237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2084159237
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2611724429
Short name T456
Test name
Test status
Simulation time 123723566157 ps
CPU time 2377.07 seconds
Started Jul 25 04:47:06 PM PDT 24
Finished Jul 25 05:26:44 PM PDT 24
Peak memory 198768 kb
Host smart-5921004e-26d5-49fb-a40f-c0be300fc375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2611724429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2611724429
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2419539414
Short name T296
Test name
Test status
Simulation time 46477080 ps
CPU time 0.57 seconds
Started Jul 25 04:47:07 PM PDT 24
Finished Jul 25 04:47:07 PM PDT 24
Peak memory 194372 kb
Host smart-3438a856-2c98-43a8-a2e2-c12b076683e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419539414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2419539414
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.483946685
Short name T129
Test name
Test status
Simulation time 47359732 ps
CPU time 0.62 seconds
Started Jul 25 04:47:11 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 194500 kb
Host smart-a9a109da-bf85-4611-ad58-aca3e62b759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483946685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.483946685
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.546721717
Short name T150
Test name
Test status
Simulation time 194126183 ps
CPU time 6.11 seconds
Started Jul 25 04:47:21 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 198436 kb
Host smart-60b5833c-515f-4c39-8599-9606c3f44062
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546721717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.546721717
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3307975828
Short name T641
Test name
Test status
Simulation time 30414855 ps
CPU time 0.61 seconds
Started Jul 25 04:47:15 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 194908 kb
Host smart-6805bf3e-07b1-4600-a8c6-f751aa9115de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307975828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3307975828
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.818095580
Short name T531
Test name
Test status
Simulation time 138962357 ps
CPU time 1.08 seconds
Started Jul 25 04:47:11 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 196276 kb
Host smart-3ef8fee0-552a-47da-bd3c-999f75627a4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818095580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.818095580
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4193253876
Short name T624
Test name
Test status
Simulation time 60542970 ps
CPU time 2.22 seconds
Started Jul 25 04:47:02 PM PDT 24
Finished Jul 25 04:47:04 PM PDT 24
Peak memory 198552 kb
Host smart-0b570557-376c-45d2-b748-18a5dfa1c7c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193253876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4193253876
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4227446735
Short name T35
Test name
Test status
Simulation time 45313267 ps
CPU time 1.08 seconds
Started Jul 25 04:46:46 PM PDT 24
Finished Jul 25 04:46:47 PM PDT 24
Peak memory 196108 kb
Host smart-844dfb16-fc73-4c5d-9d17-4f9da89a7949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227446735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4227446735
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3686805017
Short name T173
Test name
Test status
Simulation time 124658058 ps
CPU time 0.89 seconds
Started Jul 25 04:47:08 PM PDT 24
Finished Jul 25 04:47:09 PM PDT 24
Peak memory 196596 kb
Host smart-b22dd957-b893-450e-8f0f-ed8102783b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686805017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3686805017
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3490719298
Short name T620
Test name
Test status
Simulation time 104609045 ps
CPU time 0.91 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:45 PM PDT 24
Peak memory 197588 kb
Host smart-5e27021f-7979-411a-b9f1-608ca0b0268f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490719298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3490719298
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.291494131
Short name T712
Test name
Test status
Simulation time 397921804 ps
CPU time 4.56 seconds
Started Jul 25 04:47:20 PM PDT 24
Finished Jul 25 04:47:24 PM PDT 24
Peak memory 198384 kb
Host smart-bcf85beb-0886-471a-8b4e-ed97caa1cf28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291494131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.291494131
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2586904202
Short name T530
Test name
Test status
Simulation time 44060974 ps
CPU time 0.91 seconds
Started Jul 25 04:47:07 PM PDT 24
Finished Jul 25 04:47:08 PM PDT 24
Peak memory 196696 kb
Host smart-f21d1685-b170-4d35-b7d5-e682d661c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586904202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2586904202
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3626572229
Short name T213
Test name
Test status
Simulation time 82659673 ps
CPU time 1.15 seconds
Started Jul 25 04:46:56 PM PDT 24
Finished Jul 25 04:46:57 PM PDT 24
Peak memory 196716 kb
Host smart-7e4e23ab-964a-4b43-ab8f-97799248e811
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626572229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3626572229
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.58503329
Short name T471
Test name
Test status
Simulation time 2898531596 ps
CPU time 75.5 seconds
Started Jul 25 04:47:17 PM PDT 24
Finished Jul 25 04:48:32 PM PDT 24
Peak memory 198540 kb
Host smart-adab411d-3965-4a6b-bf40-eaf7ebc1630d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58503329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gp
io_stress_all.58503329
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2946828031
Short name T450
Test name
Test status
Simulation time 68424120252 ps
CPU time 1521.19 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 05:12:32 PM PDT 24
Peak memory 198644 kb
Host smart-1b973eb4-21dc-48e9-9a19-bc9c3c1a6801
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2946828031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.2946828031
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3696272223
Short name T457
Test name
Test status
Simulation time 16034167 ps
CPU time 0.6 seconds
Started Jul 25 04:47:06 PM PDT 24
Finished Jul 25 04:47:07 PM PDT 24
Peak memory 195252 kb
Host smart-c5969205-34e7-4846-bd3a-1f6850f81880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696272223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3696272223
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2977205927
Short name T346
Test name
Test status
Simulation time 21321186 ps
CPU time 0.69 seconds
Started Jul 25 04:47:00 PM PDT 24
Finished Jul 25 04:47:01 PM PDT 24
Peak memory 195728 kb
Host smart-c5c37cdf-e1a1-4067-a3b1-589fc99cc6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977205927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2977205927
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.826046547
Short name T534
Test name
Test status
Simulation time 524950698 ps
CPU time 6.26 seconds
Started Jul 25 04:47:16 PM PDT 24
Finished Jul 25 04:47:23 PM PDT 24
Peak memory 198432 kb
Host smart-60d34d74-b939-4545-80ad-d36964db103f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826046547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.826046547
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2647284823
Short name T494
Test name
Test status
Simulation time 517364229 ps
CPU time 0.65 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:29 PM PDT 24
Peak memory 195464 kb
Host smart-da85a2ee-d462-4967-88f7-6c29a9125ee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647284823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2647284823
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1110487570
Short name T23
Test name
Test status
Simulation time 43504863 ps
CPU time 0.64 seconds
Started Jul 25 04:46:58 PM PDT 24
Finished Jul 25 04:46:59 PM PDT 24
Peak memory 195572 kb
Host smart-15eec76d-e4f5-4481-a658-5a95f650047c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110487570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1110487570
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1128644120
Short name T146
Test name
Test status
Simulation time 336507530 ps
CPU time 1.85 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:47:01 PM PDT 24
Peak memory 198488 kb
Host smart-96da9b10-1d46-4adb-9d5e-418e6bd44509
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128644120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1128644120
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2176492889
Short name T34
Test name
Test status
Simulation time 183103210 ps
CPU time 1.47 seconds
Started Jul 25 04:47:05 PM PDT 24
Finished Jul 25 04:47:06 PM PDT 24
Peak memory 196256 kb
Host smart-04b5b9b6-5562-4b93-bbf4-60d9d4d20519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176492889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2176492889
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2233796490
Short name T134
Test name
Test status
Simulation time 130071267 ps
CPU time 1.09 seconds
Started Jul 25 04:47:16 PM PDT 24
Finished Jul 25 04:47:17 PM PDT 24
Peak memory 197268 kb
Host smart-65a3ac59-ca19-4d22-925d-8ad4d6417c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233796490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2233796490
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.984846703
Short name T452
Test name
Test status
Simulation time 42584159 ps
CPU time 0.69 seconds
Started Jul 25 04:46:58 PM PDT 24
Finished Jul 25 04:46:59 PM PDT 24
Peak memory 194856 kb
Host smart-e72a61d8-c850-4363-a0a3-00fa30d06707
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984846703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.984846703
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1916210927
Short name T435
Test name
Test status
Simulation time 1433322975 ps
CPU time 3.13 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:47:02 PM PDT 24
Peak memory 198444 kb
Host smart-c5eaf9cf-22ac-48e2-9d4e-dffd9faf1ac3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916210927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1916210927
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.410209538
Short name T199
Test name
Test status
Simulation time 58724396 ps
CPU time 1.09 seconds
Started Jul 25 04:47:01 PM PDT 24
Finished Jul 25 04:47:03 PM PDT 24
Peak memory 196984 kb
Host smart-187a5f82-bdfb-4d47-bf4b-e9d3f3c2845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410209538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.410209538
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2007353047
Short name T212
Test name
Test status
Simulation time 259818685 ps
CPU time 1.25 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:45 PM PDT 24
Peak memory 197852 kb
Host smart-f67fb005-da66-45e6-9dc4-867f9b40bdd0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007353047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2007353047
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.500650835
Short name T317
Test name
Test status
Simulation time 29858868129 ps
CPU time 108.92 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:48:53 PM PDT 24
Peak memory 198684 kb
Host smart-fcc1b250-9eab-41ae-b3bf-168b3448794d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500650835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.500650835
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3376602513
Short name T184
Test name
Test status
Simulation time 31766804 ps
CPU time 0.58 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:44 PM PDT 24
Peak memory 194320 kb
Host smart-da859a72-11b6-4e3b-b0d9-0dc4c243dc75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376602513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3376602513
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3915144292
Short name T438
Test name
Test status
Simulation time 41289270 ps
CPU time 0.87 seconds
Started Jul 25 04:47:13 PM PDT 24
Finished Jul 25 04:47:14 PM PDT 24
Peak memory 197768 kb
Host smart-8a357047-de1b-4633-aa51-dd59ec78a30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915144292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3915144292
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2447358732
Short name T681
Test name
Test status
Simulation time 3040974277 ps
CPU time 10.13 seconds
Started Jul 25 04:46:52 PM PDT 24
Finished Jul 25 04:47:02 PM PDT 24
Peak memory 197044 kb
Host smart-b559b058-aa20-41ec-860c-2c417e9b2f7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447358732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2447358732
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1916771635
Short name T654
Test name
Test status
Simulation time 61894688 ps
CPU time 0.87 seconds
Started Jul 25 04:46:56 PM PDT 24
Finished Jul 25 04:46:57 PM PDT 24
Peak memory 197172 kb
Host smart-1fd47a95-8b54-4276-b827-242aed3dca3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916771635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1916771635
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2563301744
Short name T250
Test name
Test status
Simulation time 80947000 ps
CPU time 1.16 seconds
Started Jul 25 04:47:03 PM PDT 24
Finished Jul 25 04:47:04 PM PDT 24
Peak memory 196252 kb
Host smart-14705dd5-735f-4075-8790-5438614938a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563301744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2563301744
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4017753136
Short name T647
Test name
Test status
Simulation time 39323547 ps
CPU time 0.95 seconds
Started Jul 25 04:46:58 PM PDT 24
Finished Jul 25 04:46:59 PM PDT 24
Peak memory 196424 kb
Host smart-4e44173c-2bf2-4565-8932-b3327da35e73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017753136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4017753136
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1619884730
Short name T61
Test name
Test status
Simulation time 113732456 ps
CPU time 2.45 seconds
Started Jul 25 04:47:11 PM PDT 24
Finished Jul 25 04:47:14 PM PDT 24
Peak memory 197596 kb
Host smart-d5121bc7-fde5-4d05-bb9a-43992a2a0a73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619884730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1619884730
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2548824590
Short name T379
Test name
Test status
Simulation time 107357267 ps
CPU time 0.73 seconds
Started Jul 25 04:46:47 PM PDT 24
Finished Jul 25 04:46:48 PM PDT 24
Peak memory 195876 kb
Host smart-02a8ce5d-c735-4587-9991-0cae15b6ef23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548824590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2548824590
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.423293393
Short name T314
Test name
Test status
Simulation time 61451951 ps
CPU time 0.75 seconds
Started Jul 25 04:48:10 PM PDT 24
Finished Jul 25 04:48:11 PM PDT 24
Peak memory 196132 kb
Host smart-2be272c5-7c93-41d7-8c18-d486f3cacf56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423293393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.423293393
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1448763883
Short name T611
Test name
Test status
Simulation time 3052660371 ps
CPU time 6.02 seconds
Started Jul 25 04:46:58 PM PDT 24
Finished Jul 25 04:47:04 PM PDT 24
Peak memory 198500 kb
Host smart-5f954fdc-4baf-4673-a436-b7dee70a444e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448763883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1448763883
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3007014442
Short name T614
Test name
Test status
Simulation time 435330407 ps
CPU time 1.18 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:06 PM PDT 24
Peak memory 196128 kb
Host smart-458c40e1-c3a5-4a79-95be-d820d93a726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007014442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3007014442
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.559627523
Short name T495
Test name
Test status
Simulation time 264609480 ps
CPU time 1.03 seconds
Started Jul 25 04:46:54 PM PDT 24
Finished Jul 25 04:46:55 PM PDT 24
Peak memory 196248 kb
Host smart-002aedc5-9016-4773-86bd-bb7bc5131263
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559627523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.559627523
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.299827025
Short name T4
Test name
Test status
Simulation time 51584582054 ps
CPU time 146.92 seconds
Started Jul 25 04:47:01 PM PDT 24
Finished Jul 25 04:49:28 PM PDT 24
Peak memory 198568 kb
Host smart-5d2bc700-9b71-43cc-b398-d46d9b9200e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299827025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.299827025
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1403112472
Short name T194
Test name
Test status
Simulation time 14751027 ps
CPU time 0.57 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:44 PM PDT 24
Peak memory 194440 kb
Host smart-f677b05c-0f85-4220-98c8-0cf446b2e2aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403112472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1403112472
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2656710286
Short name T672
Test name
Test status
Simulation time 128443580 ps
CPU time 0.81 seconds
Started Jul 25 04:47:09 PM PDT 24
Finished Jul 25 04:47:10 PM PDT 24
Peak memory 195680 kb
Host smart-11a775f0-dd7a-4cf1-bf16-d9d01847dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656710286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2656710286
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3379207378
Short name T695
Test name
Test status
Simulation time 255261245 ps
CPU time 11.98 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:16 PM PDT 24
Peak memory 197344 kb
Host smart-b863f784-271d-4383-89ed-668e2e4e3e67
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379207378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3379207378
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.477794594
Short name T544
Test name
Test status
Simulation time 53642176 ps
CPU time 0.79 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:44 PM PDT 24
Peak memory 196412 kb
Host smart-cfc2e206-4469-4c2b-9fe7-f182bc88df83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477794594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.477794594
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.4126257289
Short name T232
Test name
Test status
Simulation time 76738654 ps
CPU time 0.69 seconds
Started Jul 25 04:47:02 PM PDT 24
Finished Jul 25 04:47:03 PM PDT 24
Peak memory 195552 kb
Host smart-dfc7673f-8b56-47e6-a69f-8df9213c56a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126257289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.4126257289
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3682411304
Short name T406
Test name
Test status
Simulation time 157530255 ps
CPU time 1.76 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 198564 kb
Host smart-1f8a9eda-bc41-4f44-aa53-8635e4001f83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682411304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3682411304
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3780074939
Short name T649
Test name
Test status
Simulation time 110111272 ps
CPU time 2.33 seconds
Started Jul 25 04:46:54 PM PDT 24
Finished Jul 25 04:46:56 PM PDT 24
Peak memory 197596 kb
Host smart-f40002c9-85b8-41e8-b792-dc47adbd002b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780074939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3780074939
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3114343389
Short name T661
Test name
Test status
Simulation time 194281684 ps
CPU time 1.07 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:42 PM PDT 24
Peak memory 196384 kb
Host smart-5e03e15b-0966-4c02-9ff8-096240457b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114343389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3114343389
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2634533554
Short name T152
Test name
Test status
Simulation time 141371806 ps
CPU time 0.92 seconds
Started Jul 25 04:47:17 PM PDT 24
Finished Jul 25 04:47:18 PM PDT 24
Peak memory 196532 kb
Host smart-0da3a6f9-474c-4c18-960f-95f65254c15c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634533554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2634533554
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1418240472
Short name T703
Test name
Test status
Simulation time 971173273 ps
CPU time 4.1 seconds
Started Jul 25 04:47:05 PM PDT 24
Finished Jul 25 04:47:14 PM PDT 24
Peak memory 198440 kb
Host smart-4e6fb272-c20b-4524-ab52-4569aaaef09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418240472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1418240472
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3778752692
Short name T248
Test name
Test status
Simulation time 43252659 ps
CPU time 0.98 seconds
Started Jul 25 04:47:06 PM PDT 24
Finished Jul 25 04:47:07 PM PDT 24
Peak memory 196184 kb
Host smart-af6e9b2b-ddc6-4c6e-8ff6-7a73f6e3593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778752692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3778752692
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3976186346
Short name T39
Test name
Test status
Simulation time 84911791 ps
CPU time 1.27 seconds
Started Jul 25 04:47:03 PM PDT 24
Finished Jul 25 04:47:05 PM PDT 24
Peak memory 197264 kb
Host smart-293293b5-374f-4d86-9e19-2148e413622c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976186346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3976186346
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2157852386
Short name T418
Test name
Test status
Simulation time 57662770353 ps
CPU time 143.83 seconds
Started Jul 25 04:47:47 PM PDT 24
Finished Jul 25 04:50:12 PM PDT 24
Peak memory 197568 kb
Host smart-02a948b1-cd2d-4d6d-8d00-9c0323c3b5bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157852386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2157852386
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3053503317
Short name T573
Test name
Test status
Simulation time 29540036 ps
CPU time 0.54 seconds
Started Jul 25 04:47:03 PM PDT 24
Finished Jul 25 04:47:04 PM PDT 24
Peak memory 195032 kb
Host smart-2367ea5d-8198-4729-bf7a-da1171050f25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053503317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3053503317
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2636996265
Short name T547
Test name
Test status
Simulation time 43300368 ps
CPU time 0.89 seconds
Started Jul 25 04:47:13 PM PDT 24
Finished Jul 25 04:47:14 PM PDT 24
Peak memory 197512 kb
Host smart-cf88e66b-625c-4394-8b25-7c8f735c68eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636996265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2636996265
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.97377645
Short name T542
Test name
Test status
Simulation time 227887066 ps
CPU time 10.2 seconds
Started Jul 25 04:47:01 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 197564 kb
Host smart-a548492a-1b20-4485-ad67-f85c1eaa84bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97377645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stress
.97377645
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3693334253
Short name T388
Test name
Test status
Simulation time 64197261 ps
CPU time 1 seconds
Started Jul 25 04:46:45 PM PDT 24
Finished Jul 25 04:46:51 PM PDT 24
Peak memory 196856 kb
Host smart-43f920ef-6061-4917-9222-7ac073c8c6bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693334253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3693334253
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1036098870
Short name T285
Test name
Test status
Simulation time 38309828 ps
CPU time 0.91 seconds
Started Jul 25 04:46:39 PM PDT 24
Finished Jul 25 04:46:40 PM PDT 24
Peak memory 197040 kb
Host smart-266d66e9-f021-4e91-b647-87d3cc0b013b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036098870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1036098870
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.538065876
Short name T669
Test name
Test status
Simulation time 80904663 ps
CPU time 3.02 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 04:47:37 PM PDT 24
Peak memory 198488 kb
Host smart-58f375f5-4da5-432c-9537-abdbfce860d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538065876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.538065876
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2894448043
Short name T269
Test name
Test status
Simulation time 50189819 ps
CPU time 1.56 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 197268 kb
Host smart-d6de869d-5815-4e66-b112-f19f3cf40e37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894448043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2894448043
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.203271743
Short name T18
Test name
Test status
Simulation time 56270312 ps
CPU time 0.62 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 195404 kb
Host smart-3dfed4a7-4000-4095-bac5-d05be108e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203271743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.203271743
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1118210181
Short name T478
Test name
Test status
Simulation time 49899704 ps
CPU time 0.95 seconds
Started Jul 25 04:47:19 PM PDT 24
Finished Jul 25 04:47:21 PM PDT 24
Peak memory 196468 kb
Host smart-4053e4c9-953f-4f29-9cae-c4d488444921
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118210181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1118210181
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2316043000
Short name T110
Test name
Test status
Simulation time 361898895 ps
CPU time 5.36 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 198516 kb
Host smart-52dde788-2c6e-4d93-88ab-ec5340cd40d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316043000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2316043000
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3608553249
Short name T265
Test name
Test status
Simulation time 222780150 ps
CPU time 1.19 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:47:00 PM PDT 24
Peak memory 197316 kb
Host smart-d9bb71f2-0073-4a7b-bf35-2f4526653b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608553249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3608553249
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1992975367
Short name T622
Test name
Test status
Simulation time 54346689 ps
CPU time 1.04 seconds
Started Jul 25 04:47:14 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 195980 kb
Host smart-d8d20511-92a8-4ac7-aee5-233e980251f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992975367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1992975367
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1605073067
Short name T257
Test name
Test status
Simulation time 2693871865 ps
CPU time 33.64 seconds
Started Jul 25 04:47:16 PM PDT 24
Finished Jul 25 04:47:50 PM PDT 24
Peak memory 198536 kb
Host smart-cbb3c284-baa0-4914-8454-fb0f70607fc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605073067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1605073067
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.225242607
Short name T352
Test name
Test status
Simulation time 14088352 ps
CPU time 0.53 seconds
Started Jul 25 04:46:04 PM PDT 24
Finished Jul 25 04:46:05 PM PDT 24
Peak memory 194384 kb
Host smart-90dfbd96-53cf-470d-ba10-7d69787bd508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225242607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.225242607
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3956594081
Short name T400
Test name
Test status
Simulation time 104507905 ps
CPU time 0.72 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:21 PM PDT 24
Peak memory 195700 kb
Host smart-2cd48be4-084d-4a6b-810a-7a78e0a5dc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956594081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3956594081
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3421968329
Short name T223
Test name
Test status
Simulation time 531604572 ps
CPU time 20.13 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:46 PM PDT 24
Peak memory 197060 kb
Host smart-1f3f9c8d-c641-4daf-ae78-094bfde51b13
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421968329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3421968329
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.4013433442
Short name T300
Test name
Test status
Simulation time 37832884 ps
CPU time 0.72 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 195328 kb
Host smart-bc8078fb-26c8-4fb8-b060-0956cd0c131a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013433442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.4013433442
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.438718872
Short name T261
Test name
Test status
Simulation time 161372799 ps
CPU time 0.83 seconds
Started Jul 25 04:46:14 PM PDT 24
Finished Jul 25 04:46:16 PM PDT 24
Peak memory 195936 kb
Host smart-b39e1e86-82e3-4ba8-aacf-ee105ce22f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438718872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.438718872
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.241098342
Short name T417
Test name
Test status
Simulation time 745794898 ps
CPU time 1.59 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 196960 kb
Host smart-cac77057-7a02-4bbd-ba31-3f13bba9b535
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241098342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.241098342
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1739744629
Short name T56
Test name
Test status
Simulation time 35861909 ps
CPU time 1.07 seconds
Started Jul 25 04:46:07 PM PDT 24
Finished Jul 25 04:46:09 PM PDT 24
Peak memory 195932 kb
Host smart-7804ec77-a9a5-43cf-a70a-d3b0c738a4b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739744629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1739744629
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2900385001
Short name T384
Test name
Test status
Simulation time 127579765 ps
CPU time 0.84 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 197752 kb
Host smart-713b0439-2423-4e62-87d8-a1f953140faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900385001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2900385001
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2360764399
Short name T570
Test name
Test status
Simulation time 572491626 ps
CPU time 1.04 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 196412 kb
Host smart-2547f697-f1d3-4fe2-b0ab-45196107a731
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360764399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2360764399
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2014509814
Short name T185
Test name
Test status
Simulation time 231146147 ps
CPU time 5 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 198444 kb
Host smart-c1534da0-bd15-40f6-8070-cd0aa4f06b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014509814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2014509814
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2658928670
Short name T54
Test name
Test status
Simulation time 108193230 ps
CPU time 0.79 seconds
Started Jul 25 04:46:27 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 214432 kb
Host smart-0c97b9e1-d609-4669-a038-b7f2f13b6d43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658928670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2658928670
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3992595064
Short name T523
Test name
Test status
Simulation time 28745957 ps
CPU time 0.91 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 196256 kb
Host smart-589c9d8b-d22f-4170-b97b-0cf0aedbf9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992595064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3992595064
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.627794865
Short name T637
Test name
Test status
Simulation time 56085847 ps
CPU time 1.36 seconds
Started Jul 25 04:46:27 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 197084 kb
Host smart-f8672bfa-747e-4997-97b7-d57841886382
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627794865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.627794865
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3081209744
Short name T451
Test name
Test status
Simulation time 46547038332 ps
CPU time 122.27 seconds
Started Jul 25 04:46:27 PM PDT 24
Finished Jul 25 04:48:30 PM PDT 24
Peak memory 198608 kb
Host smart-2a909a9e-af8c-49ac-8d3c-3ef3b407eddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081209744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3081209744
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2327345159
Short name T16
Test name
Test status
Simulation time 41889555 ps
CPU time 0.57 seconds
Started Jul 25 04:47:14 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 195184 kb
Host smart-3fae774e-13d8-4ccd-807a-3073bb2c19b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327345159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2327345159
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.4048348293
Short name T480
Test name
Test status
Simulation time 31554464 ps
CPU time 0.85 seconds
Started Jul 25 04:47:15 PM PDT 24
Finished Jul 25 04:47:16 PM PDT 24
Peak memory 197140 kb
Host smart-33041a66-7ff2-4fec-ad01-e0c33d24cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048348293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.4048348293
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2697349590
Short name T32
Test name
Test status
Simulation time 3852436826 ps
CPU time 27.34 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:40 PM PDT 24
Peak memory 198548 kb
Host smart-ede4cd65-eeac-48e8-beb6-f435088cd2f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697349590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2697349590
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.459799698
Short name T191
Test name
Test status
Simulation time 111729214 ps
CPU time 0.67 seconds
Started Jul 25 04:47:11 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 195724 kb
Host smart-f9167c15-b11a-4b54-8c4a-4b858d942639
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459799698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.459799698
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1601716626
Short name T454
Test name
Test status
Simulation time 387910075 ps
CPU time 0.77 seconds
Started Jul 25 04:47:19 PM PDT 24
Finished Jul 25 04:47:20 PM PDT 24
Peak memory 195940 kb
Host smart-ecb7e85f-4c9b-45b3-a804-888ed2c620ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601716626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1601716626
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.102565341
Short name T551
Test name
Test status
Simulation time 62761499 ps
CPU time 2.29 seconds
Started Jul 25 04:46:53 PM PDT 24
Finished Jul 25 04:46:56 PM PDT 24
Peak memory 198548 kb
Host smart-72c1e9bb-496e-40a9-833c-e153b19dbce4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102565341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.102565341
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2531730434
Short name T500
Test name
Test status
Simulation time 566495569 ps
CPU time 3.16 seconds
Started Jul 25 04:47:01 PM PDT 24
Finished Jul 25 04:47:04 PM PDT 24
Peak memory 196976 kb
Host smart-c415cd1b-a868-4d35-a457-86c0041ceaa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531730434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2531730434
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.4259670186
Short name T357
Test name
Test status
Simulation time 41375684 ps
CPU time 1.02 seconds
Started Jul 25 04:47:19 PM PDT 24
Finished Jul 25 04:47:20 PM PDT 24
Peak memory 197232 kb
Host smart-612e4069-1927-4311-ac5e-5474c98b7436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259670186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.4259670186
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3702878310
Short name T486
Test name
Test status
Simulation time 80293252 ps
CPU time 0.9 seconds
Started Jul 25 04:47:09 PM PDT 24
Finished Jul 25 04:47:10 PM PDT 24
Peak memory 196496 kb
Host smart-60f7e82e-8899-4a4f-b95c-a05f19f099f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702878310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3702878310
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1471849377
Short name T561
Test name
Test status
Simulation time 297456220 ps
CPU time 4.9 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 198556 kb
Host smart-024c11eb-dd0e-4c17-b23b-7a126ca6779a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471849377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1471849377
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1910083473
Short name T399
Test name
Test status
Simulation time 37939614 ps
CPU time 1.19 seconds
Started Jul 25 04:46:54 PM PDT 24
Finished Jul 25 04:46:55 PM PDT 24
Peak memory 198496 kb
Host smart-b4d617a3-08db-4269-8115-c54a0fbca5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910083473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1910083473
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2782577719
Short name T429
Test name
Test status
Simulation time 507372639 ps
CPU time 1.13 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 196720 kb
Host smart-2c2b950a-5c58-4218-b872-a623cacdf507
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782577719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2782577719
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3392557031
Short name T424
Test name
Test status
Simulation time 16981971607 ps
CPU time 54.98 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:48:25 PM PDT 24
Peak memory 198464 kb
Host smart-90fd1f21-4efc-402f-b0ee-28a40e85b895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392557031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3392557031
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.4205968159
Short name T538
Test name
Test status
Simulation time 21947132 ps
CPU time 0.56 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:26 PM PDT 24
Peak memory 194600 kb
Host smart-f188f489-ca0f-4363-8ec8-776dcf13a8ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205968159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4205968159
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1254638273
Short name T161
Test name
Test status
Simulation time 13924395 ps
CPU time 0.66 seconds
Started Jul 25 04:47:16 PM PDT 24
Finished Jul 25 04:47:17 PM PDT 24
Peak memory 195196 kb
Host smart-2fe6ab73-9adf-4431-a6d8-aac3f3c0fc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254638273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1254638273
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.705972759
Short name T481
Test name
Test status
Simulation time 987998994 ps
CPU time 12.24 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:38 PM PDT 24
Peak memory 197652 kb
Host smart-cd0d0344-49ec-4b16-980d-fdcbf0cb62d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705972759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.705972759
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2138200572
Short name T222
Test name
Test status
Simulation time 62614253 ps
CPU time 0.84 seconds
Started Jul 25 04:47:05 PM PDT 24
Finished Jul 25 04:47:06 PM PDT 24
Peak memory 196504 kb
Host smart-634e9586-3f48-41e7-9a6e-cd80d5d97a29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138200572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2138200572
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3045313546
Short name T516
Test name
Test status
Simulation time 67531959 ps
CPU time 1.1 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 197236 kb
Host smart-7a277750-cee8-43a3-be3c-983ec714d98b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045313546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3045313546
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.491573878
Short name T665
Test name
Test status
Simulation time 187124626 ps
CPU time 1.89 seconds
Started Jul 25 04:47:15 PM PDT 24
Finished Jul 25 04:47:17 PM PDT 24
Peak memory 198472 kb
Host smart-ddb4a78d-7474-47e5-9119-4f423e3f2eb5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491573878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.491573878
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2094976951
Short name T273
Test name
Test status
Simulation time 122526044 ps
CPU time 1.37 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 196456 kb
Host smart-48b8b9ea-ca68-4dcf-8a82-39ea880cdd85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094976951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2094976951
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1523106428
Short name T283
Test name
Test status
Simulation time 33524910 ps
CPU time 1.26 seconds
Started Jul 25 04:46:56 PM PDT 24
Finished Jul 25 04:47:03 PM PDT 24
Peak memory 197512 kb
Host smart-0c149e56-b341-44b0-b285-1034c3b24b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523106428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1523106428
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.81996812
Short name T387
Test name
Test status
Simulation time 23393164 ps
CPU time 0.76 seconds
Started Jul 25 04:46:58 PM PDT 24
Finished Jul 25 04:47:04 PM PDT 24
Peak memory 195756 kb
Host smart-9ac96335-b6b4-4bf1-9448-2a371300107b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81996812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup_
pulldown.81996812
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3872779995
Short name T302
Test name
Test status
Simulation time 2232396699 ps
CPU time 5.52 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:09 PM PDT 24
Peak memory 198604 kb
Host smart-bc736cc1-e558-4b35-a17f-a6cc2836595a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872779995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3872779995
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.87337705
Short name T599
Test name
Test status
Simulation time 119744604 ps
CPU time 0.9 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:26 PM PDT 24
Peak memory 196096 kb
Host smart-a35dc098-38f2-4c7e-b943-36b3887baf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87337705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.87337705
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.4200714045
Short name T209
Test name
Test status
Simulation time 32239560 ps
CPU time 1 seconds
Started Jul 25 04:47:19 PM PDT 24
Finished Jul 25 04:47:20 PM PDT 24
Peak memory 196168 kb
Host smart-08cea172-439f-4715-a3e8-06b5c3548b7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200714045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.4200714045
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3170539707
Short name T546
Test name
Test status
Simulation time 13189151724 ps
CPU time 88.65 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:48:41 PM PDT 24
Peak memory 198604 kb
Host smart-ef598d18-f56b-4593-b669-26be9149d978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170539707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3170539707
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2797741023
Short name T365
Test name
Test status
Simulation time 22762068 ps
CPU time 0.57 seconds
Started Jul 25 04:47:22 PM PDT 24
Finished Jul 25 04:47:23 PM PDT 24
Peak memory 194316 kb
Host smart-90e061f1-6548-4cea-820f-3533aae72e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797741023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2797741023
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2047098492
Short name T422
Test name
Test status
Simulation time 36453932 ps
CPU time 0.68 seconds
Started Jul 25 04:47:06 PM PDT 24
Finished Jul 25 04:47:07 PM PDT 24
Peak memory 195636 kb
Host smart-727c1d40-d856-4057-9d9b-bfeab8312eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047098492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2047098492
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1033186997
Short name T469
Test name
Test status
Simulation time 237836997 ps
CPU time 8.16 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 197300 kb
Host smart-6334f6c8-0c14-4258-83ea-a0dcf34626ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033186997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1033186997
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3310131875
Short name T123
Test name
Test status
Simulation time 123555855 ps
CPU time 0.88 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 196524 kb
Host smart-71d04176-0499-42f4-a489-cdc88dcbe8c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310131875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3310131875
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.131920113
Short name T670
Test name
Test status
Simulation time 23806431 ps
CPU time 0.81 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 04:47:05 PM PDT 24
Peak memory 196620 kb
Host smart-f970e12f-4c30-416d-a52d-5fc5e9db3e95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131920113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.131920113
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2292136875
Short name T325
Test name
Test status
Simulation time 37075858 ps
CPU time 1.57 seconds
Started Jul 25 04:47:01 PM PDT 24
Finished Jul 25 04:47:03 PM PDT 24
Peak memory 196992 kb
Host smart-ce98f869-0611-4abb-9989-61f278a8eb54
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292136875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2292136875
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.4153817389
Short name T164
Test name
Test status
Simulation time 204719678 ps
CPU time 1.38 seconds
Started Jul 25 04:47:01 PM PDT 24
Finished Jul 25 04:47:03 PM PDT 24
Peak memory 196688 kb
Host smart-8eb065bf-a930-4527-8d31-080aa3cf0a94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153817389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.4153817389
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.897075923
Short name T105
Test name
Test status
Simulation time 28009850 ps
CPU time 0.69 seconds
Started Jul 25 04:47:09 PM PDT 24
Finished Jul 25 04:47:10 PM PDT 24
Peak memory 194664 kb
Host smart-79d866cd-be1b-4bf1-88be-4ec0eba0ace1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897075923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.897075923
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2140366904
Short name T653
Test name
Test status
Simulation time 149783922 ps
CPU time 0.95 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 196976 kb
Host smart-1f1d4d2a-af5c-4a95-9734-955460a26aaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140366904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2140366904
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3626574571
Short name T172
Test name
Test status
Simulation time 120479735 ps
CPU time 1.13 seconds
Started Jul 25 04:47:09 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 198452 kb
Host smart-4b44789b-c713-4a4e-89fd-944f8f9bf89a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626574571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3626574571
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.755361133
Short name T482
Test name
Test status
Simulation time 49842809 ps
CPU time 1.23 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 197580 kb
Host smart-c516a8d8-e5d3-46da-8555-8c35095aeecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755361133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.755361133
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2549999899
Short name T169
Test name
Test status
Simulation time 137288661 ps
CPU time 0.96 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 196132 kb
Host smart-3ad14ac0-9f2b-4f14-aa2a-d3d33e46f0d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549999899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2549999899
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1941468397
Short name T290
Test name
Test status
Simulation time 28009686391 ps
CPU time 201.96 seconds
Started Jul 25 04:47:14 PM PDT 24
Finished Jul 25 04:50:37 PM PDT 24
Peak memory 198652 kb
Host smart-6041eedb-62eb-467b-8c55-fcc584c474b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941468397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1941468397
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.678791724
Short name T224
Test name
Test status
Simulation time 65401728 ps
CPU time 0.56 seconds
Started Jul 25 04:46:59 PM PDT 24
Finished Jul 25 04:46:59 PM PDT 24
Peak memory 195068 kb
Host smart-2186cb17-0267-45df-b200-d5c44aabaa3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678791724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.678791724
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2793240010
Short name T465
Test name
Test status
Simulation time 219888803 ps
CPU time 0.69 seconds
Started Jul 25 04:47:16 PM PDT 24
Finished Jul 25 04:47:17 PM PDT 24
Peak memory 194496 kb
Host smart-0a167a15-629d-44fe-bc62-609419941c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793240010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2793240010
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1183392409
Short name T552
Test name
Test status
Simulation time 680601259 ps
CPU time 17.09 seconds
Started Jul 25 04:46:58 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 197696 kb
Host smart-3595b904-46e3-494f-95b3-39162ded98fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183392409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1183392409
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1285284029
Short name T339
Test name
Test status
Simulation time 265668456 ps
CPU time 0.86 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 198128 kb
Host smart-63b4a6fc-dc15-4199-9f0e-2fe99daf939f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285284029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1285284029
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1152489558
Short name T634
Test name
Test status
Simulation time 553239961 ps
CPU time 0.84 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 196700 kb
Host smart-d081b031-fbd3-4156-acbb-b0685a70a254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152489558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1152489558
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.86954054
Short name T610
Test name
Test status
Simulation time 523035307 ps
CPU time 2.04 seconds
Started Jul 25 04:47:08 PM PDT 24
Finished Jul 25 04:47:10 PM PDT 24
Peak memory 198452 kb
Host smart-a189567d-7b28-4840-a98a-5de2bb078dfe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86954054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.gpio_intr_with_filter_rand_intr_event.86954054
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3376713875
Short name T499
Test name
Test status
Simulation time 604027733 ps
CPU time 2.04 seconds
Started Jul 25 04:47:08 PM PDT 24
Finished Jul 25 04:47:20 PM PDT 24
Peak memory 197648 kb
Host smart-e6481b5a-032e-4430-a7af-6bced1c10a24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376713875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3376713875
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1667877761
Short name T211
Test name
Test status
Simulation time 37604403 ps
CPU time 0.79 seconds
Started Jul 25 04:47:21 PM PDT 24
Finished Jul 25 04:47:22 PM PDT 24
Peak memory 195852 kb
Host smart-96b819ea-709f-4082-8c2c-542f1f96e168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667877761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1667877761
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3298255073
Short name T208
Test name
Test status
Simulation time 74104337 ps
CPU time 0.68 seconds
Started Jul 25 04:46:56 PM PDT 24
Finished Jul 25 04:46:57 PM PDT 24
Peak memory 195512 kb
Host smart-bad94636-ff3c-4834-87ce-6e5014ce8040
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298255073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3298255073
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2155671733
Short name T311
Test name
Test status
Simulation time 146652480 ps
CPU time 4.54 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:17 PM PDT 24
Peak memory 198424 kb
Host smart-e9a63fc1-dda0-4779-8113-2285ba30fcdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155671733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2155671733
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.4169946719
Short name T502
Test name
Test status
Simulation time 152476768 ps
CPU time 0.93 seconds
Started Jul 25 04:47:21 PM PDT 24
Finished Jul 25 04:47:22 PM PDT 24
Peak memory 195808 kb
Host smart-4cd6db63-c2f8-41fc-ae05-786b969aa688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169946719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.4169946719
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1666154053
Short name T293
Test name
Test status
Simulation time 78948109 ps
CPU time 1.04 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 197308 kb
Host smart-cc62d965-f32f-48e0-9e07-0b94d59a8f6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666154053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1666154053
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3279899071
Short name T25
Test name
Test status
Simulation time 3142892649 ps
CPU time 42.54 seconds
Started Jul 25 04:47:00 PM PDT 24
Finished Jul 25 04:47:43 PM PDT 24
Peak memory 198516 kb
Host smart-433cff36-505b-40bc-b0f7-8918199e5eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279899071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3279899071
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.775978654
Short name T68
Test name
Test status
Simulation time 507888195672 ps
CPU time 1775.66 seconds
Started Jul 25 04:47:04 PM PDT 24
Finished Jul 25 05:16:40 PM PDT 24
Peak memory 198696 kb
Host smart-9608f9a5-70ea-4ea9-b5ca-757617810f80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=775978654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.775978654
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3064531401
Short name T423
Test name
Test status
Simulation time 22401775 ps
CPU time 0.54 seconds
Started Jul 25 04:47:15 PM PDT 24
Finished Jul 25 04:47:16 PM PDT 24
Peak memory 194352 kb
Host smart-fdbab8b8-0bc9-470c-8f23-e6a24d2bbfa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064531401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3064531401
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1276404105
Short name T515
Test name
Test status
Simulation time 154396511 ps
CPU time 0.92 seconds
Started Jul 25 04:47:15 PM PDT 24
Finished Jul 25 04:47:16 PM PDT 24
Peak memory 195836 kb
Host smart-0129d12b-b25a-4a41-b7ba-263d230b4c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276404105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1276404105
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2745433788
Short name T342
Test name
Test status
Simulation time 459121518 ps
CPU time 23.33 seconds
Started Jul 25 04:47:11 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 195980 kb
Host smart-9dd80356-3447-4d03-b68d-f5eb8343e4ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745433788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2745433788
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2910358007
Short name T109
Test name
Test status
Simulation time 35542182 ps
CPU time 0.78 seconds
Started Jul 25 04:47:14 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 195184 kb
Host smart-c7fbbeb1-bb5c-41ee-adac-87b62ec4ee64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910358007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2910358007
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.4050840385
Short name T407
Test name
Test status
Simulation time 64881850 ps
CPU time 0.65 seconds
Started Jul 25 04:47:13 PM PDT 24
Finished Jul 25 04:47:14 PM PDT 24
Peak memory 194636 kb
Host smart-998ca194-d697-4185-9c2e-60b3b44afcb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050840385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.4050840385
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1438571814
Short name T698
Test name
Test status
Simulation time 48076716 ps
CPU time 1.94 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:28 PM PDT 24
Peak memory 198432 kb
Host smart-c3850867-a6c8-449e-9964-5e5f5568ca86
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438571814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1438571814
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.428545003
Short name T348
Test name
Test status
Simulation time 104018387 ps
CPU time 2.34 seconds
Started Jul 25 04:47:22 PM PDT 24
Finished Jul 25 04:47:24 PM PDT 24
Peak memory 197544 kb
Host smart-44cde3c5-ac6d-4fb0-860d-169f71c51465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428545003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
428545003
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2742407831
Short name T529
Test name
Test status
Simulation time 60351960 ps
CPU time 0.79 seconds
Started Jul 25 04:47:23 PM PDT 24
Finished Jul 25 04:47:24 PM PDT 24
Peak memory 196496 kb
Host smart-d5368954-69ab-4844-964b-5e8729ab1da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742407831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2742407831
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4170787098
Short name T22
Test name
Test status
Simulation time 47133341 ps
CPU time 0.72 seconds
Started Jul 25 04:47:20 PM PDT 24
Finished Jul 25 04:47:21 PM PDT 24
Peak memory 195844 kb
Host smart-789d4062-fbd7-464a-8af1-4bbc7226ee60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170787098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4170787098
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2778536992
Short name T437
Test name
Test status
Simulation time 100617744 ps
CPU time 1.14 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:33 PM PDT 24
Peak memory 196916 kb
Host smart-57fce822-8edc-431f-b9d4-21423b8f1468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778536992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2778536992
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3892929578
Short name T347
Test name
Test status
Simulation time 67561431 ps
CPU time 0.82 seconds
Started Jul 25 04:47:15 PM PDT 24
Finished Jul 25 04:47:16 PM PDT 24
Peak memory 195780 kb
Host smart-b0ddd958-0781-4a21-9108-022b6793c5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892929578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3892929578
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3754226231
Short name T31
Test name
Test status
Simulation time 143889213 ps
CPU time 1.05 seconds
Started Jul 25 04:47:12 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 196836 kb
Host smart-703e29d0-01f2-4e0d-aa7e-afc3c228ece8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754226231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3754226231
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.602888685
Short name T113
Test name
Test status
Simulation time 31880419192 ps
CPU time 195.34 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:50:41 PM PDT 24
Peak memory 198592 kb
Host smart-755b8d47-11d7-4e75-8d80-d860230d337e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602888685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.602888685
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3838804355
Short name T69
Test name
Test status
Simulation time 15034093940 ps
CPU time 255.77 seconds
Started Jul 25 04:47:21 PM PDT 24
Finished Jul 25 04:51:37 PM PDT 24
Peak memory 198796 kb
Host smart-399225d2-2d39-48b9-997a-fd09c1d53dcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3838804355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3838804355
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2968021181
Short name T193
Test name
Test status
Simulation time 56027406 ps
CPU time 0.53 seconds
Started Jul 25 04:47:24 PM PDT 24
Finished Jul 25 04:47:25 PM PDT 24
Peak memory 194344 kb
Host smart-ceb7d6a2-7eea-4f35-a3b5-8edb535bf599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968021181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2968021181
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3655649865
Short name T391
Test name
Test status
Simulation time 28097899 ps
CPU time 0.75 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 194560 kb
Host smart-e2c4b252-9c1c-4a35-b784-e284bdf68974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655649865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3655649865
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2580969099
Short name T321
Test name
Test status
Simulation time 579146702 ps
CPU time 19.71 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:50 PM PDT 24
Peak memory 198476 kb
Host smart-4e1052ee-dd87-47f5-ac1c-56121a1c18e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580969099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2580969099
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3794400760
Short name T255
Test name
Test status
Simulation time 26717081 ps
CPU time 0.69 seconds
Started Jul 25 04:47:18 PM PDT 24
Finished Jul 25 04:47:18 PM PDT 24
Peak memory 194904 kb
Host smart-e776d123-ff24-4a98-804a-563c8bc7761a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794400760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3794400760
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2472569857
Short name T274
Test name
Test status
Simulation time 173772778 ps
CPU time 1.13 seconds
Started Jul 25 04:47:06 PM PDT 24
Finished Jul 25 04:47:07 PM PDT 24
Peak memory 196556 kb
Host smart-6272a27c-e00d-484d-bf15-6ece646eb1d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472569857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2472569857
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3198969270
Short name T558
Test name
Test status
Simulation time 696973802 ps
CPU time 1.83 seconds
Started Jul 25 04:47:11 PM PDT 24
Finished Jul 25 04:47:13 PM PDT 24
Peak memory 196332 kb
Host smart-13ff73e6-372f-4dfa-8fae-f7ec5ae69673
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198969270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3198969270
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3387257741
Short name T58
Test name
Test status
Simulation time 39225777 ps
CPU time 0.72 seconds
Started Jul 25 04:47:17 PM PDT 24
Finished Jul 25 04:47:18 PM PDT 24
Peak memory 195728 kb
Host smart-6c5648b8-bf2a-4043-919d-ef5b654d9f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387257741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3387257741
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1294261692
Short name T562
Test name
Test status
Simulation time 97630673 ps
CPU time 1.01 seconds
Started Jul 25 04:47:15 PM PDT 24
Finished Jul 25 04:47:16 PM PDT 24
Peak memory 196432 kb
Host smart-d7f177bc-2a6c-4f3e-bb72-98bb700e7d71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294261692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1294261692
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2963152482
Short name T270
Test name
Test status
Simulation time 83517232 ps
CPU time 3.8 seconds
Started Jul 25 04:47:18 PM PDT 24
Finished Jul 25 04:47:22 PM PDT 24
Peak memory 198508 kb
Host smart-000d9853-18c3-4ca6-94ec-529a67eca6a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963152482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2963152482
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3038961436
Short name T420
Test name
Test status
Simulation time 77356865 ps
CPU time 1.28 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:47:39 PM PDT 24
Peak memory 197184 kb
Host smart-a2280a1b-c7d4-44dd-8f72-c719254574e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038961436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3038961436
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1251226376
Short name T358
Test name
Test status
Simulation time 60873407 ps
CPU time 1.08 seconds
Started Jul 25 04:47:15 PM PDT 24
Finished Jul 25 04:47:16 PM PDT 24
Peak memory 196300 kb
Host smart-30bdf908-1815-4fc7-b37c-cd8fac0c95bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251226376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1251226376
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4268582913
Short name T115
Test name
Test status
Simulation time 2991527901 ps
CPU time 24.51 seconds
Started Jul 25 04:47:18 PM PDT 24
Finished Jul 25 04:47:43 PM PDT 24
Peak memory 198632 kb
Host smart-b750a001-2c8a-4284-91b6-2407f98f42ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268582913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4268582913
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3425935297
Short name T713
Test name
Test status
Simulation time 45639501 ps
CPU time 0.57 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 195244 kb
Host smart-d9e79299-6ba1-4b0f-ad75-e5dcbb31a0d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425935297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3425935297
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1977018250
Short name T234
Test name
Test status
Simulation time 97615661 ps
CPU time 0.68 seconds
Started Jul 25 04:47:09 PM PDT 24
Finished Jul 25 04:47:10 PM PDT 24
Peak memory 196244 kb
Host smart-c7b41967-5d75-45d1-b85b-e74aad557f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977018250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1977018250
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.332017161
Short name T517
Test name
Test status
Simulation time 650227328 ps
CPU time 21.87 seconds
Started Jul 25 04:47:42 PM PDT 24
Finished Jul 25 04:48:04 PM PDT 24
Peak memory 198468 kb
Host smart-4d712b9c-4f8d-4573-ac24-106c3b99d3cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332017161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.332017161
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3451352621
Short name T680
Test name
Test status
Simulation time 238224420 ps
CPU time 0.92 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 04:47:36 PM PDT 24
Peak memory 198332 kb
Host smart-5b2d94f9-cf8e-43a1-8e51-b03b38fbfb15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451352621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3451352621
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2059413772
Short name T668
Test name
Test status
Simulation time 87038119 ps
CPU time 1.23 seconds
Started Jul 25 04:46:57 PM PDT 24
Finished Jul 25 04:46:59 PM PDT 24
Peak memory 196968 kb
Host smart-132d93f5-2cad-4d4c-9c55-cf844b5f70c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059413772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2059413772
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2197090540
Short name T310
Test name
Test status
Simulation time 34619914 ps
CPU time 1.36 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:26 PM PDT 24
Peak memory 198428 kb
Host smart-4e1c23fe-275d-4183-b062-2c7d74e75d95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197090540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2197090540
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1833890959
Short name T149
Test name
Test status
Simulation time 600914227 ps
CPU time 2.89 seconds
Started Jul 25 04:47:18 PM PDT 24
Finished Jul 25 04:47:21 PM PDT 24
Peak memory 197728 kb
Host smart-105f19a5-dc42-420d-a76e-f35038b804e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833890959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1833890959
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4162796689
Short name T276
Test name
Test status
Simulation time 62766802 ps
CPU time 1.12 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:35 PM PDT 24
Peak memory 198452 kb
Host smart-6a1ed8ed-72ac-4ef9-bcd3-3f93f0018bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162796689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4162796689
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.644128589
Short name T294
Test name
Test status
Simulation time 45276622 ps
CPU time 1.04 seconds
Started Jul 25 04:47:11 PM PDT 24
Finished Jul 25 04:47:12 PM PDT 24
Peak memory 197172 kb
Host smart-1b27c3c3-5059-49eb-8101-2829532e357e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644128589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.644128589
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1313158408
Short name T484
Test name
Test status
Simulation time 1159482843 ps
CPU time 3.34 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 198464 kb
Host smart-dcad67e8-fdf9-4dce-997d-cdb7b6b3e8d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313158408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1313158408
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4102458735
Short name T275
Test name
Test status
Simulation time 180700066 ps
CPU time 1.11 seconds
Started Jul 25 04:47:13 PM PDT 24
Finished Jul 25 04:47:15 PM PDT 24
Peak memory 196956 kb
Host smart-c9a7eef9-3cae-404b-bf87-f5a5d9ca957d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102458735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4102458735
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3234690826
Short name T601
Test name
Test status
Simulation time 38540394 ps
CPU time 0.97 seconds
Started Jul 25 04:47:06 PM PDT 24
Finished Jul 25 04:47:11 PM PDT 24
Peak memory 196208 kb
Host smart-fa555295-5786-4fcb-9757-3936d8ae8b85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234690826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3234690826
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.838449137
Short name T518
Test name
Test status
Simulation time 51377295022 ps
CPU time 174.38 seconds
Started Jul 25 04:47:49 PM PDT 24
Finished Jul 25 04:50:44 PM PDT 24
Peak memory 198596 kb
Host smart-100213e0-a1fe-4c98-9b83-91d0e2e6ee7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838449137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.838449137
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.935242585
Short name T431
Test name
Test status
Simulation time 14500151 ps
CPU time 0.55 seconds
Started Jul 25 04:47:39 PM PDT 24
Finished Jul 25 04:47:40 PM PDT 24
Peak memory 195060 kb
Host smart-c359fe89-44d6-4a41-b6bd-7b6212c153b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935242585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.935242585
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3728326370
Short name T508
Test name
Test status
Simulation time 198790260 ps
CPU time 0.95 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:31 PM PDT 24
Peak memory 196492 kb
Host smart-bf41b59b-5ef1-4676-a9d6-da8f39609e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728326370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3728326370
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2168317174
Short name T520
Test name
Test status
Simulation time 530204968 ps
CPU time 8.45 seconds
Started Jul 25 04:47:24 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 198472 kb
Host smart-9016d4e0-fb9f-40fc-9c71-9d52f353c6c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168317174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2168317174
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2170570218
Short name T304
Test name
Test status
Simulation time 169448582 ps
CPU time 1.08 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 196972 kb
Host smart-47c77630-5b65-43d5-a676-b117ddecf37f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170570218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2170570218
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.916983100
Short name T473
Test name
Test status
Simulation time 98749094 ps
CPU time 0.9 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:29 PM PDT 24
Peak memory 196736 kb
Host smart-11cf2045-818d-47bd-9d8b-325807b4f7df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916983100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.916983100
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2004129910
Short name T174
Test name
Test status
Simulation time 571393942 ps
CPU time 3.14 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:31 PM PDT 24
Peak memory 198628 kb
Host smart-e25c873a-fa92-4b0b-9aa7-196a2d0f6b7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004129910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2004129910
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2375869343
Short name T119
Test name
Test status
Simulation time 618337978 ps
CPU time 3.07 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 197636 kb
Host smart-5167171b-3e18-49a9-8683-54f3af85eb10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375869343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2375869343
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3475660856
Short name T490
Test name
Test status
Simulation time 77901097 ps
CPU time 0.81 seconds
Started Jul 25 04:47:23 PM PDT 24
Finished Jul 25 04:47:24 PM PDT 24
Peak memory 197052 kb
Host smart-f993b8d2-a4c8-48c1-ad0c-4811d2167d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475660856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3475660856
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.542398449
Short name T428
Test name
Test status
Simulation time 394088494 ps
CPU time 1.12 seconds
Started Jul 25 04:47:20 PM PDT 24
Finished Jul 25 04:47:21 PM PDT 24
Peak memory 197284 kb
Host smart-17ea6b7c-286e-45bc-885a-eedfd8bde9d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542398449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.542398449
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3716777356
Short name T122
Test name
Test status
Simulation time 1143124148 ps
CPU time 4.96 seconds
Started Jul 25 04:47:21 PM PDT 24
Finished Jul 25 04:47:26 PM PDT 24
Peak memory 198440 kb
Host smart-260307c3-62db-4a7d-b2b8-1b62e35f4c9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716777356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3716777356
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1144109295
Short name T220
Test name
Test status
Simulation time 36858255 ps
CPU time 0.81 seconds
Started Jul 25 04:47:20 PM PDT 24
Finished Jul 25 04:47:21 PM PDT 24
Peak memory 195584 kb
Host smart-a7b82549-73b2-4f77-9474-fb971539abf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144109295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1144109295
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.523007082
Short name T205
Test name
Test status
Simulation time 101053974 ps
CPU time 1.05 seconds
Started Jul 25 04:51:07 PM PDT 24
Finished Jul 25 04:51:08 PM PDT 24
Peak memory 196184 kb
Host smart-12ebe894-9d37-47ca-9915-50e0a872bf54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523007082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.523007082
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3833357134
Short name T497
Test name
Test status
Simulation time 6034441959 ps
CPU time 44.61 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:48:10 PM PDT 24
Peak memory 198604 kb
Host smart-ad052fe7-b671-477c-9b3e-c458b238d662
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833357134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3833357134
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2902298136
Short name T708
Test name
Test status
Simulation time 38700949 ps
CPU time 0.54 seconds
Started Jul 25 04:47:33 PM PDT 24
Finished Jul 25 04:47:33 PM PDT 24
Peak memory 195092 kb
Host smart-970bc17a-300f-49e1-8417-b040afd9ef7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902298136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2902298136
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2303793090
Short name T351
Test name
Test status
Simulation time 40161244 ps
CPU time 0.69 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:30 PM PDT 24
Peak memory 194572 kb
Host smart-5bc6dfba-7197-434e-b812-340b3654c41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303793090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2303793090
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2042278371
Short name T181
Test name
Test status
Simulation time 545930281 ps
CPU time 20.3 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:56 PM PDT 24
Peak memory 197620 kb
Host smart-294ceb46-903f-4310-a8ae-2732cbe30ff2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042278371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2042278371
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1048574049
Short name T581
Test name
Test status
Simulation time 49861694 ps
CPU time 0.78 seconds
Started Jul 25 04:47:19 PM PDT 24
Finished Jul 25 04:47:20 PM PDT 24
Peak memory 196984 kb
Host smart-69577be2-7c97-4cb2-9fe0-7974944533d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048574049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1048574049
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3865396813
Short name T607
Test name
Test status
Simulation time 46064241 ps
CPU time 0.96 seconds
Started Jul 25 04:47:21 PM PDT 24
Finished Jul 25 04:47:22 PM PDT 24
Peak memory 196628 kb
Host smart-fb9fa06f-1577-4a2c-984f-3d0c6c6f9543
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865396813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3865396813
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3660334594
Short name T295
Test name
Test status
Simulation time 517722430 ps
CPU time 3.32 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:30 PM PDT 24
Peak memory 196780 kb
Host smart-dbb10aff-bb65-4a3e-83bd-1b0370f5e791
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660334594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3660334594
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.606632878
Short name T246
Test name
Test status
Simulation time 63190648 ps
CPU time 1.9 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 198516 kb
Host smart-c757d037-13ed-4ed7-9ce6-88c0d6f5ff81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606632878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
606632878
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1877946221
Short name T277
Test name
Test status
Simulation time 24145996 ps
CPU time 0.72 seconds
Started Jul 25 04:47:23 PM PDT 24
Finished Jul 25 04:47:24 PM PDT 24
Peak memory 195904 kb
Host smart-e1e321c8-2064-44e2-98b7-e55d9c70df41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877946221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1877946221
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.15428850
Short name T309
Test name
Test status
Simulation time 34204714 ps
CPU time 1.17 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 197364 kb
Host smart-0062ac70-ef7d-4791-8bff-5b7665ffe33f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup_
pulldown.15428850
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2225213369
Short name T460
Test name
Test status
Simulation time 2069100716 ps
CPU time 5.34 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:38 PM PDT 24
Peak memory 198436 kb
Host smart-7ed537e6-e7fd-4a30-a9e3-f148909ed8ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225213369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2225213369
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2605308297
Short name T476
Test name
Test status
Simulation time 44406811 ps
CPU time 1 seconds
Started Jul 25 04:47:20 PM PDT 24
Finished Jul 25 04:47:21 PM PDT 24
Peak memory 196268 kb
Host smart-d0ac4c08-5903-47b6-9a70-512adc86abe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605308297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2605308297
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3699573141
Short name T305
Test name
Test status
Simulation time 29758023 ps
CPU time 0.91 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:33 PM PDT 24
Peak memory 196968 kb
Host smart-8d735958-461a-4ed1-9d72-3d55b05d180d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699573141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3699573141
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3124296393
Short name T567
Test name
Test status
Simulation time 46763107772 ps
CPU time 91.12 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:48:58 PM PDT 24
Peak memory 198580 kb
Host smart-e29ef9e3-d463-44d7-885a-99832f0d8c75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124296393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3124296393
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1645207488
Short name T575
Test name
Test status
Simulation time 194836673131 ps
CPU time 662.79 seconds
Started Jul 25 04:49:55 PM PDT 24
Finished Jul 25 05:00:58 PM PDT 24
Peak memory 198760 kb
Host smart-99ff6696-9178-49a3-9f7a-b5148ad2f8a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1645207488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1645207488
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3579459002
Short name T142
Test name
Test status
Simulation time 12001163 ps
CPU time 0.57 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 194364 kb
Host smart-9e36a73d-4d85-4e90-852d-e09258129e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579459002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3579459002
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.4193423445
Short name T556
Test name
Test status
Simulation time 178374473 ps
CPU time 0.89 seconds
Started Jul 25 04:47:39 PM PDT 24
Finished Jul 25 04:47:40 PM PDT 24
Peak memory 196944 kb
Host smart-423e09a8-f4e5-4b78-9a3b-414406ecebfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193423445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.4193423445
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3440300840
Short name T178
Test name
Test status
Simulation time 1398996502 ps
CPU time 12.7 seconds
Started Jul 25 04:47:10 PM PDT 24
Finished Jul 25 04:47:23 PM PDT 24
Peak memory 197364 kb
Host smart-e9006933-f05b-406b-8be3-fe48e29e2518
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440300840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3440300840
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1032635999
Short name T20
Test name
Test status
Simulation time 665269852 ps
CPU time 0.96 seconds
Started Jul 25 04:47:36 PM PDT 24
Finished Jul 25 04:47:42 PM PDT 24
Peak memory 198200 kb
Host smart-9276e30f-37ca-487e-ad64-0a03cebe4ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032635999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1032635999
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.876691464
Short name T371
Test name
Test status
Simulation time 203000944 ps
CPU time 0.99 seconds
Started Jul 25 04:47:18 PM PDT 24
Finished Jul 25 04:47:19 PM PDT 24
Peak memory 196932 kb
Host smart-4b90c65c-41af-4010-93c1-5233e80cab3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876691464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.876691464
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2165477588
Short name T192
Test name
Test status
Simulation time 104406468 ps
CPU time 3.6 seconds
Started Jul 25 04:47:18 PM PDT 24
Finished Jul 25 04:47:22 PM PDT 24
Peak memory 198476 kb
Host smart-f99ba37b-88e7-4e0c-86d6-f7441b6dbdac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165477588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2165477588
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2042020912
Short name T154
Test name
Test status
Simulation time 149868452 ps
CPU time 2.7 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 04:47:37 PM PDT 24
Peak memory 197572 kb
Host smart-32e8fdd5-3c8d-47be-a63e-6973c6e76dbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042020912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2042020912
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1357530123
Short name T543
Test name
Test status
Simulation time 48328050 ps
CPU time 0.91 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:29 PM PDT 24
Peak memory 196332 kb
Host smart-84c46072-d6af-4080-afeb-021168f1449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357530123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1357530123
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.226655777
Short name T332
Test name
Test status
Simulation time 61863105 ps
CPU time 1.19 seconds
Started Jul 25 04:47:50 PM PDT 24
Finished Jul 25 04:47:52 PM PDT 24
Peak memory 197608 kb
Host smart-ddfe5947-8c2b-43a3-a8dd-cd7fd6fa717d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226655777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.226655777
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.523163323
Short name T280
Test name
Test status
Simulation time 371949441 ps
CPU time 1.91 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 198508 kb
Host smart-1628c6ee-b022-44c3-ab56-5e1d16c739f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523163323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.523163323
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.29502412
Short name T633
Test name
Test status
Simulation time 415387442 ps
CPU time 0.99 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:28 PM PDT 24
Peak memory 195984 kb
Host smart-704a3e50-76e0-4ac9-bb8e-3b9c1c74785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29502412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.29502412
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2597328656
Short name T210
Test name
Test status
Simulation time 38953097 ps
CPU time 1.11 seconds
Started Jul 25 04:47:20 PM PDT 24
Finished Jul 25 04:47:22 PM PDT 24
Peak memory 196260 kb
Host smart-6d421d8c-5479-403a-9806-25c4c3881394
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597328656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2597328656
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3547279246
Short name T158
Test name
Test status
Simulation time 4908955052 ps
CPU time 36.17 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:48:08 PM PDT 24
Peak memory 198632 kb
Host smart-a19e8a47-2723-463f-9f2a-55dcf4b80269
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547279246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3547279246
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1651462969
Short name T628
Test name
Test status
Simulation time 44097480 ps
CPU time 0.54 seconds
Started Jul 25 04:46:24 PM PDT 24
Finished Jul 25 04:46:25 PM PDT 24
Peak memory 194328 kb
Host smart-b4914629-0cfe-4811-9d5e-1a53641770ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651462969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1651462969
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3728255430
Short name T353
Test name
Test status
Simulation time 25440666 ps
CPU time 0.77 seconds
Started Jul 25 04:46:04 PM PDT 24
Finished Jul 25 04:46:05 PM PDT 24
Peak memory 196400 kb
Host smart-3d265c16-0783-4f18-879c-a9c6b29aa052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728255430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3728255430
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1157836133
Short name T364
Test name
Test status
Simulation time 559828994 ps
CPU time 28.17 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:47:00 PM PDT 24
Peak memory 198492 kb
Host smart-658c2e08-a9e6-4142-aa7e-00df518e63ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157836133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1157836133
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3526334137
Short name T560
Test name
Test status
Simulation time 401233116 ps
CPU time 0.88 seconds
Started Jul 25 04:46:15 PM PDT 24
Finished Jul 25 04:46:16 PM PDT 24
Peak memory 196288 kb
Host smart-8a5ebc2b-7469-468b-bb52-8a5f65a8ebf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526334137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3526334137
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3955859410
Short name T442
Test name
Test status
Simulation time 70374469 ps
CPU time 1.21 seconds
Started Jul 25 04:46:30 PM PDT 24
Finished Jul 25 04:46:31 PM PDT 24
Peak memory 196264 kb
Host smart-f8bd9827-cb6f-4f35-af64-91d9b2e301f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955859410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3955859410
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2316846470
Short name T259
Test name
Test status
Simulation time 64097756 ps
CPU time 1.37 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 196808 kb
Host smart-5c2ef208-c1d9-4c8c-8394-4135d37ee35e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316846470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2316846470
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1635756897
Short name T116
Test name
Test status
Simulation time 50617102 ps
CPU time 1.17 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 196984 kb
Host smart-734e84dc-1daf-41c5-8fb6-dc9d4bdeb0ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635756897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1635756897
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.4068538843
Short name T578
Test name
Test status
Simulation time 18622709 ps
CPU time 0.66 seconds
Started Jul 25 04:46:41 PM PDT 24
Finished Jul 25 04:46:42 PM PDT 24
Peak memory 195392 kb
Host smart-25529878-e60d-4f70-bc8f-c631817dca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068538843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.4068538843
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1296268159
Short name T231
Test name
Test status
Simulation time 184493959 ps
CPU time 1.16 seconds
Started Jul 25 04:46:22 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 197104 kb
Host smart-af2aeb86-a004-4469-9493-6b04e2c404a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296268159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1296268159
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.511385296
Short name T278
Test name
Test status
Simulation time 363580383 ps
CPU time 3.12 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:30 PM PDT 24
Peak memory 198456 kb
Host smart-e3e4f9aa-14a9-4781-93b6-c45fea6eb841
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511385296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.511385296
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.652007472
Short name T46
Test name
Test status
Simulation time 57236369 ps
CPU time 0.81 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 214292 kb
Host smart-ac482922-e4fa-4808-91e2-cc2a871c8b32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652007472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.652007472
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3281779636
Short name T677
Test name
Test status
Simulation time 403210384 ps
CPU time 1.05 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:46:26 PM PDT 24
Peak memory 197112 kb
Host smart-e0ed7083-2ce9-49c9-aa93-78315fd4032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281779636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3281779636
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.518709729
Short name T642
Test name
Test status
Simulation time 210803200 ps
CPU time 1.07 seconds
Started Jul 25 04:46:15 PM PDT 24
Finished Jul 25 04:46:17 PM PDT 24
Peak memory 195968 kb
Host smart-2b9b9c45-824e-4953-b38c-e9d6b9b6c37c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518709729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.518709729
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2569520833
Short name T106
Test name
Test status
Simulation time 13712090782 ps
CPU time 193.19 seconds
Started Jul 25 04:46:27 PM PDT 24
Finished Jul 25 04:49:40 PM PDT 24
Peak memory 198588 kb
Host smart-6747e2d1-9242-4229-aec6-4a244d970498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569520833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2569520833
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3364176563
Short name T445
Test name
Test status
Simulation time 69642648874 ps
CPU time 1288.09 seconds
Started Jul 25 04:46:27 PM PDT 24
Finished Jul 25 05:07:56 PM PDT 24
Peak memory 198712 kb
Host smart-7216adac-2776-4b77-929e-139215bb2f4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3364176563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3364176563
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.444366619
Short name T462
Test name
Test status
Simulation time 14454031 ps
CPU time 0.56 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:29 PM PDT 24
Peak memory 194440 kb
Host smart-bd8bc8c2-53b7-4c98-a754-bb0bb6028859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444366619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.444366619
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3213507585
Short name T180
Test name
Test status
Simulation time 99758139 ps
CPU time 0.73 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 04:47:35 PM PDT 24
Peak memory 196492 kb
Host smart-36b54e4e-778d-4389-80aa-9cef357da50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213507585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3213507585
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1223158679
Short name T156
Test name
Test status
Simulation time 852397091 ps
CPU time 7.02 seconds
Started Jul 25 04:47:48 PM PDT 24
Finished Jul 25 04:47:55 PM PDT 24
Peak memory 198460 kb
Host smart-9565cb2c-4122-497b-84b4-476a382f5036
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223158679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1223158679
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1380333449
Short name T559
Test name
Test status
Simulation time 217245955 ps
CPU time 0.86 seconds
Started Jul 25 04:47:40 PM PDT 24
Finished Jul 25 04:47:41 PM PDT 24
Peak memory 197568 kb
Host smart-0a587c9c-2a27-45b4-9fe4-cb4fc271bd89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380333449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1380333449
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1108104772
Short name T313
Test name
Test status
Simulation time 39865463 ps
CPU time 0.67 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 194780 kb
Host smart-26d22059-8c40-48af-b3e9-3f0281ec2133
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108104772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1108104772
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2741854090
Short name T411
Test name
Test status
Simulation time 122735561 ps
CPU time 2.12 seconds
Started Jul 25 04:47:44 PM PDT 24
Finished Jul 25 04:47:47 PM PDT 24
Peak memory 198460 kb
Host smart-79b93e60-f399-464d-b907-0d486480acfa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741854090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2741854090
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2305439719
Short name T227
Test name
Test status
Simulation time 155003754 ps
CPU time 2.22 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:29 PM PDT 24
Peak memory 198524 kb
Host smart-5b85fc73-2cbd-43a8-af5a-a3822980b198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305439719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2305439719
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1987313527
Short name T390
Test name
Test status
Simulation time 125309710 ps
CPU time 1.19 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:30 PM PDT 24
Peak memory 197092 kb
Host smart-40883aee-2dbc-4ee9-be47-9cd87d1ee1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987313527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1987313527
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1797192201
Short name T202
Test name
Test status
Simulation time 30144991 ps
CPU time 0.98 seconds
Started Jul 25 04:47:51 PM PDT 24
Finished Jul 25 04:47:52 PM PDT 24
Peak memory 197156 kb
Host smart-f63e8a0f-47fe-49e3-99ab-b2a8156e761d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797192201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1797192201
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.306955491
Short name T504
Test name
Test status
Simulation time 296015682 ps
CPU time 3.36 seconds
Started Jul 25 04:47:44 PM PDT 24
Finished Jul 25 04:47:48 PM PDT 24
Peak memory 198416 kb
Host smart-2af2e353-0b92-4fba-94a3-4ace9d3e8301
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306955491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.306955491
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.464580128
Short name T350
Test name
Test status
Simulation time 41148769 ps
CPU time 0.81 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 04:47:35 PM PDT 24
Peak memory 195772 kb
Host smart-5acb4287-c5b3-42cc-a0ec-8f2d26cd3b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464580128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.464580128
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1848737404
Short name T398
Test name
Test status
Simulation time 25121397 ps
CPU time 0.79 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:28 PM PDT 24
Peak memory 195744 kb
Host smart-97235ecb-f5f5-4f45-8fbb-df0d3859d8f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848737404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1848737404
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.4135970171
Short name T10
Test name
Test status
Simulation time 24019297241 ps
CPU time 147.67 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 04:50:03 PM PDT 24
Peak memory 198664 kb
Host smart-ee7ae1f7-9d12-4f84-8806-3eae3e87ed8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135970171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.4135970171
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.498869695
Short name T479
Test name
Test status
Simulation time 48564197201 ps
CPU time 794.34 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 05:00:49 PM PDT 24
Peak memory 198732 kb
Host smart-de6648a1-51e3-4884-89ea-598873e6da70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=498869695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.498869695
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3744609827
Short name T133
Test name
Test status
Simulation time 22434173 ps
CPU time 0.54 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:31 PM PDT 24
Peak memory 194364 kb
Host smart-f2f234c1-3642-49d1-8ca4-dc6ec4d5c656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744609827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3744609827
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2534748428
Short name T377
Test name
Test status
Simulation time 62500903 ps
CPU time 0.77 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 195880 kb
Host smart-14208fe2-2275-42b8-b275-428381918b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534748428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2534748428
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1136470873
Short name T699
Test name
Test status
Simulation time 4723914828 ps
CPU time 26.13 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:48:10 PM PDT 24
Peak memory 197212 kb
Host smart-e3af4589-e0f8-4a82-8d97-de644dd39112
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136470873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1136470873
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1039811407
Short name T403
Test name
Test status
Simulation time 273221370 ps
CPU time 1.06 seconds
Started Jul 25 04:47:47 PM PDT 24
Finished Jul 25 04:47:48 PM PDT 24
Peak memory 196992 kb
Host smart-60cf4023-f783-487c-a41b-bac7d39339eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039811407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1039811407
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2802402813
Short name T565
Test name
Test status
Simulation time 122211526 ps
CPU time 1.02 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 04:47:37 PM PDT 24
Peak memory 196420 kb
Host smart-0e67510e-3f9a-4456-a98c-cdef5cec8b5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802402813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2802402813
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1817012357
Short name T492
Test name
Test status
Simulation time 66260951 ps
CPU time 2.5 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 198476 kb
Host smart-33f1a278-ddde-4890-97c3-755f617db091
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817012357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1817012357
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.4153045883
Short name T621
Test name
Test status
Simulation time 147986746 ps
CPU time 1.42 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 196508 kb
Host smart-724f963f-d206-46d3-a2c5-27ed49a88216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153045883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.4153045883
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2029028978
Short name T685
Test name
Test status
Simulation time 235493348 ps
CPU time 1.26 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 196280 kb
Host smart-0ee88324-40fd-4d52-9cf9-14f4c73a73da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029028978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2029028978
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.178016441
Short name T596
Test name
Test status
Simulation time 117659903 ps
CPU time 0.76 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 195920 kb
Host smart-175c93c4-271d-48a4-8737-a9bee5cc1e2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178016441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.178016441
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1165527167
Short name T230
Test name
Test status
Simulation time 309315290 ps
CPU time 4.9 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:37 PM PDT 24
Peak memory 198448 kb
Host smart-bd9e5edd-b836-4002-b78f-550aeeb14e6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165527167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1165527167
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.36149433
Short name T207
Test name
Test status
Simulation time 88700263 ps
CPU time 1.38 seconds
Started Jul 25 04:47:20 PM PDT 24
Finished Jul 25 04:47:22 PM PDT 24
Peak memory 196376 kb
Host smart-717528f1-1139-4fc7-b1d4-68b827c2a394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36149433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.36149433
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.908639254
Short name T139
Test name
Test status
Simulation time 298422110 ps
CPU time 1.2 seconds
Started Jul 25 04:48:06 PM PDT 24
Finished Jul 25 04:48:07 PM PDT 24
Peak memory 196064 kb
Host smart-f4e5da31-4b9d-4e04-8674-98019a3de933
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908639254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.908639254
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3027058173
Short name T657
Test name
Test status
Simulation time 11345735062 ps
CPU time 46.39 seconds
Started Jul 25 04:47:38 PM PDT 24
Finished Jul 25 04:48:24 PM PDT 24
Peak memory 198584 kb
Host smart-5d70df0b-693c-4443-902a-92a1db27cea7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027058173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3027058173
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.773476963
Short name T650
Test name
Test status
Simulation time 42798440 ps
CPU time 0.57 seconds
Started Jul 25 04:48:02 PM PDT 24
Finished Jul 25 04:48:08 PM PDT 24
Peak memory 194612 kb
Host smart-6682e8b9-954e-4e0a-9944-eb1e62fc96c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773476963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.773476963
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2470405814
Short name T341
Test name
Test status
Simulation time 26277541 ps
CPU time 0.62 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:31 PM PDT 24
Peak memory 194356 kb
Host smart-37f24b2e-11a8-42ff-b71c-942cb8477c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470405814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2470405814
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3139458976
Short name T62
Test name
Test status
Simulation time 1907049854 ps
CPU time 16.54 seconds
Started Jul 25 04:48:08 PM PDT 24
Finished Jul 25 04:48:25 PM PDT 24
Peak memory 198476 kb
Host smart-0314718b-dcbe-4b51-a058-4c7053fb6415
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139458976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3139458976
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.4033241280
Short name T48
Test name
Test status
Simulation time 169547703 ps
CPU time 0.78 seconds
Started Jul 25 04:47:21 PM PDT 24
Finished Jul 25 04:47:22 PM PDT 24
Peak memory 196508 kb
Host smart-64fdf22f-8b0b-4b92-af97-237ba3f2d4b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033241280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4033241280
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2899993025
Short name T183
Test name
Test status
Simulation time 31096059 ps
CPU time 0.68 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:31 PM PDT 24
Peak memory 195540 kb
Host smart-f69a07e3-82cc-4694-a2d9-e17c0537413b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899993025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2899993025
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.951660825
Short name T233
Test name
Test status
Simulation time 248910933 ps
CPU time 2.53 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 196980 kb
Host smart-fa4807df-2be7-4a7e-8f82-73406f8cb8a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951660825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.951660825
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3418407179
Short name T511
Test name
Test status
Simulation time 323359123 ps
CPU time 2.4 seconds
Started Jul 25 04:47:48 PM PDT 24
Finished Jul 25 04:47:50 PM PDT 24
Peak memory 196980 kb
Host smart-b6e3ca41-3f4b-4a13-919e-9f1f0260339e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418407179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3418407179
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3284902629
Short name T260
Test name
Test status
Simulation time 72962181 ps
CPU time 0.88 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 197216 kb
Host smart-ee088c40-69d1-4e52-aef6-a950a22e1391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284902629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3284902629
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.690659568
Short name T410
Test name
Test status
Simulation time 29164006 ps
CPU time 0.75 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 195952 kb
Host smart-e7198339-3d12-4375-a170-4c05ca59c7b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690659568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.690659568
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2121829922
Short name T136
Test name
Test status
Simulation time 419915896 ps
CPU time 4.53 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:31 PM PDT 24
Peak memory 198400 kb
Host smart-50455b15-4676-4eb0-b814-b70671908016
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121829922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2121829922
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.502737714
Short name T536
Test name
Test status
Simulation time 140292455 ps
CPU time 0.83 seconds
Started Jul 25 04:47:36 PM PDT 24
Finished Jul 25 04:47:37 PM PDT 24
Peak memory 195876 kb
Host smart-5f468c3a-3c71-4ae3-99c3-783f718e9d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502737714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.502737714
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.136309728
Short name T190
Test name
Test status
Simulation time 71550237 ps
CPU time 0.72 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 196244 kb
Host smart-56b0c152-b220-4873-82a8-bdf467f6ebdd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136309728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.136309728
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3500717917
Short name T468
Test name
Test status
Simulation time 31145214155 ps
CPU time 162.94 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 198704 kb
Host smart-aed27c48-f643-4103-80bc-354647aa60f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500717917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3500717917
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1644165678
Short name T521
Test name
Test status
Simulation time 30616586 ps
CPU time 0.56 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 195412 kb
Host smart-fc492e6d-73be-40d2-bf45-6f86e1f05908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644165678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1644165678
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1969060979
Short name T402
Test name
Test status
Simulation time 83205106 ps
CPU time 0.74 seconds
Started Jul 25 04:47:36 PM PDT 24
Finished Jul 25 04:47:37 PM PDT 24
Peak memory 195736 kb
Host smart-582074fb-2be1-404d-800f-38bf9dbf989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969060979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1969060979
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1721788197
Short name T33
Test name
Test status
Simulation time 1659541739 ps
CPU time 21.48 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:48 PM PDT 24
Peak memory 197356 kb
Host smart-d1282adb-c67c-4f20-84c4-f62887285b79
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721788197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1721788197
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1889816526
Short name T679
Test name
Test status
Simulation time 111949779 ps
CPU time 0.71 seconds
Started Jul 25 04:47:24 PM PDT 24
Finished Jul 25 04:47:25 PM PDT 24
Peak memory 195796 kb
Host smart-1d1843ed-0645-4de9-b318-291751104adc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889816526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1889816526
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.978107525
Short name T281
Test name
Test status
Simulation time 50633295 ps
CPU time 1.29 seconds
Started Jul 25 04:47:40 PM PDT 24
Finished Jul 25 04:47:42 PM PDT 24
Peak memory 197588 kb
Host smart-25814cf0-0e61-44b8-a187-c3c44ee4fca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978107525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.978107525
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2294928423
Short name T415
Test name
Test status
Simulation time 164588574 ps
CPU time 1.13 seconds
Started Jul 25 04:47:24 PM PDT 24
Finished Jul 25 04:47:26 PM PDT 24
Peak memory 197884 kb
Host smart-b346faf1-b11f-4093-aa03-4d8a9c234462
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294928423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2294928423
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3402173296
Short name T103
Test name
Test status
Simulation time 50475193 ps
CPU time 0.94 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:28 PM PDT 24
Peak memory 196680 kb
Host smart-a767f384-84c3-4432-b533-7a4fc6749164
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402173296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3402173296
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.85667749
Short name T652
Test name
Test status
Simulation time 30699101 ps
CPU time 0.91 seconds
Started Jul 25 04:47:22 PM PDT 24
Finished Jul 25 04:47:23 PM PDT 24
Peak memory 196264 kb
Host smart-f61937fc-2089-45ef-8766-137942bf30ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85667749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.85667749
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2452510132
Short name T463
Test name
Test status
Simulation time 84294672 ps
CPU time 0.63 seconds
Started Jul 25 04:47:38 PM PDT 24
Finished Jul 25 04:47:39 PM PDT 24
Peak memory 195500 kb
Host smart-fa0deeaf-aa76-45a6-8d2b-314d51aa4bbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452510132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2452510132
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.24325637
Short name T512
Test name
Test status
Simulation time 207417490 ps
CPU time 2.59 seconds
Started Jul 25 04:47:38 PM PDT 24
Finished Jul 25 04:47:40 PM PDT 24
Peak memory 198312 kb
Host smart-7e58df54-badb-4c1d-9256-ebd50224152f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24325637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand
om_long_reg_writes_reg_reads.24325637
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3664090793
Short name T609
Test name
Test status
Simulation time 29500272 ps
CPU time 0.93 seconds
Started Jul 25 04:47:54 PM PDT 24
Finished Jul 25 04:47:56 PM PDT 24
Peak memory 196136 kb
Host smart-2d11850d-1225-4d01-94ea-c55795ce4384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664090793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3664090793
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3998326282
Short name T108
Test name
Test status
Simulation time 113233077 ps
CPU time 0.77 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:28 PM PDT 24
Peak memory 195672 kb
Host smart-90c345ed-eae2-446f-90c9-a4f043611bc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998326282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3998326282
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1361961424
Short name T412
Test name
Test status
Simulation time 19212382952 ps
CPU time 101.26 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:49:25 PM PDT 24
Peak memory 198644 kb
Host smart-b855f24a-3e89-4c85-a90d-8bf626ce9fb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361961424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1361961424
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1113299331
Short name T40
Test name
Test status
Simulation time 213942804285 ps
CPU time 1924.99 seconds
Started Jul 25 04:47:33 PM PDT 24
Finished Jul 25 05:19:39 PM PDT 24
Peak memory 198696 kb
Host smart-9e5954ef-382e-4200-9a2a-51a159bb1c13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1113299331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1113299331
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2123188344
Short name T144
Test name
Test status
Simulation time 14305306 ps
CPU time 0.57 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:28 PM PDT 24
Peak memory 194552 kb
Host smart-2ef48116-f0b7-4e48-a017-cbce7674357c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123188344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2123188344
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1338398699
Short name T188
Test name
Test status
Simulation time 35117521 ps
CPU time 0.71 seconds
Started Jul 25 04:47:38 PM PDT 24
Finished Jul 25 04:47:45 PM PDT 24
Peak memory 196296 kb
Host smart-a59bfe5c-7fac-4b30-b8e4-ab7fc770f31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338398699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1338398699
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.473468399
Short name T374
Test name
Test status
Simulation time 529013296 ps
CPU time 26.82 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:55 PM PDT 24
Peak memory 196732 kb
Host smart-b6dfeaa9-4b38-4135-872c-3c6894c2a241
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473468399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.473468399
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2659580349
Short name T244
Test name
Test status
Simulation time 304418672 ps
CPU time 0.92 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:30 PM PDT 24
Peak memory 197600 kb
Host smart-32e5f449-b21e-45bc-aae8-2040afc7f8c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659580349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2659580349
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.45872282
Short name T541
Test name
Test status
Simulation time 196629795 ps
CPU time 1.36 seconds
Started Jul 25 04:47:53 PM PDT 24
Finished Jul 25 04:47:54 PM PDT 24
Peak memory 197636 kb
Host smart-c4e6a2fc-4956-49f6-a243-3304e4ddb3a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45872282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.45872282
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1208646556
Short name T289
Test name
Test status
Simulation time 96262389 ps
CPU time 1.96 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:31 PM PDT 24
Peak memory 198236 kb
Host smart-4113b804-eb43-4553-9016-c9034b9118aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208646556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1208646556
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3356394171
Short name T301
Test name
Test status
Simulation time 291794900 ps
CPU time 3.21 seconds
Started Jul 25 04:47:23 PM PDT 24
Finished Jul 25 04:47:26 PM PDT 24
Peak memory 198496 kb
Host smart-9fdaa9fd-a8e4-426b-a081-df31d1aee3e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356394171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3356394171
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3304844302
Short name T288
Test name
Test status
Simulation time 326654941 ps
CPU time 1.23 seconds
Started Jul 25 04:47:23 PM PDT 24
Finished Jul 25 04:47:25 PM PDT 24
Peak memory 197088 kb
Host smart-6a7ef4f8-2ac7-4b2d-b919-421945bd9a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304844302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3304844302
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3314520427
Short name T574
Test name
Test status
Simulation time 55792777 ps
CPU time 1.2 seconds
Started Jul 25 04:47:33 PM PDT 24
Finished Jul 25 04:47:35 PM PDT 24
Peak memory 196332 kb
Host smart-57fb9a41-e5a2-4163-83c3-11155e451a96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314520427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3314520427
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.859567869
Short name T3
Test name
Test status
Simulation time 413919251 ps
CPU time 5.18 seconds
Started Jul 25 04:47:41 PM PDT 24
Finished Jul 25 04:47:47 PM PDT 24
Peak memory 198388 kb
Host smart-ce6b6d38-62e5-4676-b1ca-14988f86930d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859567869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.859567869
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3777557940
Short name T389
Test name
Test status
Simulation time 38320157 ps
CPU time 1.04 seconds
Started Jul 25 04:47:22 PM PDT 24
Finished Jul 25 04:47:24 PM PDT 24
Peak memory 196264 kb
Host smart-591d2e31-f76a-472b-afe9-963d2a612efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777557940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3777557940
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.994641407
Short name T221
Test name
Test status
Simulation time 51991227 ps
CPU time 1.32 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:30 PM PDT 24
Peak memory 198524 kb
Host smart-407ed51b-d631-4638-9c95-1a3f06ad6866
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994641407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.994641407
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3504618507
Short name T107
Test name
Test status
Simulation time 21645681026 ps
CPU time 127.49 seconds
Started Jul 25 04:47:23 PM PDT 24
Finished Jul 25 04:49:31 PM PDT 24
Peak memory 198576 kb
Host smart-c322a3b2-a7b0-42b8-bd7e-b62f6cf8cb1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504618507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3504618507
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2444589061
Short name T362
Test name
Test status
Simulation time 129354273017 ps
CPU time 772.82 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 05:00:28 PM PDT 24
Peak memory 198696 kb
Host smart-d5390349-62e3-4759-bebd-6378a4fc7379
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2444589061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2444589061
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2206083634
Short name T138
Test name
Test status
Simulation time 17741017 ps
CPU time 0.53 seconds
Started Jul 25 04:47:44 PM PDT 24
Finished Jul 25 04:47:45 PM PDT 24
Peak memory 193164 kb
Host smart-ffae1f57-61b5-4c13-babb-302e61e9a4ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206083634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2206083634
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1116986835
Short name T272
Test name
Test status
Simulation time 58783056 ps
CPU time 0.9 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 196508 kb
Host smart-427a1153-192a-410c-a6ad-ecac56756e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116986835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1116986835
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.592714243
Short name T472
Test name
Test status
Simulation time 557162129 ps
CPU time 9.6 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:47:47 PM PDT 24
Peak memory 195988 kb
Host smart-eb314424-026d-4644-9708-29002107dcf1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592714243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.592714243
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1465896091
Short name T671
Test name
Test status
Simulation time 132623338 ps
CPU time 0.7 seconds
Started Jul 25 04:47:25 PM PDT 24
Finished Jul 25 04:47:26 PM PDT 24
Peak memory 194920 kb
Host smart-4f1cbc2e-ae15-4c58-9570-aed828958b8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465896091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1465896091
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3369830474
Short name T711
Test name
Test status
Simulation time 183851159 ps
CPU time 1.21 seconds
Started Jul 25 04:47:36 PM PDT 24
Finished Jul 25 04:47:37 PM PDT 24
Peak memory 198476 kb
Host smart-57a40175-26dd-4f32-a186-a3118135c568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369830474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3369830474
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.409045886
Short name T216
Test name
Test status
Simulation time 184342083 ps
CPU time 1.72 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:29 PM PDT 24
Peak memory 198408 kb
Host smart-295b2157-872f-4fc8-aac7-497459fe59ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409045886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.409045886
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1182225994
Short name T175
Test name
Test status
Simulation time 104815991 ps
CPU time 2.31 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 197372 kb
Host smart-5441fb68-9baf-45ae-8577-0b74ccdb03d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182225994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1182225994
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.522481118
Short name T349
Test name
Test status
Simulation time 14163672 ps
CPU time 0.67 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 04:47:36 PM PDT 24
Peak memory 195448 kb
Host smart-f9e43dff-5457-4360-a9c8-b1b161487603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522481118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.522481118
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3075502816
Short name T393
Test name
Test status
Simulation time 67120303 ps
CPU time 1.19 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 04:47:35 PM PDT 24
Peak memory 197024 kb
Host smart-3f2a12a9-d94f-48c2-b7cb-a5e613ec7e6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075502816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3075502816
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2548682323
Short name T555
Test name
Test status
Simulation time 77004372 ps
CPU time 3.57 seconds
Started Jul 25 04:47:49 PM PDT 24
Finished Jul 25 04:47:53 PM PDT 24
Peak memory 198524 kb
Host smart-04fca3f7-4d1c-40d5-a9bc-01e3388f3203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548682323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2548682323
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1711590992
Short name T617
Test name
Test status
Simulation time 55848871 ps
CPU time 0.97 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 196268 kb
Host smart-570d49e3-44da-41ab-a9f6-2226ee9103ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711590992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1711590992
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2322280532
Short name T432
Test name
Test status
Simulation time 152702046 ps
CPU time 0.99 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 04:47:36 PM PDT 24
Peak memory 195996 kb
Host smart-1eaf3046-eee2-4ac1-895c-3db65330eb4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322280532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2322280532
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3669891780
Short name T426
Test name
Test status
Simulation time 18287885431 ps
CPU time 157.79 seconds
Started Jul 25 04:47:57 PM PDT 24
Finished Jul 25 04:50:35 PM PDT 24
Peak memory 198544 kb
Host smart-fe618381-d977-457f-8fc1-f0753aa069cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669891780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3669891780
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1930261880
Short name T405
Test name
Test status
Simulation time 23775860423 ps
CPU time 757.81 seconds
Started Jul 25 04:47:40 PM PDT 24
Finished Jul 25 05:00:18 PM PDT 24
Peak memory 198712 kb
Host smart-eceafd78-f636-45e2-ad3f-1fcedc37211c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1930261880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1930261880
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.4171213322
Short name T137
Test name
Test status
Simulation time 43657563 ps
CPU time 0.56 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:33 PM PDT 24
Peak memory 194332 kb
Host smart-d1ad3e40-a284-4760-91db-13c50d1933d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171213322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.4171213322
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2430523908
Short name T623
Test name
Test status
Simulation time 28682794 ps
CPU time 0.63 seconds
Started Jul 25 04:47:29 PM PDT 24
Finished Jul 25 04:47:29 PM PDT 24
Peak memory 194416 kb
Host smart-a852f585-a6cc-4d0f-9111-27681088f59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430523908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2430523908
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.226507442
Short name T533
Test name
Test status
Simulation time 705513639 ps
CPU time 25 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:48:08 PM PDT 24
Peak memory 197112 kb
Host smart-fe56210a-6e88-431b-8be5-796f534116f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226507442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.226507442
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.666935613
Short name T203
Test name
Test status
Simulation time 45618443 ps
CPU time 0.78 seconds
Started Jul 25 04:47:27 PM PDT 24
Finished Jul 25 04:47:28 PM PDT 24
Peak memory 196488 kb
Host smart-7eacdf7f-141f-487e-8ed1-c54d2da85b33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666935613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.666935613
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1055005502
Short name T363
Test name
Test status
Simulation time 26298508 ps
CPU time 0.85 seconds
Started Jul 25 04:47:31 PM PDT 24
Finished Jul 25 04:47:32 PM PDT 24
Peak memory 197148 kb
Host smart-40b7f278-d6f8-4225-9040-c6487c22e649
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055005502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1055005502
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3247995369
Short name T477
Test name
Test status
Simulation time 227320477 ps
CPU time 1.07 seconds
Started Jul 25 04:47:44 PM PDT 24
Finished Jul 25 04:47:45 PM PDT 24
Peak memory 198460 kb
Host smart-e7a3fbea-92d3-4d49-a6ad-d1b75cb9af74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247995369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3247995369
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2413010209
Short name T243
Test name
Test status
Simulation time 155962134 ps
CPU time 1.05 seconds
Started Jul 25 04:47:50 PM PDT 24
Finished Jul 25 04:47:51 PM PDT 24
Peak memory 195872 kb
Host smart-dfc086ce-d865-4809-ad71-30be489d67f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413010209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2413010209
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3150170847
Short name T385
Test name
Test status
Simulation time 21593898 ps
CPU time 0.73 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:47:38 PM PDT 24
Peak memory 195928 kb
Host smart-ebe85145-bd04-4bc8-bade-63879ef9d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150170847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3150170847
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.266336457
Short name T29
Test name
Test status
Simulation time 130936109 ps
CPU time 1.39 seconds
Started Jul 25 04:48:05 PM PDT 24
Finished Jul 25 04:48:07 PM PDT 24
Peak memory 197444 kb
Host smart-1bc79eb9-3de1-4730-bbd0-b4af50f7064b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266336457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.266336457
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.142223238
Short name T688
Test name
Test status
Simulation time 192950533 ps
CPU time 4.31 seconds
Started Jul 25 04:47:42 PM PDT 24
Finished Jul 25 04:47:46 PM PDT 24
Peak memory 198392 kb
Host smart-7a1b49a3-374b-4d88-a779-29c62f5c7547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142223238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.142223238
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1948030608
Short name T488
Test name
Test status
Simulation time 43000946 ps
CPU time 1.18 seconds
Started Jul 25 04:47:41 PM PDT 24
Finished Jul 25 04:47:42 PM PDT 24
Peak memory 198448 kb
Host smart-0dfdd07b-c206-4854-b0d4-fa1e79852694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948030608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1948030608
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3990674734
Short name T235
Test name
Test status
Simulation time 155903866 ps
CPU time 1.15 seconds
Started Jul 25 04:47:42 PM PDT 24
Finished Jul 25 04:47:43 PM PDT 24
Peak memory 196344 kb
Host smart-f30add04-7856-4280-9ddc-e02b28cadaaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990674734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3990674734
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3241729745
Short name T434
Test name
Test status
Simulation time 3808584379 ps
CPU time 36.59 seconds
Started Jul 25 04:48:07 PM PDT 24
Finished Jul 25 04:48:44 PM PDT 24
Peak memory 198576 kb
Host smart-d25d821e-c78e-4834-be4e-3d9e76b2779e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241729745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3241729745
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2392534140
Short name T63
Test name
Test status
Simulation time 40433322 ps
CPU time 0.57 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 194388 kb
Host smart-af406a1e-6a24-4b3e-970c-0450e198869a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392534140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2392534140
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3960892036
Short name T218
Test name
Test status
Simulation time 40292723 ps
CPU time 0.75 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:47:38 PM PDT 24
Peak memory 195760 kb
Host smart-e3f870bf-8b05-44b4-8437-8cb7fc759a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960892036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3960892036
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.4116155853
Short name T335
Test name
Test status
Simulation time 480813392 ps
CPU time 25.3 seconds
Started Jul 25 04:47:39 PM PDT 24
Finished Jul 25 04:48:05 PM PDT 24
Peak memory 197656 kb
Host smart-ef4ea5ca-ce07-494d-800d-91962532cf59
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116155853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.4116155853
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1250165620
Short name T631
Test name
Test status
Simulation time 33516818 ps
CPU time 0.68 seconds
Started Jul 25 04:47:45 PM PDT 24
Finished Jul 25 04:47:45 PM PDT 24
Peak memory 195060 kb
Host smart-92dcc32c-fd26-4ef7-b335-03d2f31cbee2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250165620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1250165620
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1940842224
Short name T306
Test name
Test status
Simulation time 59968755 ps
CPU time 0.96 seconds
Started Jul 25 04:47:33 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 196236 kb
Host smart-3980971f-4f80-40bb-8521-d3ff03b0a7f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940842224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1940842224
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1066246217
Short name T322
Test name
Test status
Simulation time 1054435321 ps
CPU time 3.06 seconds
Started Jul 25 04:48:08 PM PDT 24
Finished Jul 25 04:48:11 PM PDT 24
Peak memory 198608 kb
Host smart-7a5a0b3f-7161-4d50-a740-2346d4289003
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066246217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1066246217
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2912483085
Short name T239
Test name
Test status
Simulation time 236772352 ps
CPU time 2.51 seconds
Started Jul 25 04:47:57 PM PDT 24
Finished Jul 25 04:48:05 PM PDT 24
Peak memory 198476 kb
Host smart-e528b59d-4beb-4309-bba7-97727f7136db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912483085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2912483085
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3041661188
Short name T459
Test name
Test status
Simulation time 92235042 ps
CPU time 0.77 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 195716 kb
Host smart-e8ab2623-38cf-4e0c-8185-97713db1fee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041661188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3041661188
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1471148281
Short name T443
Test name
Test status
Simulation time 42733655 ps
CPU time 1.22 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 04:47:37 PM PDT 24
Peak memory 198532 kb
Host smart-106ae2e6-eb04-4fc3-8945-7a04fcbc0217
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471148281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1471148281
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3479250354
Short name T7
Test name
Test status
Simulation time 150303009 ps
CPU time 2.05 seconds
Started Jul 25 04:47:48 PM PDT 24
Finished Jul 25 04:47:50 PM PDT 24
Peak memory 198436 kb
Host smart-363f4963-38ec-4033-8301-a03b9f45eb10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479250354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3479250354
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.558665824
Short name T700
Test name
Test status
Simulation time 347527324 ps
CPU time 1.29 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:47:39 PM PDT 24
Peak memory 197316 kb
Host smart-68a8160a-c9dc-4590-92c4-e48301df6af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558665824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.558665824
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2552009535
Short name T697
Test name
Test status
Simulation time 175142568 ps
CPU time 0.89 seconds
Started Jul 25 04:48:11 PM PDT 24
Finished Jul 25 04:48:12 PM PDT 24
Peak memory 195836 kb
Host smart-e108ef0a-8457-4f27-9b5a-5a8aad2c8db6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552009535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2552009535
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1797095855
Short name T9
Test name
Test status
Simulation time 14514615189 ps
CPU time 173.28 seconds
Started Jul 25 04:47:58 PM PDT 24
Finished Jul 25 04:50:51 PM PDT 24
Peak memory 198648 kb
Host smart-173ad08c-1965-4aeb-93a7-4f8c8c29153e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797095855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1797095855
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2736509689
Short name T143
Test name
Test status
Simulation time 22818562 ps
CPU time 0.6 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:48:29 PM PDT 24
Peak memory 194240 kb
Host smart-0d1b7891-30b3-41af-be96-ecf111ccc8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736509689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2736509689
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.921497629
Short name T686
Test name
Test status
Simulation time 44566386 ps
CPU time 0.83 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:48:29 PM PDT 24
Peak memory 196656 kb
Host smart-280e61ad-66db-4a59-9007-e6c10cde1d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921497629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.921497629
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3483143673
Short name T597
Test name
Test status
Simulation time 515638343 ps
CPU time 12.69 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 04:47:47 PM PDT 24
Peak memory 198440 kb
Host smart-2eeda340-e16b-4da4-92a1-d9c2c42a4e0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483143673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3483143673
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1578794632
Short name T215
Test name
Test status
Simulation time 441185128 ps
CPU time 0.91 seconds
Started Jul 25 04:48:27 PM PDT 24
Finished Jul 25 04:48:28 PM PDT 24
Peak memory 196808 kb
Host smart-d82a59b9-8f59-4d61-afcd-f00e8b18b500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578794632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1578794632
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.384781349
Short name T147
Test name
Test status
Simulation time 35853894 ps
CPU time 0.64 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:33 PM PDT 24
Peak memory 194684 kb
Host smart-9067d853-d158-4d73-ae1e-f97752aa75f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384781349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.384781349
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3133480886
Short name T638
Test name
Test status
Simulation time 69416740 ps
CPU time 1.51 seconds
Started Jul 25 04:47:48 PM PDT 24
Finished Jul 25 04:47:49 PM PDT 24
Peak memory 196808 kb
Host smart-ada1ef95-2c2a-4359-8ec9-8f8c00d37829
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133480886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3133480886
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.13157892
Short name T701
Test name
Test status
Simulation time 173039340 ps
CPU time 1.35 seconds
Started Jul 25 04:47:36 PM PDT 24
Finished Jul 25 04:47:38 PM PDT 24
Peak memory 196404 kb
Host smart-849f96c3-e2d9-4e0a-ab4c-03cb75e4fe7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13157892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.13157892
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2954419703
Short name T630
Test name
Test status
Simulation time 69406036 ps
CPU time 0.86 seconds
Started Jul 25 04:47:30 PM PDT 24
Finished Jul 25 04:47:33 PM PDT 24
Peak memory 197224 kb
Host smart-455f88c6-7f05-4e00-801c-79091ec95a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954419703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2954419703
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2639420582
Short name T483
Test name
Test status
Simulation time 41934058 ps
CPU time 0.92 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 04:47:35 PM PDT 24
Peak memory 196456 kb
Host smart-b8ba5e09-70e2-4473-b8b0-87be69c23b99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639420582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2639420582
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.60059252
Short name T5
Test name
Test status
Simulation time 535776083 ps
CPU time 5.9 seconds
Started Jul 25 04:47:37 PM PDT 24
Finished Jul 25 04:47:43 PM PDT 24
Peak memory 198364 kb
Host smart-077980c5-bc93-4101-a475-62bf084a86a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60059252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand
om_long_reg_writes_reg_reads.60059252
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1229244747
Short name T591
Test name
Test status
Simulation time 192658165 ps
CPU time 1.06 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:48:29 PM PDT 24
Peak memory 196040 kb
Host smart-049bbdca-8376-49a4-84f9-e3db9247f547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229244747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1229244747
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.961125149
Short name T564
Test name
Test status
Simulation time 61553227 ps
CPU time 0.89 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 04:47:36 PM PDT 24
Peak memory 196900 kb
Host smart-3b0a8ed8-91f2-4c8e-a46f-0b8202f856ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961125149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.961125149
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.194694521
Short name T702
Test name
Test status
Simulation time 13319487404 ps
CPU time 161.5 seconds
Started Jul 25 04:47:54 PM PDT 24
Finished Jul 25 04:50:36 PM PDT 24
Peak memory 198536 kb
Host smart-801d498b-df82-409a-8d73-2bf6f106ae7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194694521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.194694521
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.765729603
Short name T141
Test name
Test status
Simulation time 29646130 ps
CPU time 0.54 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:33 PM PDT 24
Peak memory 194384 kb
Host smart-81e2c9c0-38a3-4cac-9b1f-31fa436dbcf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765729603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.765729603
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.4026308524
Short name T279
Test name
Test status
Simulation time 26151913 ps
CPU time 0.68 seconds
Started Jul 25 04:47:35 PM PDT 24
Finished Jul 25 04:47:36 PM PDT 24
Peak memory 194540 kb
Host smart-d71a7189-439a-4ff7-9fdf-8ceced3b4335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026308524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.4026308524
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1043551352
Short name T355
Test name
Test status
Simulation time 4322222473 ps
CPU time 17.78 seconds
Started Jul 25 04:47:42 PM PDT 24
Finished Jul 25 04:48:00 PM PDT 24
Peak memory 197372 kb
Host smart-4de88dd1-9f3d-4649-8577-16e9bd13d944
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043551352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1043551352
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.282397326
Short name T709
Test name
Test status
Simulation time 179020057 ps
CPU time 0.78 seconds
Started Jul 25 04:47:46 PM PDT 24
Finished Jul 25 04:47:52 PM PDT 24
Peak memory 197144 kb
Host smart-51bfc7da-96f2-4b99-a62f-c91c000c0586
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282397326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.282397326
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2147419812
Short name T608
Test name
Test status
Simulation time 174464286 ps
CPU time 0.81 seconds
Started Jul 25 04:47:39 PM PDT 24
Finished Jul 25 04:47:40 PM PDT 24
Peak memory 197864 kb
Host smart-72d6498a-5e64-4f78-aef4-8b1d7fa213a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147419812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2147419812
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1697985747
Short name T99
Test name
Test status
Simulation time 72583782 ps
CPU time 1.91 seconds
Started Jul 25 04:47:58 PM PDT 24
Finished Jul 25 04:48:00 PM PDT 24
Peak memory 198504 kb
Host smart-2e197cf7-d93f-4951-b9d3-80350ddfc022
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697985747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1697985747
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2905420038
Short name T64
Test name
Test status
Simulation time 2399369111 ps
CPU time 2.7 seconds
Started Jul 25 04:47:43 PM PDT 24
Finished Jul 25 04:47:46 PM PDT 24
Peak memory 198568 kb
Host smart-f1422a67-31a6-4ee0-8614-3535f708005c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905420038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2905420038
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2871116972
Short name T171
Test name
Test status
Simulation time 61767302 ps
CPU time 1.02 seconds
Started Jul 25 04:47:26 PM PDT 24
Finished Jul 25 04:47:27 PM PDT 24
Peak memory 196372 kb
Host smart-abc64e2b-4ee1-4927-9287-8b899897db04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871116972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2871116972
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.26624180
Short name T36
Test name
Test status
Simulation time 25426851 ps
CPU time 0.7 seconds
Started Jul 25 04:47:32 PM PDT 24
Finished Jul 25 04:47:33 PM PDT 24
Peak memory 195788 kb
Host smart-ef43cd0c-72d2-4c67-9bcd-9ca77c20b46a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup_
pulldown.26624180
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1457238551
Short name T507
Test name
Test status
Simulation time 116656429 ps
CPU time 5.14 seconds
Started Jul 25 04:47:28 PM PDT 24
Finished Jul 25 04:47:34 PM PDT 24
Peak memory 198468 kb
Host smart-67fca4ef-7b21-4aa3-af94-3f9259448080
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457238551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1457238551
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1744521299
Short name T323
Test name
Test status
Simulation time 210717723 ps
CPU time 1.15 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:48:29 PM PDT 24
Peak memory 196212 kb
Host smart-df6e0725-bc87-4b40-96f7-eacd7d4c8a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744521299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1744521299
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.854961167
Short name T286
Test name
Test status
Simulation time 168550774 ps
CPU time 1.05 seconds
Started Jul 25 04:48:28 PM PDT 24
Finished Jul 25 04:48:29 PM PDT 24
Peak memory 196796 kb
Host smart-584bca7e-b12d-4322-a0cf-c6a051129e63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854961167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.854961167
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3910693224
Short name T2
Test name
Test status
Simulation time 31213967281 ps
CPU time 78.48 seconds
Started Jul 25 04:47:55 PM PDT 24
Finished Jul 25 04:49:14 PM PDT 24
Peak memory 198656 kb
Host smart-6c0e613e-0ab4-4527-a8e5-9ba2df405cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910693224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3910693224
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.952166617
Short name T409
Test name
Test status
Simulation time 272475804024 ps
CPU time 1629.46 seconds
Started Jul 25 04:47:34 PM PDT 24
Finished Jul 25 05:14:44 PM PDT 24
Peak memory 198748 kb
Host smart-ea9f944d-f182-4e50-89ff-95f9971ed635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=952166617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.952166617
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1721511408
Short name T14
Test name
Test status
Simulation time 41729478 ps
CPU time 0.6 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 194584 kb
Host smart-8a42163a-3594-43fb-bb09-7755e555732a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721511408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1721511408
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.4084074062
Short name T539
Test name
Test status
Simulation time 127068957 ps
CPU time 0.83 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:30 PM PDT 24
Peak memory 197392 kb
Host smart-ac5a74a8-fef3-40ac-8f74-1e7646f91c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084074062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.4084074062
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2211854740
Short name T204
Test name
Test status
Simulation time 1472465702 ps
CPU time 8.85 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:41 PM PDT 24
Peak memory 197420 kb
Host smart-ad6c7891-d834-4451-87ed-b19fc3b93888
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211854740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2211854740
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3297095811
Short name T179
Test name
Test status
Simulation time 262742417 ps
CPU time 1 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 197088 kb
Host smart-fa5b2ca0-d38a-458f-a932-57d8f01aad67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297095811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3297095811
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3214224909
Short name T263
Test name
Test status
Simulation time 62027372 ps
CPU time 0.72 seconds
Started Jul 25 04:46:24 PM PDT 24
Finished Jul 25 04:46:25 PM PDT 24
Peak memory 196632 kb
Host smart-df4fcdb6-63df-445e-8762-bbaac55e0eca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214224909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3214224909
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2107058689
Short name T117
Test name
Test status
Simulation time 25306133 ps
CPU time 1.19 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:28 PM PDT 24
Peak memory 197432 kb
Host smart-5483629e-6a7b-48de-ba66-a056525bdb28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107058689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2107058689
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.30809409
Short name T336
Test name
Test status
Simulation time 430850852 ps
CPU time 2.35 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 197480 kb
Host smart-2b0d3ee0-f516-41cc-ac02-9da92c87624d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30809409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.30809409
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3441124350
Short name T557
Test name
Test status
Simulation time 54358327 ps
CPU time 0.99 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:21 PM PDT 24
Peak memory 197144 kb
Host smart-318ed766-2bcd-4495-be54-9131561477c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441124350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3441124350
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.248375627
Short name T694
Test name
Test status
Simulation time 71252492 ps
CPU time 0.76 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:34 PM PDT 24
Peak memory 195904 kb
Host smart-f21443a1-db5f-4daa-81be-5e8ae5bbc354
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248375627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.248375627
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.735821976
Short name T635
Test name
Test status
Simulation time 261529375 ps
CPU time 3.76 seconds
Started Jul 25 04:46:29 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 198392 kb
Host smart-9b147c07-e3c6-42bc-bffb-97bfa5d03d51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735821976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.735821976
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1498581060
Short name T605
Test name
Test status
Simulation time 89564154 ps
CPU time 1.29 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 197256 kb
Host smart-0466b36b-ea84-432d-92f1-bac855cb4f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498581060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1498581060
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1207838506
Short name T104
Test name
Test status
Simulation time 84412725 ps
CPU time 1.47 seconds
Started Jul 25 04:46:22 PM PDT 24
Finished Jul 25 04:46:24 PM PDT 24
Peak memory 197152 kb
Host smart-0a087094-066a-4b16-875a-0ef39061810c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207838506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1207838506
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.189350366
Short name T487
Test name
Test status
Simulation time 7989334948 ps
CPU time 104.1 seconds
Started Jul 25 04:51:00 PM PDT 24
Finished Jul 25 04:52:44 PM PDT 24
Peak memory 198632 kb
Host smart-e1b92029-6837-418f-ae43-c1ad05ea10b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189350366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.189350366
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1879098201
Short name T566
Test name
Test status
Simulation time 12862079 ps
CPU time 0.57 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 194340 kb
Host smart-f6c329e3-8c2f-49e8-94ba-d917652dd950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879098201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1879098201
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3668910688
Short name T449
Test name
Test status
Simulation time 62992315 ps
CPU time 0.72 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 196324 kb
Host smart-06db25cf-b338-45da-b1bc-8c54bfa88c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668910688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3668910688
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.432145891
Short name T334
Test name
Test status
Simulation time 883924149 ps
CPU time 23.71 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:56 PM PDT 24
Peak memory 197376 kb
Host smart-b1344cee-4857-47f2-bb15-d007aaaaed98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432145891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.432145891
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1839578779
Short name T26
Test name
Test status
Simulation time 210130319 ps
CPU time 1.01 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 196840 kb
Host smart-1ff1b5cf-bd6a-48ae-9611-0a801e908acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839578779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1839578779
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.824413290
Short name T662
Test name
Test status
Simulation time 72104996 ps
CPU time 1.17 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 197264 kb
Host smart-f9c6768e-d63e-40f0-aea0-8906c02c8f43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824413290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.824413290
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.765133535
Short name T643
Test name
Test status
Simulation time 87545036 ps
CPU time 3.35 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 198488 kb
Host smart-120e0229-4ca5-4f63-84f6-130daf2f7c92
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765133535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.765133535
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2469813820
Short name T684
Test name
Test status
Simulation time 136873788 ps
CPU time 1.51 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 196432 kb
Host smart-19fe2382-21bc-4372-8759-41656b01304d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469813820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2469813820
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1493257078
Short name T262
Test name
Test status
Simulation time 68035115 ps
CPU time 0.86 seconds
Started Jul 25 04:46:10 PM PDT 24
Finished Jul 25 04:46:11 PM PDT 24
Peak memory 197120 kb
Host smart-6a511efb-cab2-4237-b72e-c178f44c2a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493257078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1493257078
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2150652682
Short name T360
Test name
Test status
Simulation time 28724290 ps
CPU time 1.09 seconds
Started Jul 25 04:46:18 PM PDT 24
Finished Jul 25 04:46:19 PM PDT 24
Peak memory 196352 kb
Host smart-20125295-923f-4227-bc74-e8ca0ae08ff2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150652682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2150652682
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.4291784341
Short name T308
Test name
Test status
Simulation time 335482528 ps
CPU time 5.4 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 198416 kb
Host smart-578b03ae-5d02-49aa-b588-0967cf0834ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291784341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.4291784341
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3188055396
Short name T683
Test name
Test status
Simulation time 83569623 ps
CPU time 1.3 seconds
Started Jul 25 04:46:19 PM PDT 24
Finished Jul 25 04:46:20 PM PDT 24
Peak memory 196872 kb
Host smart-6745a328-f412-4de5-b516-097cf7ff1427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188055396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3188055396
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1558973866
Short name T674
Test name
Test status
Simulation time 252498324 ps
CPU time 1.04 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 195736 kb
Host smart-ccdf5662-d1ad-4977-9ac5-626288476c2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558973866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1558973866
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1983195325
Short name T252
Test name
Test status
Simulation time 6965332187 ps
CPU time 116.17 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:48:17 PM PDT 24
Peak memory 198536 kb
Host smart-cd37b787-baa2-4bc6-b900-72b6f26df798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983195325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1983195325
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3330688855
Short name T524
Test name
Test status
Simulation time 111413301 ps
CPU time 0.77 seconds
Started Jul 25 04:46:04 PM PDT 24
Finished Jul 25 04:46:05 PM PDT 24
Peak memory 195680 kb
Host smart-6deaf6ce-372d-4f90-be83-d10dbdbc5086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330688855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3330688855
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3719641078
Short name T704
Test name
Test status
Simulation time 1967494309 ps
CPU time 20.26 seconds
Started Jul 25 04:46:29 PM PDT 24
Finished Jul 25 04:46:50 PM PDT 24
Peak memory 196084 kb
Host smart-c8e7b232-af0c-4522-bcbf-ecf436069c52
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719641078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3719641078
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1703013287
Short name T710
Test name
Test status
Simulation time 85874756 ps
CPU time 0.73 seconds
Started Jul 25 04:46:38 PM PDT 24
Finished Jul 25 04:46:39 PM PDT 24
Peak memory 196948 kb
Host smart-a8aca902-726c-47d0-8e0b-87829b51599a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703013287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1703013287
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1209750646
Short name T359
Test name
Test status
Simulation time 324992977 ps
CPU time 1.45 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 197412 kb
Host smart-ce55b1da-3b5f-4fdc-a42c-f4c887e30620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209750646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1209750646
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3502607015
Short name T527
Test name
Test status
Simulation time 256123014 ps
CPU time 1.02 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 196832 kb
Host smart-63a2e6e7-b662-49c8-8b9d-361beb2c80d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502607015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3502607015
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.5988488
Short name T327
Test name
Test status
Simulation time 113521889 ps
CPU time 1.37 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 197928 kb
Host smart-408853ce-61d2-4116-b277-436c7f3919b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5988488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.5988488
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2805739321
Short name T585
Test name
Test status
Simulation time 83680940 ps
CPU time 0.61 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:36 PM PDT 24
Peak memory 194660 kb
Host smart-afe69bf3-6f0e-4f0a-8136-123f039bed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805739321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2805739321
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2585728276
Short name T214
Test name
Test status
Simulation time 47589532 ps
CPU time 1.22 seconds
Started Jul 25 04:46:23 PM PDT 24
Finished Jul 25 04:46:24 PM PDT 24
Peak memory 197596 kb
Host smart-cffe548b-ff9f-43a1-b2a1-238394ce1686
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585728276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2585728276
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4289152026
Short name T112
Test name
Test status
Simulation time 254328339 ps
CPU time 5.61 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:40 PM PDT 24
Peak memory 198460 kb
Host smart-10ef6efc-3f8b-48a2-b05f-b1122df7e81d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289152026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4289152026
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1155141374
Short name T312
Test name
Test status
Simulation time 281832339 ps
CPU time 1.35 seconds
Started Jul 25 04:46:30 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 197224 kb
Host smart-65e2a0da-e99a-4a9a-bea6-710400aa937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155141374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1155141374
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2359897009
Short name T532
Test name
Test status
Simulation time 39252558 ps
CPU time 1.06 seconds
Started Jul 25 04:46:21 PM PDT 24
Finished Jul 25 04:46:23 PM PDT 24
Peak memory 196864 kb
Host smart-2b05c620-0c04-44c9-89d9-b30caa351f4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359897009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2359897009
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1634429954
Short name T600
Test name
Test status
Simulation time 65777931599 ps
CPU time 216.73 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:49:57 PM PDT 24
Peak memory 198604 kb
Host smart-1eb918fc-f0ed-46bd-841f-65b0bf695cbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634429954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1634429954
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2478772552
Short name T493
Test name
Test status
Simulation time 38598574 ps
CPU time 0.57 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 195068 kb
Host smart-a392cc8b-b2d1-4c83-b620-3978a41a3dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478772552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2478772552
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.829907430
Short name T324
Test name
Test status
Simulation time 58825490 ps
CPU time 0.73 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 195772 kb
Host smart-f36379ff-3167-4f84-90b1-34f55d71a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829907430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.829907430
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3130624493
Short name T148
Test name
Test status
Simulation time 278935792 ps
CPU time 13.63 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:49 PM PDT 24
Peak memory 197152 kb
Host smart-bd4d4520-0ca8-4ae0-96a6-68f86c54ddad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130624493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3130624493
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.4205421743
Short name T576
Test name
Test status
Simulation time 38087124 ps
CPU time 0.75 seconds
Started Jul 25 04:46:32 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 197024 kb
Host smart-fa50c560-0224-44cb-9007-33963abf8aed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205421743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.4205421743
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1613387391
Short name T692
Test name
Test status
Simulation time 90769147 ps
CPU time 1.35 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:31 PM PDT 24
Peak memory 198520 kb
Host smart-21e38dfe-7682-47ac-b2aa-f6f2f9ccd452
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613387391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1613387391
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1480424037
Short name T292
Test name
Test status
Simulation time 82083281 ps
CPU time 3.09 seconds
Started Jul 25 04:46:30 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 198428 kb
Host smart-147e83e1-1365-4964-8bd6-df8fbcc6b131
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480424037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1480424037
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.657606941
Short name T615
Test name
Test status
Simulation time 73611125 ps
CPU time 2.09 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:38 PM PDT 24
Peak memory 197044 kb
Host smart-025ddea5-e14f-4006-9c75-b9a1329ad562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657606941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.657606941
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.951462873
Short name T228
Test name
Test status
Simulation time 79554257 ps
CPU time 1.38 seconds
Started Jul 25 04:46:20 PM PDT 24
Finished Jul 25 04:46:22 PM PDT 24
Peak memory 197480 kb
Host smart-80236bb4-242e-4ed6-aa3e-f56e3dc30967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951462873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.951462873
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1377884056
Short name T619
Test name
Test status
Simulation time 225118687 ps
CPU time 0.71 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 196456 kb
Host smart-98d63bf7-67d3-4abd-b103-b1540cb2addb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377884056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1377884056
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3211246012
Short name T526
Test name
Test status
Simulation time 408545221 ps
CPU time 4.8 seconds
Started Jul 25 04:46:25 PM PDT 24
Finished Jul 25 04:46:30 PM PDT 24
Peak memory 198372 kb
Host smart-68d9cc3c-bc27-412e-922a-f0d5951d559c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211246012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3211246012
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1188531131
Short name T251
Test name
Test status
Simulation time 68774968 ps
CPU time 1.08 seconds
Started Jul 25 04:46:43 PM PDT 24
Finished Jul 25 04:46:44 PM PDT 24
Peak memory 196028 kb
Host smart-8efc217e-5bd3-492e-b469-ea490b72749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188531131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1188531131
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2504883223
Short name T590
Test name
Test status
Simulation time 356209223 ps
CPU time 0.89 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:46:33 PM PDT 24
Peak memory 195832 kb
Host smart-99855140-8e14-4e11-bd8b-21b57fa1c013
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504883223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2504883223
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.713703672
Short name T455
Test name
Test status
Simulation time 25051211980 ps
CPU time 177.78 seconds
Started Jul 25 04:46:31 PM PDT 24
Finished Jul 25 04:49:30 PM PDT 24
Peak memory 198628 kb
Host smart-80805aca-e9c2-4d13-a263-4e3bb1dc7c01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713703672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.713703672
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3404033792
Short name T11
Test name
Test status
Simulation time 47553217193 ps
CPU time 207.68 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:50:02 PM PDT 24
Peak memory 198688 kb
Host smart-c317a99c-1bf9-4579-a3f2-e2ab4bb30985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3404033792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3404033792
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3737886597
Short name T675
Test name
Test status
Simulation time 22326350 ps
CPU time 0.56 seconds
Started Jul 25 04:46:34 PM PDT 24
Finished Jul 25 04:46:36 PM PDT 24
Peak memory 193204 kb
Host smart-bd014860-d81e-416b-86d5-6526d531b2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737886597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3737886597
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.578925011
Short name T503
Test name
Test status
Simulation time 18231735 ps
CPU time 0.69 seconds
Started Jul 25 04:46:35 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 195452 kb
Host smart-4c098fb0-b932-4995-bf4a-94233dbd1e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578925011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.578925011
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1221883274
Short name T299
Test name
Test status
Simulation time 1702054247 ps
CPU time 15.26 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:44 PM PDT 24
Peak memory 198580 kb
Host smart-a3890367-936a-4b49-b5cb-ae0782cb9132
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221883274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1221883274
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1651888692
Short name T440
Test name
Test status
Simulation time 137132208 ps
CPU time 0.69 seconds
Started Jul 25 04:46:44 PM PDT 24
Finished Jul 25 04:46:45 PM PDT 24
Peak memory 196148 kb
Host smart-087d3955-3434-459d-b28c-fe5c22dc4402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651888692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1651888692
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4009344766
Short name T705
Test name
Test status
Simulation time 168825660 ps
CPU time 1.19 seconds
Started Jul 25 04:46:30 PM PDT 24
Finished Jul 25 04:46:37 PM PDT 24
Peak memory 197584 kb
Host smart-44923649-4ae7-4b25-a334-f9c356ca58a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009344766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4009344766
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1559498163
Short name T588
Test name
Test status
Simulation time 85733989 ps
CPU time 1.87 seconds
Started Jul 25 04:46:37 PM PDT 24
Finished Jul 25 04:46:44 PM PDT 24
Peak memory 196820 kb
Host smart-080b0274-599e-4fce-9792-10455f702c07
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559498163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1559498163
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.654562701
Short name T132
Test name
Test status
Simulation time 242760157 ps
CPU time 2.46 seconds
Started Jul 25 04:46:42 PM PDT 24
Finished Jul 25 04:46:45 PM PDT 24
Peak memory 197484 kb
Host smart-771ec59e-39fd-49af-9baa-18435a5d3c4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654562701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.654562701
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.605840191
Short name T676
Test name
Test status
Simulation time 183150446 ps
CPU time 0.93 seconds
Started Jul 25 04:46:28 PM PDT 24
Finished Jul 25 04:46:29 PM PDT 24
Peak memory 196396 kb
Host smart-7164f03a-c85f-4386-9b42-2a6cf451acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605840191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.605840191
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3915352675
Short name T13
Test name
Test status
Simulation time 21814884 ps
CPU time 0.62 seconds
Started Jul 25 04:46:26 PM PDT 24
Finished Jul 25 04:46:27 PM PDT 24
Peak memory 194620 kb
Host smart-e2369c7f-b4c2-479d-97f8-65a0f280400c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915352675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3915352675
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3799280824
Short name T225
Test name
Test status
Simulation time 115574977 ps
CPU time 5.16 seconds
Started Jul 25 04:46:43 PM PDT 24
Finished Jul 25 04:46:53 PM PDT 24
Peak memory 198472 kb
Host smart-bd364e4c-9526-44db-94ab-0f3eda5358cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799280824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3799280824
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4107057382
Short name T219
Test name
Test status
Simulation time 113894117 ps
CPU time 1.18 seconds
Started Jul 25 04:46:33 PM PDT 24
Finished Jul 25 04:46:35 PM PDT 24
Peak memory 196088 kb
Host smart-123fc38b-418e-4580-ab07-96144445f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107057382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4107057382
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.295198278
Short name T625
Test name
Test status
Simulation time 57468181 ps
CPU time 1.07 seconds
Started Jul 25 04:46:30 PM PDT 24
Finished Jul 25 04:46:32 PM PDT 24
Peak memory 196176 kb
Host smart-4ccafc63-47b4-4ee7-9216-e60aae5d4a34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295198278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.295198278
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3312830302
Short name T343
Test name
Test status
Simulation time 8107031059 ps
CPU time 24.92 seconds
Started Jul 25 04:46:29 PM PDT 24
Finished Jul 25 04:46:54 PM PDT 24
Peak memory 198568 kb
Host smart-4a4e8bf4-38de-422c-8118-aad6dbda2198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312830302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3312830302
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.896391117
Short name T616
Test name
Test status
Simulation time 35130248573 ps
CPU time 738.8 seconds
Started Jul 25 04:46:22 PM PDT 24
Finished Jul 25 04:58:41 PM PDT 24
Peak memory 198736 kb
Host smart-a2cb6b40-fee9-4617-bccd-ae44ac3c31c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=896391117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.896391117
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1416183314
Short name T854
Test name
Test status
Simulation time 283939314 ps
CPU time 1.01 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 197424 kb
Host smart-8beeca90-f03c-4ce4-b398-2a14c8bccd01
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1416183314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1416183314
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.304111115
Short name T918
Test name
Test status
Simulation time 76311900 ps
CPU time 1.19 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 191704 kb
Host smart-430326b4-3557-4dd3-8ec6-f1cdb9529f7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304111115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.304111115
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1606560111
Short name T895
Test name
Test status
Simulation time 75751919 ps
CPU time 1.15 seconds
Started Jul 25 04:44:04 PM PDT 24
Finished Jul 25 04:44:11 PM PDT 24
Peak memory 191732 kb
Host smart-802b30ef-cf43-4f6b-8b6d-e813e93272fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1606560111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1606560111
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.834552250
Short name T933
Test name
Test status
Simulation time 292458163 ps
CPU time 1.27 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 191692 kb
Host smart-846be916-8ba9-4b3e-ba58-0a6753e3b604
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834552250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.834552250
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4239501828
Short name T929
Test name
Test status
Simulation time 61551799 ps
CPU time 1.05 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 191720 kb
Host smart-dd025c81-c242-476d-860d-916c03938479
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4239501828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.4239501828
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2304305753
Short name T871
Test name
Test status
Simulation time 38514898 ps
CPU time 1.11 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 191664 kb
Host smart-e0b6ec42-db3c-4951-81c7-448e12fc59dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304305753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2304305753
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2274852674
Short name T931
Test name
Test status
Simulation time 231116816 ps
CPU time 0.99 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 191540 kb
Host smart-9783b0ee-6664-4ab9-a67b-1e4432b1d3e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2274852674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2274852674
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1057450704
Short name T917
Test name
Test status
Simulation time 98461586 ps
CPU time 0.85 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 196120 kb
Host smart-62952f47-c934-4754-9487-b98a5d668807
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057450704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1057450704
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.275710957
Short name T941
Test name
Test status
Simulation time 321081150 ps
CPU time 1.41 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 191744 kb
Host smart-2a18abce-c20e-4224-9a2e-e82cc59e4eb4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=275710957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.275710957
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3527464960
Short name T920
Test name
Test status
Simulation time 21834940 ps
CPU time 0.76 seconds
Started Jul 25 04:44:15 PM PDT 24
Finished Jul 25 04:44:16 PM PDT 24
Peak memory 191564 kb
Host smart-17201925-5239-4215-a35c-a88113cf86d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527464960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3527464960
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3813099356
Short name T923
Test name
Test status
Simulation time 97410011 ps
CPU time 1.42 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 191704 kb
Host smart-7e37d589-723f-4c3b-a7de-e17b3b36cf29
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3813099356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3813099356
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3777982028
Short name T896
Test name
Test status
Simulation time 42512265 ps
CPU time 1.25 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 191736 kb
Host smart-4f7d320f-6071-46f4-bd7c-14cce4539a6a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777982028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3777982028
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3586700776
Short name T906
Test name
Test status
Simulation time 52704588 ps
CPU time 1.26 seconds
Started Jul 25 04:44:10 PM PDT 24
Finished Jul 25 04:44:11 PM PDT 24
Peak memory 198032 kb
Host smart-de1f1ecf-a8bd-4063-a164-3d51ac0d8d1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3586700776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3586700776
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.76555359
Short name T878
Test name
Test status
Simulation time 207471350 ps
CPU time 0.8 seconds
Started Jul 25 04:44:09 PM PDT 24
Finished Jul 25 04:44:10 PM PDT 24
Peak memory 191624 kb
Host smart-e203f722-fd7d-48dd-a52c-b5dcb146f4f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76555359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.76555359
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3931498768
Short name T921
Test name
Test status
Simulation time 54879490 ps
CPU time 1.4 seconds
Started Jul 25 04:44:16 PM PDT 24
Finished Jul 25 04:44:18 PM PDT 24
Peak memory 191792 kb
Host smart-74988055-c5ba-4831-b413-cb030003fe55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3931498768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3931498768
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.825970285
Short name T858
Test name
Test status
Simulation time 128459197 ps
CPU time 0.82 seconds
Started Jul 25 04:44:09 PM PDT 24
Finished Jul 25 04:44:10 PM PDT 24
Peak memory 191532 kb
Host smart-817cad01-33ff-4915-ba81-257b56aebee8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825970285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.825970285
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.801536884
Short name T940
Test name
Test status
Simulation time 64121122 ps
CPU time 1.19 seconds
Started Jul 25 04:44:44 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 191684 kb
Host smart-fe42f657-e34c-4cd4-96c1-4dadf2242139
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=801536884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.801536884
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2069822887
Short name T911
Test name
Test status
Simulation time 32864062 ps
CPU time 0.8 seconds
Started Jul 25 04:44:20 PM PDT 24
Finished Jul 25 04:44:21 PM PDT 24
Peak memory 191536 kb
Host smart-7e9f4649-b334-4046-9f8e-5618f9b4494a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069822887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2069822887
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4177308547
Short name T857
Test name
Test status
Simulation time 570623793 ps
CPU time 1.24 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 196808 kb
Host smart-5f7ab465-8bbd-4eb6-98dd-c0d933a83fae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4177308547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.4177308547
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2742212570
Short name T861
Test name
Test status
Simulation time 159134452 ps
CPU time 0.98 seconds
Started Jul 25 04:44:08 PM PDT 24
Finished Jul 25 04:44:09 PM PDT 24
Peak memory 191680 kb
Host smart-bacd91eb-9280-41ff-b2f4-17ec87b88950
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742212570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2742212570
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.224350001
Short name T863
Test name
Test status
Simulation time 36479030 ps
CPU time 0.93 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:49 PM PDT 24
Peak memory 191560 kb
Host smart-9d4677e5-1318-42bb-9697-90580a0868bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=224350001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.224350001
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2342437792
Short name T862
Test name
Test status
Simulation time 108317944 ps
CPU time 1.04 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 197252 kb
Host smart-60f553b9-1bb2-4b56-a78e-b59cbcf3c2d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342437792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2342437792
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2086767292
Short name T859
Test name
Test status
Simulation time 50561494 ps
CPU time 0.95 seconds
Started Jul 25 04:44:29 PM PDT 24
Finished Jul 25 04:44:30 PM PDT 24
Peak memory 196128 kb
Host smart-395fa602-2efa-4f6a-909e-df20c4326241
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2086767292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2086767292
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1040887642
Short name T936
Test name
Test status
Simulation time 314729034 ps
CPU time 0.93 seconds
Started Jul 25 04:44:46 PM PDT 24
Finished Jul 25 04:44:47 PM PDT 24
Peak memory 197388 kb
Host smart-5fd5e292-6e76-4b87-b6bc-bfe2858c8b2a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040887642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1040887642
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.978237392
Short name T934
Test name
Test status
Simulation time 71419711 ps
CPU time 1.34 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 191712 kb
Host smart-7e663ae1-e054-4d9a-b83b-31c4f037fc00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=978237392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.978237392
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.557164815
Short name T897
Test name
Test status
Simulation time 205842763 ps
CPU time 1.41 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 198032 kb
Host smart-b205e9a0-1770-42bf-afc6-9318dbc1b8ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557164815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.557164815
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.189442773
Short name T855
Test name
Test status
Simulation time 229555179 ps
CPU time 1.26 seconds
Started Jul 25 04:44:08 PM PDT 24
Finished Jul 25 04:44:10 PM PDT 24
Peak memory 191728 kb
Host smart-baf344c8-ad4f-4f5d-96b9-35b70dae16ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=189442773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.189442773
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2507724740
Short name T935
Test name
Test status
Simulation time 45278753 ps
CPU time 1.33 seconds
Started Jul 25 04:43:58 PM PDT 24
Finished Jul 25 04:44:00 PM PDT 24
Peak memory 191692 kb
Host smart-356ee558-e50a-433c-a79d-df58f6208349
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507724740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2507724740
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1897947578
Short name T867
Test name
Test status
Simulation time 40414950 ps
CPU time 0.93 seconds
Started Jul 25 04:43:57 PM PDT 24
Finished Jul 25 04:43:58 PM PDT 24
Peak memory 191552 kb
Host smart-19c4a8b6-38ef-4159-a6d8-223911373800
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1897947578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1897947578
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1299247854
Short name T932
Test name
Test status
Simulation time 400699747 ps
CPU time 1.14 seconds
Started Jul 25 04:44:10 PM PDT 24
Finished Jul 25 04:44:11 PM PDT 24
Peak memory 191756 kb
Host smart-ffd33c38-8796-4810-ac61-fca06721e715
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299247854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1299247854
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1122945920
Short name T908
Test name
Test status
Simulation time 128478992 ps
CPU time 1.05 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 198080 kb
Host smart-b06c9c10-4180-4f3d-9cdd-6535f2f04e5d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1122945920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1122945920
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1302289032
Short name T885
Test name
Test status
Simulation time 45231528 ps
CPU time 1.04 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 197204 kb
Host smart-92ec2164-a14f-4753-9220-77dff17deef5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302289032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1302289032
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.109767409
Short name T856
Test name
Test status
Simulation time 96967924 ps
CPU time 0.98 seconds
Started Jul 25 04:44:16 PM PDT 24
Finished Jul 25 04:44:17 PM PDT 24
Peak memory 191704 kb
Host smart-8c868266-3493-4d71-9f7e-46ae8e939fc0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=109767409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.109767409
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3011887802
Short name T881
Test name
Test status
Simulation time 49767557 ps
CPU time 0.9 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 196264 kb
Host smart-24f3fda4-f83a-437c-805f-f84599674d36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011887802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3011887802
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3068787696
Short name T880
Test name
Test status
Simulation time 59538320 ps
CPU time 1.3 seconds
Started Jul 25 04:44:34 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 197084 kb
Host smart-d12b6674-08d0-40c4-9655-b7604f1e5190
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3068787696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3068787696
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2943626210
Short name T922
Test name
Test status
Simulation time 190261219 ps
CPU time 1.45 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:42 PM PDT 24
Peak memory 191736 kb
Host smart-1bfed4b6-15fc-453a-850d-e97093362403
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943626210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2943626210
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.673430871
Short name T901
Test name
Test status
Simulation time 54865139 ps
CPU time 0.75 seconds
Started Jul 25 04:44:03 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 191520 kb
Host smart-ebd65342-1dc9-48ce-9c6b-453ef2da3584
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=673430871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.673430871
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2439036438
Short name T938
Test name
Test status
Simulation time 290694470 ps
CPU time 1.21 seconds
Started Jul 25 04:44:05 PM PDT 24
Finished Jul 25 04:44:07 PM PDT 24
Peak memory 198120 kb
Host smart-be4e98bc-d35b-40ef-a63c-246f69a85ea7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439036438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2439036438
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1560024584
Short name T851
Test name
Test status
Simulation time 134009846 ps
CPU time 0.88 seconds
Started Jul 25 04:43:59 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 191544 kb
Host smart-ae541192-00ca-47d7-94c0-90b983eeeea4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1560024584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1560024584
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2265779270
Short name T903
Test name
Test status
Simulation time 58608480 ps
CPU time 0.92 seconds
Started Jul 25 04:44:15 PM PDT 24
Finished Jul 25 04:44:16 PM PDT 24
Peak memory 196340 kb
Host smart-24168000-8d24-439b-ae7e-090e606c116c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265779270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2265779270
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3843815179
Short name T889
Test name
Test status
Simulation time 282504874 ps
CPU time 1.01 seconds
Started Jul 25 04:44:12 PM PDT 24
Finished Jul 25 04:44:14 PM PDT 24
Peak memory 191752 kb
Host smart-6e5b23c9-d867-4ee2-afec-d86500d0fb8b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3843815179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3843815179
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1950648963
Short name T875
Test name
Test status
Simulation time 143985144 ps
CPU time 0.94 seconds
Started Jul 25 04:44:21 PM PDT 24
Finished Jul 25 04:44:23 PM PDT 24
Peak memory 191448 kb
Host smart-2c3f331f-8d8b-4773-9ae0-21e26e1b6a9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950648963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1950648963
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.282187660
Short name T869
Test name
Test status
Simulation time 76042603 ps
CPU time 1.23 seconds
Started Jul 25 04:44:42 PM PDT 24
Finished Jul 25 04:44:43 PM PDT 24
Peak memory 191700 kb
Host smart-c406e531-4011-4cff-bf8f-33dd8b972e68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=282187660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.282187660
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3914106508
Short name T882
Test name
Test status
Simulation time 144017032 ps
CPU time 1.07 seconds
Started Jul 25 04:44:28 PM PDT 24
Finished Jul 25 04:44:30 PM PDT 24
Peak memory 191744 kb
Host smart-95fcb759-2c24-43af-b412-4367328c2087
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914106508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3914106508
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3388422368
Short name T910
Test name
Test status
Simulation time 244250481 ps
CPU time 1.07 seconds
Started Jul 25 04:44:04 PM PDT 24
Finished Jul 25 04:44:05 PM PDT 24
Peak memory 191756 kb
Host smart-00171c84-cf36-4420-86ae-52fbcde4aeb1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3388422368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3388422368
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3884303815
Short name T913
Test name
Test status
Simulation time 38706596 ps
CPU time 0.91 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 196212 kb
Host smart-e4a492fa-f515-4369-b74f-f4fbb9043c6c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884303815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3884303815
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1004237150
Short name T846
Test name
Test status
Simulation time 73595241 ps
CPU time 1.28 seconds
Started Jul 25 04:44:09 PM PDT 24
Finished Jul 25 04:44:11 PM PDT 24
Peak memory 198064 kb
Host smart-f51e8097-a886-4691-9060-b9b9254c28c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1004237150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1004237150
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1607852077
Short name T891
Test name
Test status
Simulation time 212810525 ps
CPU time 1.1 seconds
Started Jul 25 04:44:03 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 197588 kb
Host smart-2da834dd-cd01-49d1-bdb7-bf9f7e5624b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607852077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1607852077
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2950914464
Short name T899
Test name
Test status
Simulation time 142030772 ps
CPU time 0.98 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 197420 kb
Host smart-192657ae-73d6-4f5f-901e-a70464d5ff0d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2950914464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2950914464
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1852610116
Short name T870
Test name
Test status
Simulation time 73039177 ps
CPU time 1.23 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 191680 kb
Host smart-00e79535-90a8-4d28-b12d-b5b9e31ae618
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852610116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1852610116
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1213483501
Short name T850
Test name
Test status
Simulation time 195811392 ps
CPU time 1.24 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 191744 kb
Host smart-85482f05-675c-4edd-a3c2-f6474cdf7d7c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1213483501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1213483501
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3602777565
Short name T865
Test name
Test status
Simulation time 152338882 ps
CPU time 1.08 seconds
Started Jul 25 04:44:57 PM PDT 24
Finished Jul 25 04:44:58 PM PDT 24
Peak memory 191708 kb
Host smart-ee43933e-d300-4593-8d8f-858cf270d8b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602777565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3602777565
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3028684672
Short name T864
Test name
Test status
Simulation time 60124283 ps
CPU time 1.14 seconds
Started Jul 25 04:44:42 PM PDT 24
Finished Jul 25 04:44:44 PM PDT 24
Peak memory 191788 kb
Host smart-419c4e8f-63c7-49c0-8e1b-b68781946b57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3028684672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3028684672
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.391047274
Short name T877
Test name
Test status
Simulation time 75379373 ps
CPU time 1.15 seconds
Started Jul 25 04:44:05 PM PDT 24
Finished Jul 25 04:44:07 PM PDT 24
Peak memory 191704 kb
Host smart-734e24cc-1e42-403d-ad75-30a810074b85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391047274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.391047274
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1272820777
Short name T943
Test name
Test status
Simulation time 126196418 ps
CPU time 1.07 seconds
Started Jul 25 04:44:33 PM PDT 24
Finished Jul 25 04:44:34 PM PDT 24
Peak memory 191812 kb
Host smart-466b9ae8-ddea-4a79-8bfe-2154eed25e62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1272820777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1272820777
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.520338423
Short name T872
Test name
Test status
Simulation time 50367989 ps
CPU time 0.75 seconds
Started Jul 25 04:44:16 PM PDT 24
Finished Jul 25 04:44:17 PM PDT 24
Peak memory 191528 kb
Host smart-e4055d44-b9a7-47c5-b037-d2dbec7d107b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520338423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.520338423
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.743502963
Short name T847
Test name
Test status
Simulation time 94982618 ps
CPU time 0.85 seconds
Started Jul 25 04:44:26 PM PDT 24
Finished Jul 25 04:44:27 PM PDT 24
Peak memory 197204 kb
Host smart-ce08ce15-0d98-4288-9bc7-5c8bc568852f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=743502963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.743502963
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3485491903
Short name T887
Test name
Test status
Simulation time 61561644 ps
CPU time 1.08 seconds
Started Jul 25 04:44:36 PM PDT 24
Finished Jul 25 04:44:37 PM PDT 24
Peak memory 191708 kb
Host smart-f3ec79d8-a6fe-41cb-a4e9-e6d168283ec5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485491903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3485491903
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3222669889
Short name T909
Test name
Test status
Simulation time 281482265 ps
CPU time 1.39 seconds
Started Jul 25 04:44:36 PM PDT 24
Finished Jul 25 04:44:38 PM PDT 24
Peak memory 191704 kb
Host smart-251382c1-34c3-4502-b8a9-7712ce8288ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3222669889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3222669889
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3587161132
Short name T919
Test name
Test status
Simulation time 315586771 ps
CPU time 1.29 seconds
Started Jul 25 04:44:26 PM PDT 24
Finished Jul 25 04:44:28 PM PDT 24
Peak memory 198052 kb
Host smart-9fb403ab-74fb-43f2-a6e9-b3a3b63a43c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587161132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3587161132
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2884010051
Short name T926
Test name
Test status
Simulation time 84610041 ps
CPU time 1.2 seconds
Started Jul 25 04:44:20 PM PDT 24
Finished Jul 25 04:44:21 PM PDT 24
Peak memory 191736 kb
Host smart-d0c3717d-9ad2-41b6-8b15-ecc9dec1a452
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2884010051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2884010051
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.32285517
Short name T930
Test name
Test status
Simulation time 55777034 ps
CPU time 1.54 seconds
Started Jul 25 04:44:32 PM PDT 24
Finished Jul 25 04:44:34 PM PDT 24
Peak memory 198024 kb
Host smart-a4393403-ee32-47e8-aa65-a5e2e0a8f793
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32285517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.32285517
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.193938928
Short name T924
Test name
Test status
Simulation time 39414878 ps
CPU time 1.15 seconds
Started Jul 25 04:44:45 PM PDT 24
Finished Jul 25 04:44:46 PM PDT 24
Peak memory 198080 kb
Host smart-b466a156-1bd2-4e84-8b59-011654180f4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=193938928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.193938928
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2293940560
Short name T848
Test name
Test status
Simulation time 493723157 ps
CPU time 1.14 seconds
Started Jul 25 04:44:44 PM PDT 24
Finished Jul 25 04:44:45 PM PDT 24
Peak memory 198104 kb
Host smart-509fd897-42e9-4420-bcdc-732a9a463a10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293940560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2293940560
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2636479853
Short name T904
Test name
Test status
Simulation time 41410434 ps
CPU time 1.22 seconds
Started Jul 25 04:44:04 PM PDT 24
Finished Jul 25 04:44:06 PM PDT 24
Peak memory 198068 kb
Host smart-ea65f80b-6bd9-4902-ab62-6e9d39a0c332
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2636479853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2636479853
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1031433962
Short name T902
Test name
Test status
Simulation time 539930936 ps
CPU time 1.08 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:40 PM PDT 24
Peak memory 191732 kb
Host smart-f1593662-6fc3-4412-88b8-05b3bcf7599e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031433962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1031433962
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1888454599
Short name T886
Test name
Test status
Simulation time 39150772 ps
CPU time 1.12 seconds
Started Jul 25 04:44:27 PM PDT 24
Finished Jul 25 04:44:29 PM PDT 24
Peak memory 191776 kb
Host smart-9ad5d4da-ed17-4476-829c-02b0b368f931
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1888454599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1888454599
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4134883060
Short name T914
Test name
Test status
Simulation time 22414144 ps
CPU time 0.79 seconds
Started Jul 25 04:44:53 PM PDT 24
Finished Jul 25 04:44:55 PM PDT 24
Peak memory 196296 kb
Host smart-24e9d5ff-3be0-4e08-abf7-5e1008f6a752
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134883060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4134883060
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4062871162
Short name T915
Test name
Test status
Simulation time 49999598 ps
CPU time 1.24 seconds
Started Jul 25 04:44:05 PM PDT 24
Finished Jul 25 04:44:07 PM PDT 24
Peak memory 191704 kb
Host smart-2a9cbed4-1df9-4d85-b6e0-6061c14728ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4062871162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4062871162
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2531709654
Short name T876
Test name
Test status
Simulation time 723563096 ps
CPU time 1.22 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 191736 kb
Host smart-a79f9aa6-b46d-4687-a61c-31210fd1258f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531709654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2531709654
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.171619683
Short name T852
Test name
Test status
Simulation time 144993330 ps
CPU time 0.92 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 197880 kb
Host smart-8ce37f77-49a1-4494-b3f0-536813ad5ceb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=171619683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.171619683
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1597073850
Short name T866
Test name
Test status
Simulation time 70964322 ps
CPU time 1.32 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 198068 kb
Host smart-8d27ea3d-1c6d-43ac-93b2-2fa2fe6e4ceb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597073850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1597073850
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.159214968
Short name T884
Test name
Test status
Simulation time 48613200 ps
CPU time 1.07 seconds
Started Jul 25 04:44:22 PM PDT 24
Finished Jul 25 04:44:23 PM PDT 24
Peak memory 197292 kb
Host smart-11ddcb9e-10ff-40cd-b4c8-5cec1c8a9ee9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=159214968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.159214968
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2710890103
Short name T874
Test name
Test status
Simulation time 67279145 ps
CPU time 1.26 seconds
Started Jul 25 04:44:39 PM PDT 24
Finished Jul 25 04:44:40 PM PDT 24
Peak memory 191824 kb
Host smart-b9088c4d-dd20-45b7-bf1c-91600372ea06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710890103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2710890103
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3446240817
Short name T844
Test name
Test status
Simulation time 35236998 ps
CPU time 1.05 seconds
Started Jul 25 04:44:08 PM PDT 24
Finished Jul 25 04:44:10 PM PDT 24
Peak memory 191768 kb
Host smart-f4df574d-ee26-4b32-bf2b-324e56a8e85d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3446240817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3446240817
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2222764616
Short name T883
Test name
Test status
Simulation time 190511022 ps
CPU time 1.46 seconds
Started Jul 25 04:44:31 PM PDT 24
Finished Jul 25 04:44:32 PM PDT 24
Peak memory 191728 kb
Host smart-1ffcffd8-dd8e-496b-948b-793b8f1185eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222764616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2222764616
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4276774262
Short name T845
Test name
Test status
Simulation time 41920112 ps
CPU time 0.94 seconds
Started Jul 25 04:44:27 PM PDT 24
Finished Jul 25 04:44:29 PM PDT 24
Peak memory 191524 kb
Host smart-dacf19de-72b9-4e21-b9fa-425769102e7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4276774262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.4276774262
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.811005787
Short name T894
Test name
Test status
Simulation time 30497034 ps
CPU time 0.7 seconds
Started Jul 25 04:44:48 PM PDT 24
Finished Jul 25 04:44:48 PM PDT 24
Peak memory 195244 kb
Host smart-82c90d3d-325d-45b1-b608-7832ea591cda
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811005787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.811005787
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1990372738
Short name T879
Test name
Test status
Simulation time 179622029 ps
CPU time 0.72 seconds
Started Jul 25 04:44:35 PM PDT 24
Finished Jul 25 04:44:36 PM PDT 24
Peak memory 196032 kb
Host smart-25139564-8606-4355-98af-cf2ffdd8a1f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1990372738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1990372738
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1812919152
Short name T916
Test name
Test status
Simulation time 56089912 ps
CPU time 0.96 seconds
Started Jul 25 04:44:29 PM PDT 24
Finished Jul 25 04:44:30 PM PDT 24
Peak memory 191488 kb
Host smart-da4cd028-8ec4-4c7b-ae14-e440d4f5579d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812919152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1812919152
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.983534552
Short name T868
Test name
Test status
Simulation time 74132740 ps
CPU time 1.21 seconds
Started Jul 25 04:44:47 PM PDT 24
Finished Jul 25 04:44:48 PM PDT 24
Peak memory 191760 kb
Host smart-98587d36-9150-4e86-803a-1a3124741d4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=983534552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.983534552
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3346470468
Short name T927
Test name
Test status
Simulation time 536164732 ps
CPU time 1.24 seconds
Started Jul 25 04:44:30 PM PDT 24
Finished Jul 25 04:44:31 PM PDT 24
Peak memory 191664 kb
Host smart-8169b15d-4ab6-4abd-8094-ad0cb028ad10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346470468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3346470468
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1792820746
Short name T873
Test name
Test status
Simulation time 50490088 ps
CPU time 1.45 seconds
Started Jul 25 04:44:30 PM PDT 24
Finished Jul 25 04:44:32 PM PDT 24
Peak memory 191672 kb
Host smart-7cb13d60-afa8-4a56-9de5-7bac9cdbdba1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1792820746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1792820746
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1855473390
Short name T893
Test name
Test status
Simulation time 714609341 ps
CPU time 1.19 seconds
Started Jul 25 04:44:36 PM PDT 24
Finished Jul 25 04:44:37 PM PDT 24
Peak memory 191664 kb
Host smart-37c39f13-d45c-4330-8e98-fcb82cf06b8c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855473390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1855473390
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1529557035
Short name T939
Test name
Test status
Simulation time 53969963 ps
CPU time 1.34 seconds
Started Jul 25 04:44:41 PM PDT 24
Finished Jul 25 04:44:43 PM PDT 24
Peak memory 191752 kb
Host smart-37eeb040-caf4-4cfe-9c9a-3dcbe322d6a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1529557035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1529557035
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.204821715
Short name T892
Test name
Test status
Simulation time 84044752 ps
CPU time 1.35 seconds
Started Jul 25 04:44:29 PM PDT 24
Finished Jul 25 04:44:31 PM PDT 24
Peak memory 191696 kb
Host smart-65fee9a3-80fd-43b4-bceb-28b1bb94e512
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204821715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.204821715
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3833174781
Short name T860
Test name
Test status
Simulation time 35504292 ps
CPU time 0.87 seconds
Started Jul 25 04:44:47 PM PDT 24
Finished Jul 25 04:44:48 PM PDT 24
Peak memory 191548 kb
Host smart-d40b9515-1906-4e26-b83b-8f275eb8b9ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3833174781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3833174781
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.227537981
Short name T937
Test name
Test status
Simulation time 110305892 ps
CPU time 0.76 seconds
Started Jul 25 04:44:33 PM PDT 24
Finished Jul 25 04:44:34 PM PDT 24
Peak memory 191524 kb
Host smart-de46367d-a03b-405d-bf97-93497c71767c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227537981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.227537981
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1806264123
Short name T853
Test name
Test status
Simulation time 794216330 ps
CPU time 1.28 seconds
Started Jul 25 04:44:32 PM PDT 24
Finished Jul 25 04:44:33 PM PDT 24
Peak memory 191716 kb
Host smart-e1cd5444-054e-49a6-a9f4-1df2ec4bd254
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1806264123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1806264123
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2475597358
Short name T890
Test name
Test status
Simulation time 23967383 ps
CPU time 0.76 seconds
Started Jul 25 04:44:40 PM PDT 24
Finished Jul 25 04:44:41 PM PDT 24
Peak memory 196116 kb
Host smart-35b7ada2-96cc-45b0-9139-7ab35fd97af0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475597358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2475597358
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.65458813
Short name T905
Test name
Test status
Simulation time 682983078 ps
CPU time 1.25 seconds
Started Jul 25 04:44:03 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 191768 kb
Host smart-a605e884-3a46-4f63-82e8-c5784602af06
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=65458813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.65458813
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3354943972
Short name T925
Test name
Test status
Simulation time 85987480 ps
CPU time 1.29 seconds
Started Jul 25 04:44:08 PM PDT 24
Finished Jul 25 04:44:09 PM PDT 24
Peak memory 191704 kb
Host smart-893180d1-a014-48e8-ac09-416c4fea3366
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354943972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3354943972
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3362036796
Short name T888
Test name
Test status
Simulation time 50048933 ps
CPU time 1.2 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 191752 kb
Host smart-cf18c032-f8f1-4890-8da1-4daf4fc63284
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3362036796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3362036796
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1093737032
Short name T907
Test name
Test status
Simulation time 186177455 ps
CPU time 1.32 seconds
Started Jul 25 04:44:01 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 198108 kb
Host smart-2255a0e8-7953-4d06-9ab8-7601ebe22452
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093737032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1093737032
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.4152847303
Short name T849
Test name
Test status
Simulation time 237985894 ps
CPU time 1.26 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:02 PM PDT 24
Peak memory 191704 kb
Host smart-dcf4b0d6-beb0-4eb4-b16d-8916e80dd3a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4152847303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.4152847303
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2125923739
Short name T928
Test name
Test status
Simulation time 187624676 ps
CPU time 1.34 seconds
Started Jul 25 04:44:03 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 198108 kb
Host smart-78e71025-5d71-4269-93fb-f2a08eb46540
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125923739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2125923739
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3993838371
Short name T942
Test name
Test status
Simulation time 126905742 ps
CPU time 1.11 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:04 PM PDT 24
Peak memory 198016 kb
Host smart-fb62459c-2c30-41fc-a8aa-a3abd9508e10
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3993838371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3993838371
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3381327054
Short name T898
Test name
Test status
Simulation time 150892703 ps
CPU time 1.26 seconds
Started Jul 25 04:44:02 PM PDT 24
Finished Jul 25 04:44:03 PM PDT 24
Peak memory 191716 kb
Host smart-9cf246c8-7028-488c-adaa-64d0ad4bce2f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381327054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3381327054
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3476901354
Short name T900
Test name
Test status
Simulation time 418462360 ps
CPU time 1.32 seconds
Started Jul 25 04:44:38 PM PDT 24
Finished Jul 25 04:44:39 PM PDT 24
Peak memory 191776 kb
Host smart-4658eaaa-4bb9-449c-b2ab-3fb1441ae599
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3476901354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3476901354
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249728021
Short name T912
Test name
Test status
Simulation time 52446151 ps
CPU time 1.29 seconds
Started Jul 25 04:44:00 PM PDT 24
Finished Jul 25 04:44:01 PM PDT 24
Peak memory 191688 kb
Host smart-eb3f0c49-fdb4-49bb-ab01-d948997e1178
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249728021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.249728021
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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