Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4876058	1			T28	1		T29	25		T30	6931
all_pins[1]	4876058	1			T28	1		T29	25		T30	6931
all_pins[2]	4876058	1			T28	1		T29	25		T30	6931
all_pins[3]	4876058	1			T28	1		T29	25		T30	6931
all_pins[4]	4876058	1			T28	1		T29	25		T30	6931
all_pins[5]	4876058	1			T28	1		T29	25		T30	6931
all_pins[6]	4876058	1			T28	1		T29	25		T30	6931
all_pins[7]	4876058	1			T28	1		T29	25		T30	6931
all_pins[8]	4876058	1			T28	1		T29	25		T30	6931
all_pins[9]	4876058	1			T28	1		T29	25		T30	6931
all_pins[10]	4876058	1			T28	1		T29	25		T30	6931
all_pins[11]	4876058	1			T28	1		T29	25		T30	6931
all_pins[12]	4876058	1			T28	1		T29	25		T30	6931
all_pins[13]	4876058	1			T28	1		T29	25		T30	6931
all_pins[14]	4876058	1			T28	1		T29	25		T30	6931
all_pins[15]	4876058	1			T28	1		T29	25		T30	6931
all_pins[16]	4876058	1			T28	1		T29	25		T30	6931
all_pins[17]	4876058	1			T28	1		T29	25		T30	6931
all_pins[18]	4876058	1			T28	1		T29	25		T30	6931
all_pins[19]	4876058	1			T28	1		T29	25		T30	6931
all_pins[20]	4876058	1			T28	1		T29	25		T30	6931
all_pins[21]	4876058	1			T28	1		T29	25		T30	6931
all_pins[22]	4876058	1			T28	1		T29	25		T30	6931
all_pins[23]	4876058	1			T28	1		T29	25		T30	6931
all_pins[24]	4876058	1			T28	1		T29	25		T30	6931
all_pins[25]	4876058	1			T28	1		T29	25		T30	6931
all_pins[26]	4876058	1			T28	1		T29	25		T30	6931
all_pins[27]	4876058	1			T28	1		T29	25		T30	6931
all_pins[28]	4876058	1			T28	1		T29	25		T30	6931
all_pins[29]	4876058	1			T28	1		T29	25		T30	6931
all_pins[30]	4876058	1			T28	1		T29	25		T30	6931
all_pins[31]	4876058	1			T28	1		T29	25		T30	6931

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	96944252	1			T28	32		T29	423		T30	138186
values[0x1]	59089604	1			T29	377		T30	83606		T32	735
transitions[0x0=>0x1]	35436795	1			T29	170		T30	50419		T32	349
transitions[0x1=>0x0]	35436644	1			T29	170		T30	50418		T32	348

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3026696	1			T28	1		T29	15		T30	4398
all_pins[0]	values[0x1]	1849362	1			T29	10		T30	2533		T32	30
all_pins[0]	transitions[0x0=>0x1]	1149122	1			T29	6		T30	1631		T32	17
all_pins[0]	transitions[0x1=>0x0]	1139476	1			T29	2		T30	1676		T32	8
all_pins[1]	values[0x0]	3031970	1			T28	1		T29	16		T30	4286
all_pins[1]	values[0x1]	1844088	1			T29	9		T30	2645		T32	24
all_pins[1]	transitions[0x0=>0x1]	1103913	1			T29	3		T30	1530		T32	5
all_pins[1]	transitions[0x1=>0x0]	1109187	1			T29	4		T30	1418		T32	11
all_pins[2]	values[0x0]	3029659	1			T28	1		T29	16		T30	4601
all_pins[2]	values[0x1]	1846399	1			T29	9		T30	2330		T32	26
all_pins[2]	transitions[0x0=>0x1]	1107902	1			T29	4		T30	1366		T32	10
all_pins[2]	transitions[0x1=>0x0]	1105591	1			T29	4		T30	1681		T32	8
all_pins[3]	values[0x0]	3029788	1			T28	1		T29	19		T30	4250
all_pins[3]	values[0x1]	1846270	1			T29	6		T30	2681		T32	24
all_pins[3]	transitions[0x0=>0x1]	1107349	1			T29	3		T30	1730		T32	11
all_pins[3]	transitions[0x1=>0x0]	1107478	1			T29	6		T30	1379		T32	13
all_pins[4]	values[0x0]	3030539	1			T28	1		T29	16		T30	4272
all_pins[4]	values[0x1]	1845519	1			T29	9		T30	2659		T32	18
all_pins[4]	transitions[0x0=>0x1]	1104797	1			T29	7		T30	1593		T32	7
all_pins[4]	transitions[0x1=>0x0]	1105548	1			T29	4		T30	1615		T32	13
all_pins[5]	values[0x0]	3034487	1			T28	1		T29	18		T30	4439
all_pins[5]	values[0x1]	1841571	1			T29	7		T30	2492		T32	26
all_pins[5]	transitions[0x0=>0x1]	1103864	1			T29	2		T30	1466		T32	13
all_pins[5]	transitions[0x1=>0x0]	1107812	1			T29	4		T30	1633		T32	5
all_pins[6]	values[0x0]	3036999	1			T28	1		T29	18		T30	4322
all_pins[6]	values[0x1]	1839059	1			T29	7		T30	2609		T32	20
all_pins[6]	transitions[0x0=>0x1]	1100919	1			T29	5		T30	1624		T32	11
all_pins[6]	transitions[0x1=>0x0]	1103431	1			T29	5		T30	1507		T32	17
all_pins[7]	values[0x0]	3035395	1			T28	1		T29	11		T30	4444
all_pins[7]	values[0x1]	1840663	1			T29	14		T30	2487		T32	22
all_pins[7]	transitions[0x0=>0x1]	1108476	1			T29	9		T30	1467		T32	12
all_pins[7]	transitions[0x1=>0x0]	1106872	1			T29	2		T30	1589		T32	10
all_pins[8]	values[0x0]	3030642	1			T28	1		T29	11		T30	4169
all_pins[8]	values[0x1]	1845416	1			T29	14		T30	2762		T32	14
all_pins[8]	transitions[0x0=>0x1]	1107730	1			T29	8		T30	1712		T32	7
all_pins[8]	transitions[0x1=>0x0]	1102977	1			T29	8		T30	1437		T32	15
all_pins[9]	values[0x0]	3032858	1			T28	1		T29	11		T30	4503
all_pins[9]	values[0x1]	1843200	1			T29	14		T30	2428		T32	25
all_pins[9]	transitions[0x0=>0x1]	1106209	1			T29	6		T30	1369		T32	17
all_pins[9]	transitions[0x1=>0x0]	1108425	1			T29	6		T30	1703		T32	6
all_pins[10]	values[0x0]	3032724	1			T28	1		T29	11		T30	4212
all_pins[10]	values[0x1]	1843334	1			T29	14		T30	2719		T32	26
all_pins[10]	transitions[0x0=>0x1]	1106216	1			T29	5		T30	1745		T32	12
all_pins[10]	transitions[0x1=>0x0]	1106082	1			T29	5		T30	1454		T32	11
all_pins[11]	values[0x0]	3027801	1			T28	1		T29	9		T30	4373
all_pins[11]	values[0x1]	1848257	1			T29	16		T30	2558		T32	23
all_pins[11]	transitions[0x0=>0x1]	1109182	1			T29	3		T30	1557		T32	11
all_pins[11]	transitions[0x1=>0x0]	1104259	1			T29	1		T30	1718		T32	14
all_pins[12]	values[0x0]	3026108	1			T28	1		T29	8		T30	4275
all_pins[12]	values[0x1]	1849950	1			T29	17		T30	2656		T32	28
all_pins[12]	transitions[0x0=>0x1]	1104978	1			T29	3		T30	1693		T32	11
all_pins[12]	transitions[0x1=>0x0]	1103285	1			T29	2		T30	1595		T32	6
all_pins[13]	values[0x0]	3027643	1			T28	1		T29	9		T30	4379
all_pins[13]	values[0x1]	1848415	1			T29	16		T30	2552		T32	24
all_pins[13]	transitions[0x0=>0x1]	1104784	1			T29	3		T30	1571		T32	6
all_pins[13]	transitions[0x1=>0x0]	1106319	1			T29	4		T30	1675		T32	10
all_pins[14]	values[0x0]	3024099	1			T28	1		T29	8		T30	4219
all_pins[14]	values[0x1]	1851959	1			T29	17		T30	2712		T32	22
all_pins[14]	transitions[0x0=>0x1]	1110962	1			T29	4		T30	1670		T32	11
all_pins[14]	transitions[0x1=>0x0]	1107418	1			T29	3		T30	1510		T32	13
all_pins[15]	values[0x0]	3028198	1			T28	1		T29	14		T30	4274
all_pins[15]	values[0x1]	1847860	1			T29	11		T30	2657		T32	20
all_pins[15]	transitions[0x0=>0x1]	1104075	1			T29	4		T30	1563		T32	9
all_pins[15]	transitions[0x1=>0x0]	1108174	1			T29	10		T30	1618		T32	11
all_pins[16]	values[0x0]	3032352	1			T28	1		T29	12		T30	4243
all_pins[16]	values[0x1]	1843706	1			T29	13		T30	2688		T32	20
all_pins[16]	transitions[0x0=>0x1]	1105305	1			T29	9		T30	1579		T32	9
all_pins[16]	transitions[0x1=>0x0]	1109459	1			T29	7		T30	1548		T32	9
all_pins[17]	values[0x0]	3029302	1			T28	1		T29	15		T30	4676
all_pins[17]	values[0x1]	1846756	1			T29	10		T30	2255		T32	20
all_pins[17]	transitions[0x0=>0x1]	1104585	1			T29	6		T30	1289		T32	13
all_pins[17]	transitions[0x1=>0x0]	1101535	1			T29	9		T30	1722		T32	13
all_pins[18]	values[0x0]	3027294	1			T28	1		T29	15		T30	4222
all_pins[18]	values[0x1]	1848764	1			T29	10		T30	2709		T32	30
all_pins[18]	transitions[0x0=>0x1]	1105741	1			T29	4		T30	1833		T32	15
all_pins[18]	transitions[0x1=>0x0]	1103733	1			T29	4		T30	1379		T32	5
all_pins[19]	values[0x0]	3023249	1			T28	1		T29	14		T30	4257
all_pins[19]	values[0x1]	1852809	1			T29	11		T30	2674		T32	25
all_pins[19]	transitions[0x0=>0x1]	1107561	1			T29	5		T30	1506		T32	5
all_pins[19]	transitions[0x1=>0x0]	1103516	1			T29	4		T30	1541		T32	10
all_pins[20]	values[0x0]	3032609	1			T28	1		T29	18		T30	4356
all_pins[20]	values[0x1]	1843449	1			T29	7		T30	2575		T32	24
all_pins[20]	transitions[0x0=>0x1]	1105031	1			T29	3		T30	1542		T32	11
all_pins[20]	transitions[0x1=>0x0]	1114391	1			T29	7		T30	1641		T32	12
all_pins[21]	values[0x0]	3025891	1			T28	1		T29	13		T30	4201
all_pins[21]	values[0x1]	1850167	1			T29	12		T30	2730		T32	24
all_pins[21]	transitions[0x0=>0x1]	1107958	1			T29	8		T30	1777		T32	11
all_pins[21]	transitions[0x1=>0x0]	1101240	1			T29	3		T30	1622		T32	11
all_pins[22]	values[0x0]	3029690	1			T28	1		T29	11		T30	4182
all_pins[22]	values[0x1]	1846368	1			T29	14		T30	2749		T32	21
all_pins[22]	transitions[0x0=>0x1]	1107286	1			T29	8		T30	1679		T32	10
all_pins[22]	transitions[0x1=>0x0]	1111085	1			T29	6		T30	1660		T32	13
all_pins[23]	values[0x0]	3030676	1			T28	1		T29	10		T30	4413
all_pins[23]	values[0x1]	1845382	1			T29	15		T30	2518		T32	22
all_pins[23]	transitions[0x0=>0x1]	1105225	1			T29	4		T30	1322		T32	14
all_pins[23]	transitions[0x1=>0x0]	1106211	1			T29	3		T30	1553		T32	13
all_pins[24]	values[0x0]	3025664	1			T28	1		T29	19		T30	4232
all_pins[24]	values[0x1]	1850394	1			T29	6		T30	2699		T32	24
all_pins[24]	transitions[0x0=>0x1]	1108237	1			T29	4		T30	1672		T32	11
all_pins[24]	transitions[0x1=>0x0]	1103225	1			T29	13		T30	1491		T32	9
all_pins[25]	values[0x0]	3031100	1			T28	1		T29	19		T30	4078
all_pins[25]	values[0x1]	1844958	1			T29	6		T30	2853		T32	21
all_pins[25]	transitions[0x0=>0x1]	1103592	1			T29	4		T30	1556		T32	9
all_pins[25]	transitions[0x1=>0x0]	1109028	1			T29	4		T30	1402		T32	12
all_pins[26]	values[0x0]	3027429	1			T28	1		T29	6		T30	4350
all_pins[26]	values[0x1]	1848629	1			T29	19		T30	2581		T32	26
all_pins[26]	transitions[0x0=>0x1]	1109382	1			T29	14		T30	1506		T32	12
all_pins[26]	transitions[0x1=>0x0]	1105711	1			T29	1		T30	1778		T32	7
all_pins[27]	values[0x0]	3026547	1			T28	1		T29	9		T30	4462
all_pins[27]	values[0x1]	1849511	1			T29	16		T30	2469		T32	20
all_pins[27]	transitions[0x0=>0x1]	1107617	1			T29	1		T30	1528		T32	10
all_pins[27]	transitions[0x1=>0x0]	1106735	1			T29	4		T30	1640		T32	16
all_pins[28]	values[0x0]	3025971	1			T28	1		T29	8		T30	4241
all_pins[28]	values[0x1]	1850087	1			T29	17		T30	2690		T32	23
all_pins[28]	transitions[0x0=>0x1]	1107675	1			T29	4		T30	1670		T32	14
all_pins[28]	transitions[0x1=>0x0]	1107099	1			T29	3		T30	1449		T32	11
all_pins[29]	values[0x0]	3024740	1			T28	1		T29	19		T30	4210
all_pins[29]	values[0x1]	1851318	1			T29	6		T30	2721		T32	19
all_pins[29]	transitions[0x0=>0x1]	1106717	1			T29	3		T30	1567		T32	12
all_pins[29]	transitions[0x1=>0x0]	1105486	1			T29	14		T30	1536		T32	16
all_pins[30]	values[0x0]	3029941	1			T28	1		T29	6		T30	4295
all_pins[30]	values[0x1]	1846117	1			T29	19		T30	2636		T32	22
all_pins[30]	transitions[0x0=>0x1]	1103671	1			T29	15		T30	1512		T32	13
all_pins[30]	transitions[0x1=>0x0]	1108872	1			T29	2		T30	1597		T32	10
all_pins[31]	values[0x0]	3036191	1			T28	1		T29	19		T30	4352
all_pins[31]	values[0x1]	1839867	1			T29	6		T30	2579		T32	22
all_pins[31]	transitions[0x0=>0x1]	1100734	1			T29	3		T30	1594		T32	10
all_pins[31]	transitions[0x1=>0x0]	1106984	1			T29	16		T30	1651		T32	10