Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15991623	1			T28	64		T29	10051		T30	24823
all_values[1]	15991623	1			T28	64		T29	10051		T30	24823
all_values[2]	15991623	1			T28	64		T29	10051		T30	24823
all_values[3]	15991623	1			T28	64		T29	10051		T30	24823
all_values[4]	15991623	1			T28	64		T29	10051		T30	24823
all_values[5]	15991623	1			T28	64		T29	10051		T30	24823
all_values[6]	15991623	1			T28	64		T29	10051		T30	24823
all_values[7]	15991623	1			T28	64		T29	10051		T30	24823
all_values[8]	15991623	1			T28	64		T29	10051		T30	24823
all_values[9]	15991623	1			T28	64		T29	10051		T30	24823
all_values[10]	15991623	1			T28	64		T29	10051		T30	24823
all_values[11]	15991623	1			T28	64		T29	10051		T30	24823
all_values[12]	15991623	1			T28	64		T29	10051		T30	24823
all_values[13]	15991623	1			T28	64		T29	10051		T30	24823
all_values[14]	15991623	1			T28	64		T29	10051		T30	24823
all_values[15]	15991623	1			T28	64		T29	10051		T30	24823
all_values[16]	15991623	1			T28	64		T29	10051		T30	24823
all_values[17]	15991623	1			T28	64		T29	10051		T30	24823
all_values[18]	15991623	1			T28	64		T29	10051		T30	24823
all_values[19]	15991623	1			T28	64		T29	10051		T30	24823
all_values[20]	15991623	1			T28	64		T29	10051		T30	24823
all_values[21]	15991623	1			T28	64		T29	10051		T30	24823
all_values[22]	15991623	1			T28	64		T29	10051		T30	24823
all_values[23]	15991623	1			T28	64		T29	10051		T30	24823
all_values[24]	15991623	1			T28	64		T29	10051		T30	24823
all_values[25]	15991623	1			T28	64		T29	10051		T30	24823
all_values[26]	15991623	1			T28	64		T29	10051		T30	24823
all_values[27]	15991623	1			T28	64		T29	10051		T30	24823
all_values[28]	15991623	1			T28	64		T29	10051		T30	24823
all_values[29]	15991623	1			T28	64		T29	10051		T30	24823
all_values[30]	15991623	1			T28	64		T29	10051		T30	24823
all_values[31]	15991623	1			T28	64		T29	10051		T30	24823

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289818738

1

T28

2048

T29

321632

T30

470997

auto[1]

221913198

1

T30

323339

T33

4822

T38

982123

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110265361

1

T28

2048

T29

321632

T30

198277

auto[1]

401466575

1

T30

596059

T33

7958

T38

177990

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

506054808

1

T28

2048

T29

321632

T30

786195

auto[1]

5677128

1

T30

8141

T38

27802

T48

99

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2774041	1			T28	64		T29	10051		T30	5315
all_values[0]	auto[0]	auto[0]	auto[1]	6201054	1			T30	9847		T33	171		T38	27966
all_values[0]	auto[0]	auto[1]	auto[0]	660329	1			T30	809		T33	13		T38	2964
all_values[0]	auto[0]	auto[1]	auto[1]	6178560	1			T30	8590		T33	92		T38	26928
all_values[0]	auto[1]	auto[0]	auto[1]	89355	1			T30	126		T38	441		T48	3
all_values[0]	auto[1]	auto[1]	auto[1]	88284	1			T30	136		T38	437		T39	14
all_values[1]	auto[0]	auto[0]	auto[0]	2784673	1			T28	64		T29	10051		T30	5219
all_values[1]	auto[0]	auto[0]	auto[1]	6208184	1			T30	9596		T33	165		T38	27006
all_values[1]	auto[0]	auto[1]	auto[0]	670063	1			T30	1089		T33	15		T38	2979
all_values[1]	auto[0]	auto[1]	auto[1]	6150491	1			T30	8682		T33	101		T38	28415
all_values[1]	auto[1]	auto[0]	auto[1]	89140	1			T30	119		T38	416		T48	2
all_values[1]	auto[1]	auto[1]	auto[1]	89072	1			T30	118		T38	454		T48	2
all_values[2]	auto[0]	auto[0]	auto[0]	2776358	1			T28	64		T29	10051		T30	5266
all_values[2]	auto[0]	auto[0]	auto[1]	6204271	1			T30	10449		T33	161		T38	27376
all_values[2]	auto[0]	auto[1]	auto[0]	666178	1			T30	983		T33	14		T38	3072
all_values[2]	auto[0]	auto[1]	auto[1]	6167171	1			T30	7867		T33	72		T38	27358
all_values[2]	auto[1]	auto[0]	auto[1]	88856	1			T30	131		T38	375		T48	2
all_values[2]	auto[1]	auto[1]	auto[1]	88789	1			T30	127		T38	512		T48	1
all_values[3]	auto[0]	auto[0]	auto[0]	2781521	1			T28	64		T29	10051		T30	5193
all_values[3]	auto[0]	auto[0]	auto[1]	6199461	1			T30	8480		T33	120		T38	27452
all_values[3]	auto[0]	auto[1]	auto[0]	662341	1			T30	1085		T33	35		T38	3210
all_values[3]	auto[0]	auto[1]	auto[1]	6171180	1			T30	9779		T33	137		T38	27345
all_values[3]	auto[1]	auto[0]	auto[1]	89298	1			T30	146		T38	437		T48	1
all_values[3]	auto[1]	auto[1]	auto[1]	87822	1			T30	140		T38	436		T48	1
all_values[4]	auto[0]	auto[0]	auto[0]	2776545	1			T28	64		T29	10051		T30	5298
all_values[4]	auto[0]	auto[0]	auto[1]	6192485	1			T30	8895		T33	84		T38	29202
all_values[4]	auto[0]	auto[1]	auto[0]	664416	1			T30	828		T33	37		T38	2932
all_values[4]	auto[0]	auto[1]	auto[1]	6180781	1			T30	9558		T33	164		T38	25813
all_values[4]	auto[1]	auto[0]	auto[1]	88884	1			T30	112		T38	391		T48	2
all_values[4]	auto[1]	auto[1]	auto[1]	88512	1			T30	132		T38	435		T39	12
all_values[5]	auto[0]	auto[0]	auto[0]	2787628	1			T28	64		T29	10051		T30	5354
all_values[5]	auto[0]	auto[0]	auto[1]	6190735	1			T30	9448		T33	116		T38	27942
all_values[5]	auto[0]	auto[1]	auto[0]	676859	1			T30	918		T33	36		T38	2781
all_values[5]	auto[0]	auto[1]	auto[1]	6159359	1			T30	8857		T33	112		T38	26824
all_values[5]	auto[1]	auto[0]	auto[1]	88388	1			T30	169		T38	421		T48	2
all_values[5]	auto[1]	auto[1]	auto[1]	88654	1			T30	77		T38	428		T48	2
all_values[6]	auto[0]	auto[0]	auto[0]	2781137	1			T28	64		T29	10051		T30	5317
all_values[6]	auto[0]	auto[0]	auto[1]	6190996	1			T30	9649		T33	65		T38	28427
all_values[6]	auto[0]	auto[1]	auto[0]	667287	1			T30	1038		T33	35		T38	2909
all_values[6]	auto[0]	auto[1]	auto[1]	6174929	1			T30	8549		T33	193		T38	26419
all_values[6]	auto[1]	auto[0]	auto[1]	88981	1			T30	133		T38	441		T48	1
all_values[6]	auto[1]	auto[1]	auto[1]	88293	1			T30	137		T38	444		T48	1
all_values[7]	auto[0]	auto[0]	auto[0]	2776138	1			T28	64		T29	10051		T30	5200
all_values[7]	auto[0]	auto[0]	auto[1]	6231060	1			T30	10048		T33	184		T38	27256
all_values[7]	auto[0]	auto[1]	auto[0]	662502	1			T30	917		T33	5		T38	2908
all_values[7]	auto[0]	auto[1]	auto[1]	6144616	1			T30	8412		T33	79		T38	28084
all_values[7]	auto[1]	auto[0]	auto[1]	88884	1			T30	115		T38	442		T48	3
all_values[7]	auto[1]	auto[1]	auto[1]	88423	1			T30	131		T38	424		T39	20
all_values[8]	auto[0]	auto[0]	auto[0]	2775848	1			T28	64		T29	10051		T30	5212
all_values[8]	auto[0]	auto[0]	auto[1]	6202130	1			T30	9029		T33	192		T38	28559
all_values[8]	auto[0]	auto[1]	auto[0]	660976	1			T30	792		T33	11		T38	3058
all_values[8]	auto[0]	auto[1]	auto[1]	6175385	1			T30	9534		T33	73		T38	26221
all_values[8]	auto[1]	auto[0]	auto[1]	89267	1			T30	153		T38	477		T48	2
all_values[8]	auto[1]	auto[1]	auto[1]	88017	1			T30	103		T38	427		T39	19
all_values[9]	auto[0]	auto[0]	auto[0]	2771222	1			T28	64		T29	10051		T30	5244
all_values[9]	auto[0]	auto[0]	auto[1]	6212408	1			T30	9444		T33	131		T38	27527
all_values[9]	auto[0]	auto[1]	auto[0]	674441	1			T30	929		T33	37		T38	2820
all_values[9]	auto[0]	auto[1]	auto[1]	6156546	1			T30	8956		T33	100		T38	27689
all_values[9]	auto[1]	auto[0]	auto[1]	88638	1			T30	151		T38	448		T48	3
all_values[9]	auto[1]	auto[1]	auto[1]	88368	1			T30	99		T38	435		T48	2
all_values[10]	auto[0]	auto[0]	auto[0]	2785767	1			T28	64		T29	10051		T30	5244
all_values[10]	auto[0]	auto[0]	auto[1]	6183871	1			T30	9235		T33	85		T38	27518
all_values[10]	auto[0]	auto[1]	auto[0]	659468	1			T30	911		T33	22		T38	3213
all_values[10]	auto[0]	auto[1]	auto[1]	6185109	1			T30	9186		T33	164		T38	26956
all_values[10]	auto[1]	auto[0]	auto[1]	89109	1			T30	127		T38	437		T48	1
all_values[10]	auto[1]	auto[1]	auto[1]	88299	1			T30	120		T38	387		T39	24
all_values[11]	auto[0]	auto[0]	auto[0]	2773636	1			T28	64		T29	10051		T30	5246
all_values[11]	auto[0]	auto[0]	auto[1]	6171503	1			T30	9523		T33	170		T38	27440
all_values[11]	auto[0]	auto[1]	auto[0]	673891	1			T30	801		T33	23		T38	3384
all_values[11]	auto[0]	auto[1]	auto[1]	6196028	1			T30	8997		T33	90		T38	27012
all_values[11]	auto[1]	auto[0]	auto[1]	88690	1			T30	141		T38	439		T48	3
all_values[11]	auto[1]	auto[1]	auto[1]	87875	1			T30	115		T38	461		T39	13
all_values[12]	auto[0]	auto[0]	auto[0]	2780957	1			T28	64		T29	10051		T30	5268
all_values[12]	auto[0]	auto[0]	auto[1]	6174681	1			T30	9551		T33	154		T38	28222
all_values[12]	auto[0]	auto[1]	auto[0]	673432	1			T30	909		T33	6		T38	3015
all_values[12]	auto[0]	auto[1]	auto[1]	6185200	1			T30	8856		T33	110		T38	26445
all_values[12]	auto[1]	auto[0]	auto[1]	88729	1			T30	94		T38	431		T48	1
all_values[12]	auto[1]	auto[1]	auto[1]	88624	1			T30	145		T38	457		T39	12
all_values[13]	auto[0]	auto[0]	auto[0]	2785345	1			T28	64		T29	10051		T30	5120
all_values[13]	auto[0]	auto[0]	auto[1]	6189552	1			T30	9590		T33	105		T38	26586
all_values[13]	auto[0]	auto[1]	auto[0]	667066	1			T30	1062		T33	30		T38	3491
all_values[13]	auto[0]	auto[1]	auto[1]	6171902	1			T30	8786		T33	135		T38	27861
all_values[13]	auto[1]	auto[0]	auto[1]	88986	1			T30	145		T38	419		T48	1
all_values[13]	auto[1]	auto[1]	auto[1]	88772	1			T30	120		T38	450		T48	2
all_values[14]	auto[0]	auto[0]	auto[0]	2773598	1			T28	64		T29	10051		T30	5299
all_values[14]	auto[0]	auto[0]	auto[1]	6142755	1			T30	8965		T33	117		T38	27271
all_values[14]	auto[0]	auto[1]	auto[0]	669612	1			T30	971		T33	18		T38	3101
all_values[14]	auto[0]	auto[1]	auto[1]	6228101	1			T30	9355		T33	157		T38	27711
all_values[14]	auto[1]	auto[0]	auto[1]	89100	1			T30	109		T38	406		T48	3
all_values[14]	auto[1]	auto[1]	auto[1]	88457	1			T30	124		T38	455		T39	22
all_values[15]	auto[0]	auto[0]	auto[0]	2773861	1			T28	64		T29	10051		T30	5214
all_values[15]	auto[0]	auto[0]	auto[1]	6196248	1			T30	8738		T33	139		T38	28228
all_values[15]	auto[0]	auto[1]	auto[0]	668924	1			T30	959		T33	24		T38	3320
all_values[15]	auto[0]	auto[1]	auto[1]	6175038	1			T30	9660		T33	120		T38	26324
all_values[15]	auto[1]	auto[0]	auto[1]	89323	1			T30	126		T38	432		T48	2
all_values[15]	auto[1]	auto[1]	auto[1]	88229	1			T30	126		T38	431		T48	2
all_values[16]	auto[0]	auto[0]	auto[0]	2786687	1			T28	64		T29	10051		T30	5336
all_values[16]	auto[0]	auto[0]	auto[1]	6238466	1			T30	9548		T33	100		T38	27395
all_values[16]	auto[0]	auto[1]	auto[0]	670220	1			T30	886		T33	43		T38	2965
all_values[16]	auto[0]	auto[1]	auto[1]	6119142	1			T30	8782		T33	146		T38	27218
all_values[16]	auto[1]	auto[0]	auto[1]	88720	1			T30	128		T38	423		T48	3
all_values[16]	auto[1]	auto[1]	auto[1]	88388	1			T30	143		T38	448		T48	1
all_values[17]	auto[0]	auto[0]	auto[0]	2771157	1			T28	64		T29	10051		T30	5611
all_values[17]	auto[0]	auto[0]	auto[1]	6192612	1			T30	9707		T33	102		T38	27757
all_values[17]	auto[0]	auto[1]	auto[0]	665420	1			T30	861		T33	20		T38	3096
all_values[17]	auto[0]	auto[1]	auto[1]	6184930	1			T30	8388		T33	152		T38	27155
all_values[17]	auto[1]	auto[0]	auto[1]	89307	1			T30	126		T38	461		T48	2
all_values[17]	auto[1]	auto[1]	auto[1]	88197	1			T30	130		T38	388		T48	1
all_values[18]	auto[0]	auto[0]	auto[0]	2783793	1			T28	64		T29	10051		T30	5012
all_values[18]	auto[0]	auto[0]	auto[1]	6242691	1			T30	9282		T33	121		T38	26666
all_values[18]	auto[0]	auto[1]	auto[0]	670348	1			T30	1068		T33	26		T38	3169
all_values[18]	auto[0]	auto[1]	auto[1]	6117752	1			T30	9218		T33	117		T38	28122
all_values[18]	auto[1]	auto[0]	auto[1]	88595	1			T30	109		T38	414		T48	2
all_values[18]	auto[1]	auto[1]	auto[1]	88444	1			T30	134		T38	426		T48	2
all_values[19]	auto[0]	auto[0]	auto[0]	2778501	1			T28	64		T29	10051		T30	5250
all_values[19]	auto[0]	auto[0]	auto[1]	6143716	1			T30	9331		T33	92		T38	28003
all_values[19]	auto[0]	auto[1]	auto[0]	658341	1			T30	957		T33	73		T38	3135
all_values[19]	auto[0]	auto[1]	auto[1]	6233668	1			T30	9012		T33	113		T38	26279
all_values[19]	auto[1]	auto[0]	auto[1]	88893	1			T30	136		T38	429		T48	3
all_values[19]	auto[1]	auto[1]	auto[1]	88504	1			T30	137		T38	453		T39	6
all_values[20]	auto[0]	auto[0]	auto[0]	2780919	1			T28	64		T29	10051		T30	5158
all_values[20]	auto[0]	auto[0]	auto[1]	6200039	1			T30	9684		T33	134		T38	27257
all_values[20]	auto[0]	auto[1]	auto[0]	668967	1			T30	623		T33	36		T38	3295
all_values[20]	auto[0]	auto[1]	auto[1]	6164397	1			T30	9108		T33	107		T38	27086
all_values[20]	auto[1]	auto[0]	auto[1]	89305	1			T30	120		T38	443		T48	3
all_values[20]	auto[1]	auto[1]	auto[1]	87996	1			T30	130		T38	441		T48	1
all_values[21]	auto[0]	auto[0]	auto[0]	2779406	1			T28	64		T29	10051		T30	5134
all_values[21]	auto[0]	auto[0]	auto[1]	6171458	1			T30	9076		T33	154		T38	29014
all_values[21]	auto[0]	auto[1]	auto[0]	671740	1			T30	881		T33	34		T38	2784
all_values[21]	auto[0]	auto[1]	auto[1]	6191610	1			T30	9483		T33	88		T38	26236
all_values[21]	auto[1]	auto[0]	auto[1]	88372	1			T30	123		T38	427		T48	2
all_values[21]	auto[1]	auto[1]	auto[1]	89037	1			T30	126		T38	438		T48	2
all_values[22]	auto[0]	auto[0]	auto[0]	2786076	1			T28	64		T29	10051		T30	5277
all_values[22]	auto[0]	auto[0]	auto[1]	6182876	1			T30	8567		T33	92		T38	27771
all_values[22]	auto[0]	auto[1]	auto[0]	658380	1			T30	973		T33	22		T38	3065
all_values[22]	auto[0]	auto[1]	auto[1]	6186643	1			T30	9754		T33	173		T38	26873
all_values[22]	auto[1]	auto[0]	auto[1]	88984	1			T30	128		T38	465		T48	4
all_values[22]	auto[1]	auto[1]	auto[1]	88664	1			T30	124		T38	413		T39	19
all_values[23]	auto[0]	auto[0]	auto[0]	2786486	1			T28	64		T29	10051		T30	5247
all_values[23]	auto[0]	auto[0]	auto[1]	6175170	1			T30	8875		T33	138		T38	27287
all_values[23]	auto[0]	auto[1]	auto[0]	661075	1			T30	1134		T33	20		T38	2800
all_values[23]	auto[0]	auto[1]	auto[1]	6190953	1			T30	9307		T33	118		T38	27753
all_values[23]	auto[1]	auto[0]	auto[1]	89705	1			T30	135		T38	455		T48	3
all_values[23]	auto[1]	auto[1]	auto[1]	88234	1			T30	125		T38	424		T39	20
all_values[24]	auto[0]	auto[0]	auto[0]	2778307	1			T28	64		T29	10051		T30	5258
all_values[24]	auto[0]	auto[0]	auto[1]	6175094	1			T30	9024		T33	122		T38	26810
all_values[24]	auto[0]	auto[1]	auto[0]	664882	1			T30	947		T33	19		T38	3095
all_values[24]	auto[0]	auto[1]	auto[1]	6195387	1			T30	9328		T33	121		T38	27799
all_values[24]	auto[1]	auto[0]	auto[1]	89165	1			T30	145		T38	480		T48	2
all_values[24]	auto[1]	auto[1]	auto[1]	88788	1			T30	121		T38	437		T39	21
all_values[25]	auto[0]	auto[0]	auto[0]	2772523	1			T28	64		T29	10051		T30	5189
all_values[25]	auto[0]	auto[0]	auto[1]	6199288	1			T30	9014		T33	155		T38	26733
all_values[25]	auto[0]	auto[1]	auto[0]	655355	1			T30	776		T33	19		T38	3345
all_values[25]	auto[0]	auto[1]	auto[1]	6186916	1			T30	9604		T33	110		T38	27592
all_values[25]	auto[1]	auto[0]	auto[1]	89220	1			T30	131		T38	419		T48	4
all_values[25]	auto[1]	auto[1]	auto[1]	88321	1			T30	109		T38	411		T48	1
all_values[26]	auto[0]	auto[0]	auto[0]	2770607	1			T28	64		T29	10051		T30	5277
all_values[26]	auto[0]	auto[0]	auto[1]	6183101	1			T30	8659		T33	160		T38	26971
all_values[26]	auto[0]	auto[1]	auto[0]	670951	1			T30	1082		T33	19		T38	3141
all_values[26]	auto[0]	auto[1]	auto[1]	6189983	1			T30	9565		T33	92		T38	27725
all_values[26]	auto[1]	auto[0]	auto[1]	88564	1			T30	119		T38	405		T48	3
all_values[26]	auto[1]	auto[1]	auto[1]	88417	1			T30	121		T38	437		T48	1
all_values[27]	auto[0]	auto[0]	auto[0]	2773566	1			T28	64		T29	10051		T30	5485
all_values[27]	auto[0]	auto[0]	auto[1]	6157619	1			T30	9675		T33	89		T38	27276
all_values[27]	auto[0]	auto[1]	auto[0]	670072	1			T30	851		T33	24		T38	3304
all_values[27]	auto[0]	auto[1]	auto[1]	6212881	1			T30	8549		T33	188		T38	27254
all_values[27]	auto[1]	auto[0]	auto[1]	88481	1			T30	139		T38	446		T48	1
all_values[27]	auto[1]	auto[1]	auto[1]	89004	1			T30	124		T38	426		T39	15
all_values[28]	auto[0]	auto[0]	auto[0]	2779397	1			T28	64		T29	10051		T30	5173
all_values[28]	auto[0]	auto[0]	auto[1]	6152241	1			T30	9729		T33	94		T38	28600
all_values[28]	auto[0]	auto[1]	auto[0]	662866	1			T30	895		T33	50		T38	2938
all_values[28]	auto[0]	auto[1]	auto[1]	6219908	1			T30	8751		T33	108		T38	26458
all_values[28]	auto[1]	auto[0]	auto[1]	88783	1			T30	147		T38	431		T48	2
all_values[28]	auto[1]	auto[1]	auto[1]	88428	1			T30	128		T38	432		T48	1
all_values[29]	auto[0]	auto[0]	auto[0]	2782228	1			T28	64		T29	10051		T30	5174
all_values[29]	auto[0]	auto[0]	auto[1]	6187835	1			T30	9311		T33	78		T38	26826
all_values[29]	auto[0]	auto[1]	auto[0]	671480	1			T30	830		T33	57		T38	3356
all_values[29]	auto[0]	auto[1]	auto[1]	6172510	1			T30	9263		T33	118		T38	27510
all_values[29]	auto[1]	auto[0]	auto[1]	88175	1			T30	107		T38	416		T48	2
all_values[29]	auto[1]	auto[1]	auto[1]	89395	1			T30	138		T38	438		T39	15
all_values[30]	auto[0]	auto[0]	auto[0]	2779453	1			T28	64		T29	10051		T30	5510
all_values[30]	auto[0]	auto[0]	auto[1]	6158234	1			T30	9387		T33	100		T38	27198
all_values[30]	auto[0]	auto[1]	auto[0]	673853	1			T30	1055		T33	47		T38	3144
all_values[30]	auto[0]	auto[1]	auto[1]	6202583	1			T30	8612		T33	152		T38	27090
all_values[30]	auto[1]	auto[0]	auto[1]	89043	1			T30	141		T38	437		T48	3
all_values[30]	auto[1]	auto[1]	auto[1]	88457	1			T30	118		T38	474		T48	1
all_values[31]	auto[0]	auto[0]	auto[0]	2778570	1			T28	64		T29	10051		T30	5389
all_values[31]	auto[0]	auto[0]	auto[1]	6194672	1			T30	8993		T33	138		T38	27282
all_values[31]	auto[0]	auto[1]	auto[0]	667675	1			T30	968		T33	22		T38	3093
all_values[31]	auto[0]	auto[1]	auto[1]	6173282	1			T30	9221		T33	128		T38	27726
all_values[31]	auto[1]	auto[0]	auto[1]	89341	1			T30	128		T38	438		T48	4
all_values[31]	auto[1]	auto[1]	auto[1]	88083	1			T30	124		T38	401		T39	14

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal