Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[1]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[2]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[3]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[4]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[5]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[6]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[7]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[8]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[9]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[10]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[11]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[12]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[13]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[14]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[15]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[16]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[17]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[18]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[19]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[20]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[21]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[22]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[23]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[24]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[25]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[26]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[27]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[28]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[29]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[30]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[31]	15737021	1			T28	119		T29	10051		T30	25314

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300345319

1

T28

2999

T29

160349

T30

284950

auto[1]

203239353

1

T28

809

T29

161283

T30

525098

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

402692011

1

T28

3419

T29

321632

T30

643070

auto[1]

100892661

1

T28

389

T30

166978

T31

9956

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

373092480

1

T28

2466

T29

321632

T30

590865

auto[1]

130492192

1

T28

1342

T30

219183

T31

10123

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5797742	1			T28	74		T29	4937		T30	5851
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4271283	1			T28	17		T29	5114		T30	9979
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1590068	1			T28	13		T30	2639		T31	132
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1997017	1			T28	8		T30	278		T31	170
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	508143	1			T28	1		T30	3950		T34	201
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1572768	1			T28	6		T30	2617		T31	201
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5801110	1			T28	94		T29	4888		T30	6041
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4281234	1			T28	16		T29	5163		T30	9943
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1583243	1			T28	4		T30	2704		T31	183
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1991428	1			T28	5		T30	319		T31	142
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	509765	1			T30	3774		T34	166		T36	9
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1570241	1			T30	2533		T31	150		T34	197
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5805090	1			T28	64		T29	5241		T30	5982
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4271271	1			T28	14		T29	4810		T30	9850
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1588303	1			T28	2		T30	2607		T31	130
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1991850	1			T28	29		T30	307		T31	189
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	508917	1			T28	7		T30	3937		T34	209
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1571590	1			T28	3		T30	2631		T31	154
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5798310	1			T28	82		T29	5451		T30	5940
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4273533	1			T28	21		T29	4600		T30	10061
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1594153	1			T28	14		T30	2577		T31	146
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1993197	1			T30	297		T31	138		T36	49
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	510484	1			T30	3883		T34	218		T36	7
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1567344	1			T28	2		T30	2556		T31	170
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5794205	1			T28	42		T29	4472		T30	6072
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4275168	1			T28	16		T29	5579		T30	9847
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1587852	1			T28	8		T30	2678		T31	174
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1993723	1			T28	35		T30	271		T31	150
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	509096	1			T28	12		T30	3921		T34	182
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1576977	1			T28	6		T30	2525		T31	174
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5802254	1			T28	73		T29	5526		T30	5949
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4275064	1			T28	24		T29	4525		T30	9745
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1581055	1			T28	5		T30	2568		T31	153
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2000531	1			T28	16		T30	353		T31	132
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	512051	1			T28	1		T30	4000		T34	214
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1566066	1			T30	2699		T31	164		T34	220
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5805532	1			T28	54		T29	5468		T30	6090
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4269107	1			T28	13		T29	4583		T30	10134
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1587771	1			T28	4		T30	2568		T31	148
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1991913	1			T28	42		T30	290		T31	211
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	510152	1			T28	6		T30	3770		T34	197
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1572546	1			T30	2462		T31	124		T34	205
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5808556	1			T28	50		T29	4849		T30	6092
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4258776	1			T28	15		T29	5202		T30	9729
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1585707	1			T28	12		T30	2679		T31	166
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1998133	1			T28	29		T30	287		T31	166
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	512613	1			T28	9		T30	3867		T34	161
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1573236	1			T28	4		T30	2660		T31	142
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5781937	1			T28	31		T29	4693		T30	6089
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4282149	1			T28	8		T29	5358		T30	9854
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1592897	1			T28	6		T30	2665		T31	195
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1997182	1			T28	52		T30	258		T31	142
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	508297	1			T28	12		T30	3861		T34	179
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1574559	1			T28	10		T30	2587		T31	162
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5803765	1			T28	54		T29	3888		T30	5947
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4268664	1			T28	13		T29	6163		T30	9908
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1585926	1			T28	7		T30	2713		T31	141
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1996582	1			T28	32		T30	275		T31	164
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	511738	1			T28	1		T30	3905		T34	199
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1570346	1			T28	12		T30	2566		T31	136
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5810043	1			T28	77		T29	5056		T30	6009
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4266157	1			T28	18		T29	4995		T30	9857
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1581942	1			T28	7		T30	2613		T31	190
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1994700	1			T28	17		T30	284		T31	154
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	511279	1			T30	3864		T34	172		T36	8
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1572900	1			T30	2687		T31	166		T34	234
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5782376	1			T28	82		T29	5364		T30	5999
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4278696	1			T28	12		T29	4687		T30	9571
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1585691	1			T28	9		T30	2593		T31	169
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2003603	1			T28	16		T30	285		T31	132
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	511680	1			T30	4209		T34	194		T36	9
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1574975	1			T30	2657		T31	140		T34	202
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5799716	1			T28	24		T29	4853		T30	5950
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4263973	1			T28	9		T29	5198		T30	9720
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1588887	1			T28	4		T30	2675		T31	157
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2002714	1			T28	54		T30	287		T31	196
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	511062	1			T28	14		T30	4011		T34	186
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1570669	1			T28	14		T30	2671		T31	120
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5803960	1			T28	51		T29	4514		T30	5917
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4272130	1			T28	21		T29	5537		T30	9506
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1587721	1			T28	3		T30	2512		T31	166
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1988260	1			T28	32		T30	353		T31	157
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	510000	1			T28	6		T30	4485		T34	210
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1574950	1			T28	6		T30	2541		T31	130
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5819817	1			T28	17		T29	5271		T30	6013
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4260491	1			T28	10		T29	4780		T30	9964
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1585960	1			T30	2663		T31	132		T34	144
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1992248	1			T28	71		T30	315		T31	174
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	509354	1			T28	15		T30	3772		T34	272
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1569151	1			T28	6		T30	2587		T31	165
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5809735	1			T28	45		T29	4357		T30	6031
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4261654	1			T28	18		T29	5694		T30	9779
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1584828	1			T28	2		T30	2590		T31	187
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1995502	1			T28	36		T30	299		T31	134
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	511138	1			T28	6		T30	3766		T34	234
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1574164	1			T28	12		T30	2849		T31	162
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5818899	1			T28	39		T29	5263		T30	5987
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4267718	1			T28	11		T29	4788		T30	9514
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1585483	1			T28	3		T30	2624		T31	102
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1993738	1			T28	53		T30	335		T31	178
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	507775	1			T28	11		T30	4256		T34	204
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1563408	1			T28	2		T30	2598		T31	154
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5803260	1			T28	49		T29	5245		T30	5997
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4277489	1			T28	16		T29	4806		T30	9709
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1579623	1			T28	8		T30	2534		T31	158
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2000396	1			T28	26		T30	346		T31	177
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	510437	1			T28	9		T30	4015		T34	194
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1565816	1			T28	11		T30	2713		T31	114
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5807525	1			T28	67		T29	6088		T30	5996
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4261470	1			T28	16		T29	3963		T30	9544
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1579787	1			T28	7		T30	2536		T31	196
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2004461	1			T28	25		T30	371		T31	148
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	513739	1			T28	4		T30	4094		T34	209
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1570039	1			T30	2773		T31	156		T34	185
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5807542	1			T28	75		T29	4918		T30	5996
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4275793	1			T28	18		T29	5133		T30	9992
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1579985	1			T28	20		T30	2743		T31	149
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1997348	1			T28	6		T30	278		T31	152
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	509485	1			T30	3711		T34	165		T36	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1566868	1			T30	2594		T31	168		T34	193
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5813040	1			T28	40		T29	4383		T30	6036
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4264595	1			T28	17		T29	5668		T30	9774
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1580539	1			T28	2		T30	2491		T31	139
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2003177	1			T28	54		T30	293		T31	174
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	512196	1			T28	6		T30	3961		T34	231
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1563474	1			T30	2759		T31	166		T34	199
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5804755	1			T28	44		T29	5054		T30	5999
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4272313	1			T28	16		T29	4997		T30	9939
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1583746	1			T28	5		T30	2619		T31	156
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1998297	1			T28	39		T30	275		T31	163
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	511545	1			T28	11		T30	3888		T34	203
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1566365	1			T28	4		T30	2594		T31	136
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5811225	1			T28	41		T29	4546		T30	6049
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4270815	1			T28	11		T29	5505		T30	9910
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1583243	1			T28	8		T30	2412		T31	154
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1996079	1			T28	47		T30	286		T31	150
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	509367	1			T28	6		T30	4085		T34	175
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1566292	1			T28	6		T30	2572		T31	190
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5795980	1			T28	34		T29	4977		T30	5910
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4275137	1			T28	4		T29	5074		T30	9885
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1580730	1			T28	10		T30	2510		T31	141
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2004486	1			T28	50		T30	320		T31	168
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	513761	1			T28	10		T30	4191		T34	165
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1566927	1			T28	11		T30	2498		T31	168
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5808278	1			T28	53		T29	5480		T30	5945
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4269957	1			T28	10		T29	4571		T30	9785
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1581444	1			T28	8		T30	2490		T31	153
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2004707	1			T28	37		T30	318		T31	172
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	507750	1			T28	3		T30	4109		T34	216
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1564885	1			T28	8		T30	2667		T31	164
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5802590	1			T28	38		T29	5236		T30	5971
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4270545	1			T28	11		T29	4815		T30	9865
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1578458	1			T30	2633		T31	146		T34	198
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2000712	1			T28	61		T30	246		T31	160
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	512631	1			T28	7		T30	3968		T34	186
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1572085	1			T28	2		T30	2631		T31	151
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5800696	1			T28	53		T29	4956		T30	5852
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4279732	1			T28	11		T29	5095		T30	10291
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1581637	1			T28	20		T30	2646		T31	146
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2002760	1			T28	21		T30	263		T31	213
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	509677	1			T28	9		T30	3830		T34	181
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1562519	1			T28	5		T30	2432		T31	130
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5800555	1			T28	52		T29	5292		T30	6007
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4277995	1			T28	24		T29	4759		T30	9958
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1578909	1			T28	12		T30	2646		T31	158
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2000295	1			T28	20		T30	293		T31	137
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	512156	1			T28	3		T30	3918		T34	198
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1567111	1			T28	8		T30	2492		T31	182
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5802591	1			T28	80		T29	5209		T30	6010
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4272770	1			T28	11		T29	4842		T30	9848
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1576624	1			T28	5		T30	2700		T31	174
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2006900	1			T28	19		T30	294		T31	174
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	511311	1			T30	4121		T34	203		T36	9
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1566825	1			T28	4		T30	2341		T31	130
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5807383	1			T28	73		T29	5042		T30	6000
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4275669	1			T28	22		T29	5009		T30	10084
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1582483	1			T28	12		T30	2764		T31	162
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1999227	1			T28	9		T30	282		T31	136
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	509131	1			T28	3		T30	3685		T34	237
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1563128	1			T30	2499		T31	175		T34	185
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5815228	1			T28	59		T29	5035		T30	5977
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4268966	1			T28	10		T29	5016		T30	9900
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1578899	1			T28	8		T30	2524		T31	132
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1995712	1			T28	27		T30	255		T31	150
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	511423	1			T28	7		T30	3943		T34	219
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1566793	1			T28	8		T30	2715		T31	181
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5796352	1			T28	55		T29	4797		T30	6028
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4280070	1			T28	14		T29	5254		T30	9940
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1578455	1			T28	5		T30	2832		T31	164
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2006345	1			T28	32		T30	257		T31	163
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	510204	1			T28	7		T30	3733		T34	222
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1565595	1			T28	6		T30	2524		T31	132

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal