Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[1]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[2]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[3]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[4]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[5]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[6]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[7]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[8]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[9]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[10]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[11]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[12]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[13]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[14]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[15]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[16]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[17]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[18]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[19]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[20]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[21]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[22]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[23]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[24]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[25]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[26]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[27]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[28]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[29]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[30]	15737021	1			T28	119		T29	10051		T30	25314
bins_for_gpio_bits[31]	15737021	1			T28	119		T29	10051		T30	25314

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300345319

1

T28

2999

T29

160349

T30

284950

auto[1]

203239353

1

T28

809

T29

161283

T30

525098

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300340056

1

T28

2999

T29

160349

T30

285001

auto[1]

203244616

1

T28

809

T29

161283

T30

525047

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9102168	1			T28	94		T29	4937		T30	8265
bins_for_gpio_bits[0]	auto[0]	auto[1]	282478	1			T28	1		T30	504		T31	49
bins_for_gpio_bits[0]	auto[1]	auto[0]	282659	1			T28	1		T30	503		T31	50
bins_for_gpio_bits[0]	auto[1]	auto[1]	6069716	1			T28	23		T29	5114		T30	16042
bins_for_gpio_bits[1]	auto[0]	auto[0]	9094488	1			T28	103		T29	4888		T30	8578
bins_for_gpio_bits[1]	auto[0]	auto[1]	281126	1			T30	489		T31	36		T34	45
bins_for_gpio_bits[1]	auto[1]	auto[0]	281293	1			T30	486		T31	36		T34	44
bins_for_gpio_bits[1]	auto[1]	auto[1]	6080114	1			T28	16		T29	5163		T30	15761
bins_for_gpio_bits[2]	auto[0]	auto[0]	9103393	1			T28	94		T29	5241		T30	8427
bins_for_gpio_bits[2]	auto[0]	auto[1]	281715	1			T28	1		T30	471		T31	34
bins_for_gpio_bits[2]	auto[1]	auto[0]	281850	1			T28	1		T30	469		T31	34
bins_for_gpio_bits[2]	auto[1]	auto[1]	6070063	1			T28	23		T29	4810		T30	15947
bins_for_gpio_bits[3]	auto[0]	auto[0]	9103595	1			T28	95		T29	5451		T30	8325
bins_for_gpio_bits[3]	auto[0]	auto[1]	281871	1			T28	1		T30	491		T31	40
bins_for_gpio_bits[3]	auto[1]	auto[0]	282065	1			T28	1		T30	489		T31	40
bins_for_gpio_bits[3]	auto[1]	auto[1]	6069490	1			T28	22		T29	4600		T30	16009
bins_for_gpio_bits[4]	auto[0]	auto[0]	9092968	1			T28	84		T29	4472		T30	8514
bins_for_gpio_bits[4]	auto[0]	auto[1]	282678	1			T28	1		T30	507		T31	42
bins_for_gpio_bits[4]	auto[1]	auto[0]	282812	1			T28	1		T30	507		T31	42
bins_for_gpio_bits[4]	auto[1]	auto[1]	6078563	1			T28	33		T29	5579		T30	15786
bins_for_gpio_bits[5]	auto[0]	auto[0]	9102417	1			T28	94		T29	5526		T30	8386
bins_for_gpio_bits[5]	auto[0]	auto[1]	281244	1			T30	486		T31	40		T34	46
bins_for_gpio_bits[5]	auto[1]	auto[0]	281423	1			T30	484		T31	40		T34	46
bins_for_gpio_bits[5]	auto[1]	auto[1]	6071937	1			T28	25		T29	4525		T30	15958
bins_for_gpio_bits[6]	auto[0]	auto[0]	9103326	1			T28	100		T29	5468		T30	8454
bins_for_gpio_bits[6]	auto[0]	auto[1]	281695	1			T30	494		T31	33		T34	51
bins_for_gpio_bits[6]	auto[1]	auto[0]	281890	1			T30	494		T31	33		T34	51
bins_for_gpio_bits[6]	auto[1]	auto[1]	6070110	1			T28	19		T29	4583		T30	15872
bins_for_gpio_bits[7]	auto[0]	auto[0]	9110147	1			T28	90		T29	4849		T30	8571
bins_for_gpio_bits[7]	auto[0]	auto[1]	282071	1			T28	1		T30	488		T31	40
bins_for_gpio_bits[7]	auto[1]	auto[0]	282249	1			T28	1		T30	487		T31	40
bins_for_gpio_bits[7]	auto[1]	auto[1]	6062554	1			T28	27		T29	5202		T30	15768
bins_for_gpio_bits[8]	auto[0]	auto[0]	9088472	1			T28	86		T29	4693		T30	8525
bins_for_gpio_bits[8]	auto[0]	auto[1]	283375	1			T28	3		T30	489		T31	38
bins_for_gpio_bits[8]	auto[1]	auto[0]	283544	1			T28	3		T30	487		T31	38
bins_for_gpio_bits[8]	auto[1]	auto[1]	6081630	1			T28	27		T29	5358		T30	15813
bins_for_gpio_bits[9]	auto[0]	auto[0]	9104293	1			T28	90		T29	3888		T30	8439
bins_for_gpio_bits[9]	auto[0]	auto[1]	281791	1			T28	3		T30	498		T31	36
bins_for_gpio_bits[9]	auto[1]	auto[0]	281980	1			T28	3		T30	496		T31	36
bins_for_gpio_bits[9]	auto[1]	auto[1]	6068957	1			T28	23		T29	6163		T30	15881
bins_for_gpio_bits[10]	auto[0]	auto[0]	9104940	1			T28	101		T29	5056		T30	8417
bins_for_gpio_bits[10]	auto[0]	auto[1]	281580	1			T30	491		T31	44		T34	49
bins_for_gpio_bits[10]	auto[1]	auto[0]	281745	1			T30	489		T31	44		T34	49
bins_for_gpio_bits[10]	auto[1]	auto[1]	6068756	1			T28	18		T29	4995		T30	15917
bins_for_gpio_bits[11]	auto[0]	auto[0]	9088905	1			T28	107		T29	5364		T30	8398
bins_for_gpio_bits[11]	auto[0]	auto[1]	282613	1			T30	482		T31	35		T34	42
bins_for_gpio_bits[11]	auto[1]	auto[0]	282765	1			T30	479		T31	35		T34	42
bins_for_gpio_bits[11]	auto[1]	auto[1]	6082738	1			T28	12		T29	4687		T30	15955
bins_for_gpio_bits[12]	auto[0]	auto[0]	9108569	1			T28	78		T29	4853		T30	8431
bins_for_gpio_bits[12]	auto[0]	auto[1]	282587	1			T28	4		T30	482		T31	35
bins_for_gpio_bits[12]	auto[1]	auto[0]	282748	1			T28	4		T30	481		T31	35
bins_for_gpio_bits[12]	auto[1]	auto[1]	6063117	1			T28	33		T29	5198		T30	15920
bins_for_gpio_bits[13]	auto[0]	auto[0]	9097687	1			T28	84		T29	4514		T30	8316
bins_for_gpio_bits[13]	auto[0]	auto[1]	282097	1			T28	2		T30	466		T31	33
bins_for_gpio_bits[13]	auto[1]	auto[0]	282254	1			T28	2		T30	466		T31	33
bins_for_gpio_bits[13]	auto[1]	auto[1]	6074983	1			T28	31		T29	5537		T30	16066
bins_for_gpio_bits[14]	auto[0]	auto[0]	9115555	1			T28	85		T29	5271		T30	8497
bins_for_gpio_bits[14]	auto[0]	auto[1]	282309	1			T28	3		T30	496		T31	34
bins_for_gpio_bits[14]	auto[1]	auto[0]	282470	1			T28	3		T30	494		T31	35
bins_for_gpio_bits[14]	auto[1]	auto[1]	6056687	1			T28	28		T29	4780		T30	15827
bins_for_gpio_bits[15]	auto[0]	auto[0]	9108127	1			T28	81		T29	4357		T30	8435
bins_for_gpio_bits[15]	auto[0]	auto[1]	281748	1			T28	2		T30	486		T31	41
bins_for_gpio_bits[15]	auto[1]	auto[0]	281938	1			T28	2		T30	485		T31	41
bins_for_gpio_bits[15]	auto[1]	auto[1]	6065208	1			T28	34		T29	5694		T30	15908
bins_for_gpio_bits[16]	auto[0]	auto[0]	9115857	1			T28	94		T29	5263		T30	8454
bins_for_gpio_bits[16]	auto[0]	auto[1]	282135	1			T28	1		T30	492		T31	41
bins_for_gpio_bits[16]	auto[1]	auto[0]	282263	1			T28	1		T30	492		T31	41
bins_for_gpio_bits[16]	auto[1]	auto[1]	6056766	1			T28	23		T29	4788		T30	15876
bins_for_gpio_bits[17]	auto[0]	auto[0]	9101010	1			T28	79		T29	5245		T30	8385
bins_for_gpio_bits[17]	auto[0]	auto[1]	282109	1			T28	4		T30	493		T31	33
bins_for_gpio_bits[17]	auto[1]	auto[0]	282269	1			T28	4		T30	492		T31	33
bins_for_gpio_bits[17]	auto[1]	auto[1]	6071633	1			T28	32		T29	4806		T30	15944
bins_for_gpio_bits[18]	auto[0]	auto[0]	9109368	1			T28	99		T29	6088		T30	8420
bins_for_gpio_bits[18]	auto[0]	auto[1]	282234	1			T30	484		T31	34		T34	51
bins_for_gpio_bits[18]	auto[1]	auto[0]	282405	1			T30	483		T31	34		T34	51
bins_for_gpio_bits[18]	auto[1]	auto[1]	6063014	1			T28	20		T29	3963		T30	15927
bins_for_gpio_bits[19]	auto[0]	auto[0]	9102342	1			T28	101		T29	4918		T30	8505
bins_for_gpio_bits[19]	auto[0]	auto[1]	282363	1			T30	513		T31	40		T34	52
bins_for_gpio_bits[19]	auto[1]	auto[0]	282533	1			T30	512		T31	40		T34	52
bins_for_gpio_bits[19]	auto[1]	auto[1]	6069783	1			T28	18		T29	5133		T30	15784
bins_for_gpio_bits[20]	auto[0]	auto[0]	9114903	1			T28	96		T29	4383		T30	8336
bins_for_gpio_bits[20]	auto[0]	auto[1]	281726	1			T30	487		T31	40		T34	49
bins_for_gpio_bits[20]	auto[1]	auto[0]	281853	1			T30	484		T31	40		T34	49
bins_for_gpio_bits[20]	auto[1]	auto[1]	6058539	1			T28	23		T29	5668		T30	16007
bins_for_gpio_bits[21]	auto[0]	auto[0]	9103662	1			T28	86		T29	5054		T30	8414
bins_for_gpio_bits[21]	auto[0]	auto[1]	282980	1			T28	2		T30	481		T31	34
bins_for_gpio_bits[21]	auto[1]	auto[0]	283136	1			T28	2		T30	479		T31	34
bins_for_gpio_bits[21]	auto[1]	auto[1]	6067243	1			T28	29		T29	4997		T30	15940
bins_for_gpio_bits[22]	auto[0]	auto[0]	9108262	1			T28	95		T29	4546		T30	8277
bins_for_gpio_bits[22]	auto[0]	auto[1]	282108	1			T28	1		T30	471		T31	40
bins_for_gpio_bits[22]	auto[1]	auto[0]	282285	1			T28	1		T30	470		T31	40
bins_for_gpio_bits[22]	auto[1]	auto[1]	6064366	1			T28	22		T29	5505		T30	16096
bins_for_gpio_bits[23]	auto[0]	auto[0]	9099198	1			T28	91		T29	4977		T30	8280
bins_for_gpio_bits[23]	auto[0]	auto[1]	281846	1			T28	3		T30	462		T31	40
bins_for_gpio_bits[23]	auto[1]	auto[0]	281998	1			T28	3		T30	460		T31	40
bins_for_gpio_bits[23]	auto[1]	auto[1]	6073979	1			T28	22		T29	5074		T30	16112
bins_for_gpio_bits[24]	auto[0]	auto[0]	9111985	1			T28	97		T29	5480		T30	8273
bins_for_gpio_bits[24]	auto[0]	auto[1]	282273	1			T28	1		T30	480		T31	44
bins_for_gpio_bits[24]	auto[1]	auto[0]	282444	1			T28	1		T30	480		T31	44
bins_for_gpio_bits[24]	auto[1]	auto[1]	6060319	1			T28	20		T29	4571		T30	16081
bins_for_gpio_bits[25]	auto[0]	auto[0]	9099146	1			T28	98		T29	5236		T30	8362
bins_for_gpio_bits[25]	auto[0]	auto[1]	282458	1			T28	1		T30	490		T31	41
bins_for_gpio_bits[25]	auto[1]	auto[0]	282614	1			T28	1		T30	488		T31	42
bins_for_gpio_bits[25]	auto[1]	auto[1]	6072803	1			T28	19		T29	4815		T30	15974
bins_for_gpio_bits[26]	auto[0]	auto[0]	9103809	1			T28	92		T29	4956		T30	8251
bins_for_gpio_bits[26]	auto[0]	auto[1]	281129	1			T28	2		T30	512		T31	40
bins_for_gpio_bits[26]	auto[1]	auto[0]	281284	1			T28	2		T30	510		T31	40
bins_for_gpio_bits[26]	auto[1]	auto[1]	6070799	1			T28	23		T29	5095		T30	16041
bins_for_gpio_bits[27]	auto[0]	auto[0]	9098217	1			T28	83		T29	5292		T30	8468
bins_for_gpio_bits[27]	auto[0]	auto[1]	281366	1			T28	1		T30	481		T31	40
bins_for_gpio_bits[27]	auto[1]	auto[0]	281542	1			T28	1		T30	478		T31	40
bins_for_gpio_bits[27]	auto[1]	auto[1]	6075896	1			T28	34		T29	4759		T30	15887
bins_for_gpio_bits[28]	auto[0]	auto[0]	9103690	1			T28	103		T29	5209		T30	8509
bins_for_gpio_bits[28]	auto[0]	auto[1]	282284	1			T28	1		T30	496		T31	42
bins_for_gpio_bits[28]	auto[1]	auto[0]	282425	1			T28	1		T30	495		T31	42
bins_for_gpio_bits[28]	auto[1]	auto[1]	6068622	1			T28	14		T29	4842		T30	15814
bins_for_gpio_bits[29]	auto[0]	auto[0]	9107065	1			T28	94		T29	5042		T30	8534
bins_for_gpio_bits[29]	auto[0]	auto[1]	281823	1			T30	514		T31	42		T34	42
bins_for_gpio_bits[29]	auto[1]	auto[0]	282028	1			T30	512		T31	43		T34	42
bins_for_gpio_bits[29]	auto[1]	auto[1]	6066105	1			T28	25		T29	5009		T30	15754
bins_for_gpio_bits[30]	auto[0]	auto[0]	9107766	1			T28	91		T29	5035		T30	8277
bins_for_gpio_bits[30]	auto[0]	auto[1]	281951	1			T28	3		T30	481		T31	39
bins_for_gpio_bits[30]	auto[1]	auto[0]	282073	1			T28	3		T30	479		T31	40
bins_for_gpio_bits[30]	auto[1]	auto[1]	6065231	1			T28	22		T29	5016		T30	16077
bins_for_gpio_bits[31]	auto[0]	auto[0]	9099033	1			T28	89		T29	4797		T30	8616
bins_for_gpio_bits[31]	auto[0]	auto[1]	281930	1			T28	3		T30	505		T31	40
bins_for_gpio_bits[31]	auto[1]	auto[0]	282119	1			T28	3		T30	501		T31	40
bins_for_gpio_bits[31]	auto[1]	auto[1]	6073939	1			T28	24		T29	5254		T30	15692