Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9064450 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15288 |
| auto[1] |
6927173 |
1 |
|
|
T30 |
9535 |
|
T33 |
105 |
|
T38 |
30329 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15098164 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23392 |
| auto[1] |
893459 |
1 |
|
|
T30 |
1431 |
|
T33 |
9 |
|
T38 |
3658 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9058840 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14517 |
| auto[1] |
6932783 |
1 |
|
|
T30 |
10306 |
|
T33 |
161 |
|
T38 |
30025 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3026916 |
1 |
|
|
T30 |
4539 |
|
T33 |
92 |
|
T38 |
12773 |
| auto[1] |
auto[0] |
auto[1] |
447971 |
1 |
|
|
T30 |
758 |
|
T33 |
7 |
|
T38 |
1786 |
| auto[1] |
auto[1] |
auto[0] |
3012408 |
1 |
|
|
T30 |
4336 |
|
T33 |
60 |
|
T38 |
13594 |
| auto[1] |
auto[1] |
auto[1] |
445488 |
1 |
|
|
T30 |
673 |
|
T33 |
2 |
|
T38 |
1872 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9081997 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14934 |
| auto[1] |
6909626 |
1 |
|
|
T30 |
9889 |
|
T33 |
116 |
|
T38 |
31848 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15100090 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23220 |
| auto[1] |
891533 |
1 |
|
|
T30 |
1603 |
|
T33 |
12 |
|
T38 |
4128 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9060679 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
13771 |
| auto[1] |
6930944 |
1 |
|
|
T30 |
11052 |
|
T33 |
176 |
|
T38 |
32114 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3050002 |
1 |
|
|
T30 |
5104 |
|
T33 |
114 |
|
T38 |
13947 |
| auto[1] |
auto[0] |
auto[1] |
451341 |
1 |
|
|
T30 |
880 |
|
T33 |
9 |
|
T38 |
2082 |
| auto[1] |
auto[1] |
auto[0] |
2989409 |
1 |
|
|
T30 |
4345 |
|
T33 |
50 |
|
T38 |
14039 |
| auto[1] |
auto[1] |
auto[1] |
440192 |
1 |
|
|
T30 |
723 |
|
T33 |
3 |
|
T38 |
2046 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9058747 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14606 |
| auto[1] |
6932876 |
1 |
|
|
T30 |
10217 |
|
T33 |
186 |
|
T38 |
30556 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15100046 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23514 |
| auto[1] |
891577 |
1 |
|
|
T30 |
1309 |
|
T33 |
11 |
|
T38 |
4027 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9059371 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15292 |
| auto[1] |
6932252 |
1 |
|
|
T30 |
9531 |
|
T33 |
180 |
|
T38 |
31587 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3005207 |
1 |
|
|
T30 |
3867 |
|
T33 |
86 |
|
T38 |
13608 |
| auto[1] |
auto[0] |
auto[1] |
442957 |
1 |
|
|
T30 |
596 |
|
T33 |
5 |
|
T38 |
1856 |
| auto[1] |
auto[1] |
auto[0] |
3035468 |
1 |
|
|
T30 |
4355 |
|
T33 |
83 |
|
T38 |
13952 |
| auto[1] |
auto[1] |
auto[1] |
448620 |
1 |
|
|
T30 |
713 |
|
T33 |
6 |
|
T38 |
2171 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9033829 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14910 |
| auto[1] |
6957794 |
1 |
|
|
T30 |
9913 |
|
T33 |
113 |
|
T38 |
30857 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15102156 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23404 |
| auto[1] |
889467 |
1 |
|
|
T30 |
1419 |
|
T33 |
7 |
|
T38 |
3829 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9081880 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14879 |
| auto[1] |
6909743 |
1 |
|
|
T30 |
9944 |
|
T33 |
157 |
|
T38 |
29995 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2997507 |
1 |
|
|
T30 |
4494 |
|
T33 |
91 |
|
T38 |
13196 |
| auto[1] |
auto[0] |
auto[1] |
441416 |
1 |
|
|
T30 |
727 |
|
T33 |
5 |
|
T38 |
1974 |
| auto[1] |
auto[1] |
auto[0] |
3022769 |
1 |
|
|
T30 |
4031 |
|
T33 |
59 |
|
T38 |
12970 |
| auto[1] |
auto[1] |
auto[1] |
448051 |
1 |
|
|
T30 |
692 |
|
T33 |
2 |
|
T38 |
1855 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9044367 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14913 |
| auto[1] |
6947256 |
1 |
|
|
T30 |
9910 |
|
T33 |
116 |
|
T38 |
29917 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15095279 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23377 |
| auto[1] |
896344 |
1 |
|
|
T30 |
1446 |
|
T33 |
12 |
|
T38 |
3864 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9038694 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14490 |
| auto[1] |
6952929 |
1 |
|
|
T30 |
10333 |
|
T33 |
200 |
|
T38 |
30575 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3014177 |
1 |
|
|
T30 |
4479 |
|
T33 |
105 |
|
T38 |
13256 |
| auto[1] |
auto[0] |
auto[1] |
444808 |
1 |
|
|
T30 |
756 |
|
T33 |
4 |
|
T38 |
1889 |
| auto[1] |
auto[1] |
auto[0] |
3042408 |
1 |
|
|
T30 |
4408 |
|
T33 |
83 |
|
T38 |
13455 |
| auto[1] |
auto[1] |
auto[1] |
451536 |
1 |
|
|
T30 |
690 |
|
T33 |
8 |
|
T38 |
1975 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9063883 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14855 |
| auto[1] |
6927740 |
1 |
|
|
T30 |
9968 |
|
T33 |
165 |
|
T38 |
31802 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15106168 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23562 |
| auto[1] |
885455 |
1 |
|
|
T30 |
1261 |
|
T33 |
13 |
|
T38 |
3780 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9095508 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15719 |
| auto[1] |
6896115 |
1 |
|
|
T30 |
9104 |
|
T33 |
198 |
|
T38 |
30016 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3012660 |
1 |
|
|
T30 |
4140 |
|
T33 |
84 |
|
T38 |
12560 |
| auto[1] |
auto[0] |
auto[1] |
444287 |
1 |
|
|
T30 |
695 |
|
T33 |
8 |
|
T38 |
1897 |
| auto[1] |
auto[1] |
auto[0] |
2998000 |
1 |
|
|
T30 |
3703 |
|
T33 |
101 |
|
T38 |
13676 |
| auto[1] |
auto[1] |
auto[1] |
441168 |
1 |
|
|
T30 |
566 |
|
T33 |
5 |
|
T38 |
1883 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9005453 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14373 |
| auto[1] |
6986170 |
1 |
|
|
T30 |
10450 |
|
T33 |
175 |
|
T38 |
31267 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15103063 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23401 |
| auto[1] |
888560 |
1 |
|
|
T30 |
1422 |
|
T33 |
8 |
|
T38 |
4088 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9077344 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14706 |
| auto[1] |
6914279 |
1 |
|
|
T30 |
10117 |
|
T33 |
151 |
|
T38 |
31145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2987828 |
1 |
|
|
T30 |
4176 |
|
T33 |
60 |
|
T38 |
13408 |
| auto[1] |
auto[0] |
auto[1] |
438596 |
1 |
|
|
T30 |
697 |
|
T33 |
4 |
|
T38 |
1999 |
| auto[1] |
auto[1] |
auto[0] |
3037891 |
1 |
|
|
T30 |
4519 |
|
T33 |
83 |
|
T38 |
13649 |
| auto[1] |
auto[1] |
auto[1] |
449964 |
1 |
|
|
T30 |
725 |
|
T33 |
4 |
|
T38 |
2089 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9059432 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14078 |
| auto[1] |
6932191 |
1 |
|
|
T30 |
10745 |
|
T33 |
144 |
|
T38 |
30075 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15095609 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23479 |
| auto[1] |
896014 |
1 |
|
|
T30 |
1344 |
|
T33 |
11 |
|
T38 |
3830 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9043646 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15119 |
| auto[1] |
6947977 |
1 |
|
|
T30 |
9704 |
|
T33 |
175 |
|
T38 |
30620 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3037376 |
1 |
|
|
T30 |
4061 |
|
T33 |
78 |
|
T38 |
13845 |
| auto[1] |
auto[0] |
auto[1] |
449054 |
1 |
|
|
T30 |
660 |
|
T33 |
8 |
|
T38 |
1951 |
| auto[1] |
auto[1] |
auto[0] |
3014587 |
1 |
|
|
T30 |
4299 |
|
T33 |
86 |
|
T38 |
12945 |
| auto[1] |
auto[1] |
auto[1] |
446960 |
1 |
|
|
T30 |
684 |
|
T33 |
3 |
|
T38 |
1879 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9113873 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15012 |
| auto[1] |
6877750 |
1 |
|
|
T30 |
9811 |
|
T33 |
189 |
|
T38 |
30631 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15099900 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23295 |
| auto[1] |
891723 |
1 |
|
|
T30 |
1528 |
|
T33 |
8 |
|
T38 |
3679 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9052992 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14432 |
| auto[1] |
6938631 |
1 |
|
|
T30 |
10391 |
|
T33 |
146 |
|
T38 |
30008 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3050196 |
1 |
|
|
T30 |
4553 |
|
T33 |
52 |
|
T38 |
13662 |
| auto[1] |
auto[0] |
auto[1] |
449111 |
1 |
|
|
T30 |
765 |
|
T38 |
1890 |
|
T39 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2996712 |
1 |
|
|
T30 |
4310 |
|
T33 |
86 |
|
T38 |
12667 |
| auto[1] |
auto[1] |
auto[1] |
442612 |
1 |
|
|
T30 |
763 |
|
T33 |
8 |
|
T38 |
1789 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9053076 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15444 |
| auto[1] |
6938547 |
1 |
|
|
T30 |
9379 |
|
T33 |
172 |
|
T38 |
30639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15094935 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23347 |
| auto[1] |
896688 |
1 |
|
|
T30 |
1476 |
|
T33 |
5 |
|
T38 |
3747 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9027908 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14575 |
| auto[1] |
6963715 |
1 |
|
|
T30 |
10248 |
|
T33 |
107 |
|
T38 |
30364 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3045647 |
1 |
|
|
T30 |
4669 |
|
T33 |
55 |
|
T38 |
13470 |
| auto[1] |
auto[0] |
auto[1] |
450242 |
1 |
|
|
T30 |
804 |
|
T33 |
3 |
|
T38 |
1878 |
| auto[1] |
auto[1] |
auto[0] |
3021380 |
1 |
|
|
T30 |
4103 |
|
T33 |
47 |
|
T38 |
13147 |
| auto[1] |
auto[1] |
auto[1] |
446446 |
1 |
|
|
T30 |
672 |
|
T33 |
2 |
|
T38 |
1869 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9115079 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14403 |
| auto[1] |
6876544 |
1 |
|
|
T30 |
10420 |
|
T33 |
143 |
|
T38 |
31717 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15098531 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23197 |
| auto[1] |
893092 |
1 |
|
|
T30 |
1626 |
|
T33 |
14 |
|
T38 |
3895 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9055301 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
13899 |
| auto[1] |
6936322 |
1 |
|
|
T30 |
10924 |
|
T33 |
198 |
|
T38 |
31130 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3037877 |
1 |
|
|
T30 |
4783 |
|
T33 |
95 |
|
T38 |
13613 |
| auto[1] |
auto[0] |
auto[1] |
448970 |
1 |
|
|
T30 |
841 |
|
T33 |
6 |
|
T38 |
1986 |
| auto[1] |
auto[1] |
auto[0] |
3005353 |
1 |
|
|
T30 |
4515 |
|
T33 |
89 |
|
T38 |
13622 |
| auto[1] |
auto[1] |
auto[1] |
444122 |
1 |
|
|
T30 |
785 |
|
T33 |
8 |
|
T38 |
1909 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9011110 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14717 |
| auto[1] |
6980513 |
1 |
|
|
T30 |
10106 |
|
T33 |
186 |
|
T38 |
29867 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15101611 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23419 |
| auto[1] |
890012 |
1 |
|
|
T30 |
1404 |
|
T33 |
7 |
|
T38 |
3927 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9073592 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14806 |
| auto[1] |
6918031 |
1 |
|
|
T30 |
10017 |
|
T33 |
126 |
|
T38 |
31292 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3001084 |
1 |
|
|
T30 |
4301 |
|
T33 |
61 |
|
T38 |
13800 |
| auto[1] |
auto[0] |
auto[1] |
442383 |
1 |
|
|
T30 |
707 |
|
T33 |
5 |
|
T38 |
2018 |
| auto[1] |
auto[1] |
auto[0] |
3026935 |
1 |
|
|
T30 |
4312 |
|
T33 |
58 |
|
T38 |
13565 |
| auto[1] |
auto[1] |
auto[1] |
447629 |
1 |
|
|
T30 |
697 |
|
T33 |
2 |
|
T38 |
1909 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9069485 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15846 |
| auto[1] |
6922138 |
1 |
|
|
T30 |
8977 |
|
T33 |
86 |
|
T38 |
30942 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15098077 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23331 |
| auto[1] |
893546 |
1 |
|
|
T30 |
1492 |
|
T33 |
12 |
|
T38 |
4039 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9060097 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14059 |
| auto[1] |
6931526 |
1 |
|
|
T30 |
10764 |
|
T33 |
164 |
|
T38 |
32146 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3030111 |
1 |
|
|
T30 |
5120 |
|
T33 |
103 |
|
T38 |
14062 |
| auto[1] |
auto[0] |
auto[1] |
449007 |
1 |
|
|
T30 |
834 |
|
T33 |
11 |
|
T38 |
2072 |
| auto[1] |
auto[1] |
auto[0] |
3007869 |
1 |
|
|
T30 |
4152 |
|
T33 |
49 |
|
T38 |
14045 |
| auto[1] |
auto[1] |
auto[1] |
444539 |
1 |
|
|
T30 |
658 |
|
T33 |
1 |
|
T38 |
1967 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9070263 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14962 |
| auto[1] |
6921360 |
1 |
|
|
T30 |
9861 |
|
T33 |
143 |
|
T38 |
30822 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15098552 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23384 |
| auto[1] |
893071 |
1 |
|
|
T30 |
1439 |
|
T33 |
11 |
|
T38 |
3684 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9051095 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14684 |
| auto[1] |
6940528 |
1 |
|
|
T30 |
10139 |
|
T33 |
175 |
|
T38 |
29567 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3038526 |
1 |
|
|
T30 |
4348 |
|
T33 |
94 |
|
T38 |
12725 |
| auto[1] |
auto[0] |
auto[1] |
450150 |
1 |
|
|
T30 |
724 |
|
T33 |
8 |
|
T38 |
1803 |
| auto[1] |
auto[1] |
auto[0] |
3008931 |
1 |
|
|
T30 |
4352 |
|
T33 |
70 |
|
T38 |
13158 |
| auto[1] |
auto[1] |
auto[1] |
442921 |
1 |
|
|
T30 |
715 |
|
T33 |
3 |
|
T38 |
1881 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9039236 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14333 |
| auto[1] |
6952387 |
1 |
|
|
T30 |
10490 |
|
T33 |
122 |
|
T38 |
29458 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15100597 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23274 |
| auto[1] |
891026 |
1 |
|
|
T30 |
1549 |
|
T33 |
8 |
|
T38 |
3782 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9069918 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
13938 |
| auto[1] |
6921705 |
1 |
|
|
T30 |
10885 |
|
T33 |
133 |
|
T38 |
30454 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3010673 |
1 |
|
|
T30 |
4586 |
|
T33 |
70 |
|
T38 |
13714 |
| auto[1] |
auto[0] |
auto[1] |
444684 |
1 |
|
|
T30 |
744 |
|
T33 |
7 |
|
T38 |
1965 |
| auto[1] |
auto[1] |
auto[0] |
3020006 |
1 |
|
|
T30 |
4750 |
|
T33 |
55 |
|
T38 |
12958 |
| auto[1] |
auto[1] |
auto[1] |
446342 |
1 |
|
|
T30 |
805 |
|
T33 |
1 |
|
T38 |
1817 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9057936 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
13972 |
| auto[1] |
6933687 |
1 |
|
|
T30 |
10851 |
|
T33 |
195 |
|
T38 |
30351 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15107172 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23420 |
| auto[1] |
884451 |
1 |
|
|
T30 |
1403 |
|
T33 |
9 |
|
T38 |
3934 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9105872 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14532 |
| auto[1] |
6885751 |
1 |
|
|
T30 |
10291 |
|
T33 |
140 |
|
T38 |
30990 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3007707 |
1 |
|
|
T30 |
4601 |
|
T33 |
38 |
|
T38 |
13916 |
| auto[1] |
auto[0] |
auto[1] |
444600 |
1 |
|
|
T30 |
713 |
|
T33 |
2 |
|
T38 |
2063 |
| auto[1] |
auto[1] |
auto[0] |
2993593 |
1 |
|
|
T30 |
4287 |
|
T33 |
93 |
|
T38 |
13140 |
| auto[1] |
auto[1] |
auto[1] |
439851 |
1 |
|
|
T30 |
690 |
|
T33 |
7 |
|
T38 |
1871 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9051361 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14257 |
| auto[1] |
6940262 |
1 |
|
|
T30 |
10566 |
|
T33 |
138 |
|
T38 |
30977 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15098826 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23291 |
| auto[1] |
892797 |
1 |
|
|
T30 |
1532 |
|
T33 |
10 |
|
T38 |
3865 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9043131 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
13694 |
| auto[1] |
6948492 |
1 |
|
|
T30 |
11129 |
|
T33 |
141 |
|
T38 |
31294 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3017389 |
1 |
|
|
T30 |
4654 |
|
T33 |
81 |
|
T38 |
14253 |
| auto[1] |
auto[0] |
auto[1] |
443765 |
1 |
|
|
T30 |
731 |
|
T33 |
6 |
|
T38 |
2064 |
| auto[1] |
auto[1] |
auto[0] |
3038306 |
1 |
|
|
T30 |
4943 |
|
T33 |
50 |
|
T38 |
13176 |
| auto[1] |
auto[1] |
auto[1] |
449032 |
1 |
|
|
T30 |
801 |
|
T33 |
4 |
|
T38 |
1801 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9042566 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14427 |
| auto[1] |
6949057 |
1 |
|
|
T30 |
10396 |
|
T33 |
140 |
|
T38 |
31331 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15101100 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23410 |
| auto[1] |
890523 |
1 |
|
|
T30 |
1413 |
|
T33 |
8 |
|
T38 |
3769 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9064502 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15124 |
| auto[1] |
6927121 |
1 |
|
|
T30 |
9699 |
|
T33 |
134 |
|
T38 |
30100 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2988580 |
1 |
|
|
T30 |
3928 |
|
T33 |
77 |
|
T38 |
13226 |
| auto[1] |
auto[0] |
auto[1] |
439133 |
1 |
|
|
T30 |
642 |
|
T33 |
5 |
|
T38 |
1781 |
| auto[1] |
auto[1] |
auto[0] |
3048018 |
1 |
|
|
T30 |
4358 |
|
T33 |
49 |
|
T38 |
13105 |
| auto[1] |
auto[1] |
auto[1] |
451390 |
1 |
|
|
T30 |
771 |
|
T33 |
3 |
|
T38 |
1988 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9061031 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14334 |
| auto[1] |
6930592 |
1 |
|
|
T30 |
10489 |
|
T33 |
129 |
|
T38 |
31348 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15097909 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23503 |
| auto[1] |
893714 |
1 |
|
|
T30 |
1320 |
|
T33 |
12 |
|
T38 |
3948 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9041934 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15061 |
| auto[1] |
6949689 |
1 |
|
|
T30 |
9762 |
|
T33 |
128 |
|
T38 |
31076 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3039282 |
1 |
|
|
T30 |
4171 |
|
T33 |
53 |
|
T38 |
13325 |
| auto[1] |
auto[0] |
auto[1] |
449539 |
1 |
|
|
T30 |
617 |
|
T33 |
4 |
|
T38 |
1983 |
| auto[1] |
auto[1] |
auto[0] |
3016693 |
1 |
|
|
T30 |
4271 |
|
T33 |
63 |
|
T38 |
13803 |
| auto[1] |
auto[1] |
auto[1] |
444175 |
1 |
|
|
T30 |
703 |
|
T33 |
8 |
|
T38 |
1965 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9042272 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
14055 |
| auto[1] |
6949351 |
1 |
|
|
T30 |
10768 |
|
T33 |
111 |
|
T38 |
31303 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15104140 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
23442 |
| auto[1] |
887483 |
1 |
|
|
T30 |
1381 |
|
T33 |
12 |
|
T38 |
3836 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9083134 |
1 |
|
|
T28 |
64 |
|
T29 |
10051 |
|
T30 |
15142 |
| auto[1] |
6908489 |
1 |
|
|
T30 |
9681 |
|
T33 |
177 |
|
T38 |
30735 |