Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3016845 |
1 |
|
|
T30 |
4184 |
|
T33 |
104 |
|
T38 |
13743 |
auto[1] |
auto[0] |
auto[1] |
444548 |
1 |
|
|
T30 |
711 |
|
T33 |
6 |
|
T38 |
2003 |
auto[1] |
auto[1] |
auto[0] |
3004161 |
1 |
|
|
T30 |
4116 |
|
T33 |
61 |
|
T38 |
13156 |
auto[1] |
auto[1] |
auto[1] |
442935 |
1 |
|
|
T30 |
670 |
|
T33 |
6 |
|
T38 |
1833 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |