Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 948
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T767 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1713965579 Jul 26 05:38:45 PM PDT 24 Jul 26 05:38:45 PM PDT 24 23462424 ps
T768 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1242675032 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:42 PM PDT 24 1263566802 ps
T769 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1072983819 Jul 26 05:38:43 PM PDT 24 Jul 26 05:38:44 PM PDT 24 18850631 ps
T770 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3058994361 Jul 26 05:38:51 PM PDT 24 Jul 26 05:38:52 PM PDT 24 106109044 ps
T771 /workspace/coverage/cover_reg_top/2.gpio_intr_test.352592551 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 11768069 ps
T772 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4092692299 Jul 26 05:38:53 PM PDT 24 Jul 26 05:38:54 PM PDT 24 18671784 ps
T773 /workspace/coverage/cover_reg_top/22.gpio_intr_test.4214048609 Jul 26 05:38:54 PM PDT 24 Jul 26 05:38:55 PM PDT 24 16179307 ps
T102 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.690986707 Jul 26 05:38:45 PM PDT 24 Jul 26 05:38:46 PM PDT 24 21953014 ps
T774 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3831587137 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:52 PM PDT 24 101503831 ps
T103 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.660482519 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:49 PM PDT 24 14837120 ps
T775 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3905293120 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 357410262 ps
T776 /workspace/coverage/cover_reg_top/0.gpio_intr_test.917873277 Jul 26 05:38:42 PM PDT 24 Jul 26 05:38:42 PM PDT 24 13639941 ps
T777 /workspace/coverage/cover_reg_top/38.gpio_intr_test.22813435 Jul 26 05:39:01 PM PDT 24 Jul 26 05:39:02 PM PDT 24 12977005 ps
T104 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1887627890 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:41 PM PDT 24 28090614 ps
T114 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3455526152 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 56087381 ps
T778 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.765313102 Jul 26 05:38:50 PM PDT 24 Jul 26 05:38:54 PM PDT 24 1492868545 ps
T779 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.971546420 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:49 PM PDT 24 334345828 ps
T780 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3424587079 Jul 26 05:38:54 PM PDT 24 Jul 26 05:38:54 PM PDT 24 35918101 ps
T781 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3913411226 Jul 26 05:38:56 PM PDT 24 Jul 26 05:38:59 PM PDT 24 150133659 ps
T782 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3231454824 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 27797385 ps
T783 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3537401830 Jul 26 05:38:42 PM PDT 24 Jul 26 05:38:44 PM PDT 24 121727847 ps
T784 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1799969050 Jul 26 05:38:46 PM PDT 24 Jul 26 05:38:47 PM PDT 24 32016635 ps
T785 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2142388267 Jul 26 05:38:54 PM PDT 24 Jul 26 05:38:55 PM PDT 24 14743507 ps
T786 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1095545380 Jul 26 05:38:46 PM PDT 24 Jul 26 05:38:47 PM PDT 24 15124899 ps
T787 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3137219054 Jul 26 05:38:42 PM PDT 24 Jul 26 05:38:43 PM PDT 24 70036255 ps
T788 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1748829619 Jul 26 05:38:49 PM PDT 24 Jul 26 05:38:52 PM PDT 24 41127233 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3165739465 Jul 26 05:38:51 PM PDT 24 Jul 26 05:38:52 PM PDT 24 235385075 ps
T115 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.606804785 Jul 26 05:38:54 PM PDT 24 Jul 26 05:38:55 PM PDT 24 20209824 ps
T790 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1876094236 Jul 26 05:39:06 PM PDT 24 Jul 26 05:39:07 PM PDT 24 105175228 ps
T791 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1333207359 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:49 PM PDT 24 22220235 ps
T116 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2162541617 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:49 PM PDT 24 33708465 ps
T792 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.364731104 Jul 26 05:38:55 PM PDT 24 Jul 26 05:38:56 PM PDT 24 36316727 ps
T793 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2867939067 Jul 26 05:38:44 PM PDT 24 Jul 26 05:38:45 PM PDT 24 176033082 ps
T105 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2569688125 Jul 26 05:38:47 PM PDT 24 Jul 26 05:38:47 PM PDT 24 30798718 ps
T794 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1293678574 Jul 26 05:38:54 PM PDT 24 Jul 26 05:38:55 PM PDT 24 251852006 ps
T795 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3572874533 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 12055969 ps
T796 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2009132892 Jul 26 05:38:49 PM PDT 24 Jul 26 05:38:50 PM PDT 24 30606788 ps
T797 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3158610967 Jul 26 05:38:46 PM PDT 24 Jul 26 05:38:47 PM PDT 24 14033859 ps
T798 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1667612190 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 41912957 ps
T799 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2316748103 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 12560574 ps
T800 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2208207578 Jul 26 05:38:57 PM PDT 24 Jul 26 05:38:59 PM PDT 24 124071684 ps
T801 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3870697591 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:49 PM PDT 24 21512575 ps
T802 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4215189600 Jul 26 05:38:53 PM PDT 24 Jul 26 05:38:54 PM PDT 24 24757047 ps
T803 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.941070456 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:51 PM PDT 24 53842728 ps
T804 /workspace/coverage/cover_reg_top/34.gpio_intr_test.3897114752 Jul 26 05:38:55 PM PDT 24 Jul 26 05:38:55 PM PDT 24 18550729 ps
T805 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1831650581 Jul 26 05:38:53 PM PDT 24 Jul 26 05:38:54 PM PDT 24 27189258 ps
T806 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.409591651 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:44 PM PDT 24 684365252 ps
T106 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3471557251 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:50 PM PDT 24 17245999 ps
T807 /workspace/coverage/cover_reg_top/48.gpio_intr_test.937292289 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 51062162 ps
T808 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1376283449 Jul 26 05:38:51 PM PDT 24 Jul 26 05:38:52 PM PDT 24 14709193 ps
T117 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1287049483 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 60189801 ps
T109 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1533501840 Jul 26 05:38:49 PM PDT 24 Jul 26 05:38:50 PM PDT 24 60546564 ps
T809 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3396501556 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 23397913 ps
T810 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1114230363 Jul 26 05:38:59 PM PDT 24 Jul 26 05:39:00 PM PDT 24 36361411 ps
T811 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3997035118 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 16387354 ps
T812 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2459588134 Jul 26 05:38:50 PM PDT 24 Jul 26 05:38:50 PM PDT 24 38061325 ps
T118 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1588922635 Jul 26 05:38:44 PM PDT 24 Jul 26 05:38:45 PM PDT 24 17739685 ps
T813 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1469799369 Jul 26 05:38:52 PM PDT 24 Jul 26 05:38:53 PM PDT 24 174703308 ps
T119 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1679717027 Jul 26 05:38:39 PM PDT 24 Jul 26 05:38:40 PM PDT 24 94380433 ps
T814 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2343873376 Jul 26 05:38:54 PM PDT 24 Jul 26 05:38:56 PM PDT 24 117911423 ps
T815 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2012115967 Jul 26 05:38:51 PM PDT 24 Jul 26 05:38:52 PM PDT 24 288894311 ps
T816 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1243183892 Jul 26 05:38:47 PM PDT 24 Jul 26 05:38:48 PM PDT 24 16457389 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.952300019 Jul 26 05:38:50 PM PDT 24 Jul 26 05:38:53 PM PDT 24 394845055 ps
T107 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1183299780 Jul 26 05:38:42 PM PDT 24 Jul 26 05:38:43 PM PDT 24 17566059 ps
T123 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1207761731 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:49 PM PDT 24 130668244 ps
T818 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3648457017 Jul 26 05:38:42 PM PDT 24 Jul 26 05:38:43 PM PDT 24 157394071 ps
T819 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1681521622 Jul 26 05:39:06 PM PDT 24 Jul 26 05:39:07 PM PDT 24 43160084 ps
T820 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2747429578 Jul 26 05:38:49 PM PDT 24 Jul 26 05:38:50 PM PDT 24 17232847 ps
T821 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1553257432 Jul 26 05:38:47 PM PDT 24 Jul 26 05:38:48 PM PDT 24 13189379 ps
T822 /workspace/coverage/cover_reg_top/27.gpio_intr_test.3789540876 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 77092443 ps
T823 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3144006017 Jul 26 05:38:59 PM PDT 24 Jul 26 05:39:00 PM PDT 24 22207709 ps
T824 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2623801927 Jul 26 05:38:55 PM PDT 24 Jul 26 05:38:56 PM PDT 24 20236619 ps
T825 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2716824632 Jul 26 05:38:49 PM PDT 24 Jul 26 05:38:50 PM PDT 24 37001096 ps
T826 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1627602482 Jul 26 05:38:58 PM PDT 24 Jul 26 05:38:59 PM PDT 24 36216496 ps
T827 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.779562425 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:50 PM PDT 24 13629664 ps
T828 /workspace/coverage/cover_reg_top/31.gpio_intr_test.537640799 Jul 26 05:38:58 PM PDT 24 Jul 26 05:38:59 PM PDT 24 10649933 ps
T110 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2678707246 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:49 PM PDT 24 16375263 ps
T829 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1231050513 Jul 26 05:38:52 PM PDT 24 Jul 26 05:38:54 PM PDT 24 23882238 ps
T830 /workspace/coverage/cover_reg_top/5.gpio_intr_test.930153980 Jul 26 05:38:40 PM PDT 24 Jul 26 05:38:41 PM PDT 24 20632717 ps
T831 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2156469765 Jul 26 05:38:56 PM PDT 24 Jul 26 05:38:57 PM PDT 24 193865406 ps
T832 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3494470005 Jul 26 05:38:44 PM PDT 24 Jul 26 05:38:45 PM PDT 24 17352322 ps
T833 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.290732487 Jul 26 05:38:46 PM PDT 24 Jul 26 05:38:47 PM PDT 24 23117834 ps
T834 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3634073779 Jul 26 05:38:43 PM PDT 24 Jul 26 05:38:44 PM PDT 24 55152468 ps
T835 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1728149163 Jul 26 05:38:47 PM PDT 24 Jul 26 05:38:48 PM PDT 24 48985781 ps
T836 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3307296624 Jul 26 05:38:58 PM PDT 24 Jul 26 05:38:59 PM PDT 24 32627435 ps
T837 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3658481077 Jul 26 05:38:36 PM PDT 24 Jul 26 05:38:37 PM PDT 24 26242353 ps
T838 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2235576834 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 15035917 ps
T839 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.312159876 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:43 PM PDT 24 236691263 ps
T840 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2345309298 Jul 26 05:38:41 PM PDT 24 Jul 26 05:38:42 PM PDT 24 70160004 ps
T108 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1243410863 Jul 26 05:38:44 PM PDT 24 Jul 26 05:38:45 PM PDT 24 33467538 ps
T841 /workspace/coverage/cover_reg_top/39.gpio_intr_test.873038657 Jul 26 05:38:58 PM PDT 24 Jul 26 05:38:59 PM PDT 24 15869694 ps
T842 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1657951196 Jul 26 05:38:39 PM PDT 24 Jul 26 05:38:40 PM PDT 24 304371925 ps
T843 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.139910651 Jul 26 05:38:49 PM PDT 24 Jul 26 05:38:50 PM PDT 24 15268386 ps
T844 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.527917639 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 66961458 ps
T845 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1790216266 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:50 PM PDT 24 149650328 ps
T846 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1437840213 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:49 PM PDT 24 17710663 ps
T847 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3290154669 Jul 26 05:38:48 PM PDT 24 Jul 26 05:38:50 PM PDT 24 109791049 ps
T848 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1084694940 Jul 26 05:38:47 PM PDT 24 Jul 26 05:38:48 PM PDT 24 16144638 ps
T849 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.943620164 Jul 26 05:39:25 PM PDT 24 Jul 26 05:39:27 PM PDT 24 65364416 ps
T850 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3052453472 Jul 26 05:39:11 PM PDT 24 Jul 26 05:39:12 PM PDT 24 237922400 ps
T851 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4135942186 Jul 26 05:39:03 PM PDT 24 Jul 26 05:39:04 PM PDT 24 37275186 ps
T852 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2936745480 Jul 26 05:39:30 PM PDT 24 Jul 26 05:39:31 PM PDT 24 580831510 ps
T853 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.926601165 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:14 PM PDT 24 76506035 ps
T854 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3434149604 Jul 26 05:39:19 PM PDT 24 Jul 26 05:39:20 PM PDT 24 49179649 ps
T855 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.78029080 Jul 26 05:39:28 PM PDT 24 Jul 26 05:39:30 PM PDT 24 252471793 ps
T856 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3297147802 Jul 26 05:39:25 PM PDT 24 Jul 26 05:39:27 PM PDT 24 316323633 ps
T857 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1013190333 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 34993014 ps
T858 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4238469353 Jul 26 05:39:21 PM PDT 24 Jul 26 05:39:22 PM PDT 24 107242068 ps
T859 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224288630 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:14 PM PDT 24 98938483 ps
T860 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2626994534 Jul 26 05:39:20 PM PDT 24 Jul 26 05:39:21 PM PDT 24 278257362 ps
T861 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749289317 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 39759084 ps
T862 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2116813190 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 77083192 ps
T863 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2030708756 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 160669139 ps
T864 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2701704242 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 210988480 ps
T865 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.158138429 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 42572614 ps
T866 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.602507508 Jul 26 05:39:23 PM PDT 24 Jul 26 05:39:24 PM PDT 24 29029357 ps
T867 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1278807947 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:14 PM PDT 24 218733470 ps
T868 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2822702499 Jul 26 05:39:27 PM PDT 24 Jul 26 05:39:29 PM PDT 24 139106825 ps
T869 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1846299363 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 146515372 ps
T870 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.161987626 Jul 26 05:39:25 PM PDT 24 Jul 26 05:39:27 PM PDT 24 160529981 ps
T871 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2530589321 Jul 26 05:39:21 PM PDT 24 Jul 26 05:39:22 PM PDT 24 231590782 ps
T872 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1207566407 Jul 26 05:39:27 PM PDT 24 Jul 26 05:39:28 PM PDT 24 73786576 ps
T873 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2161881136 Jul 26 05:38:59 PM PDT 24 Jul 26 05:39:00 PM PDT 24 32739366 ps
T874 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1117475142 Jul 26 05:39:04 PM PDT 24 Jul 26 05:39:05 PM PDT 24 63031384 ps
T875 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1840030988 Jul 26 05:39:28 PM PDT 24 Jul 26 05:39:30 PM PDT 24 151772022 ps
T876 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3811922309 Jul 26 05:39:19 PM PDT 24 Jul 26 05:39:20 PM PDT 24 100234537 ps
T877 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.300498491 Jul 26 05:39:23 PM PDT 24 Jul 26 05:39:25 PM PDT 24 249180852 ps
T878 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2970099577 Jul 26 05:39:24 PM PDT 24 Jul 26 05:39:25 PM PDT 24 50496717 ps
T879 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.471828419 Jul 26 05:39:24 PM PDT 24 Jul 26 05:39:25 PM PDT 24 42719225 ps
T880 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1383477044 Jul 26 05:39:23 PM PDT 24 Jul 26 05:39:25 PM PDT 24 253385306 ps
T881 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1114264076 Jul 26 05:39:23 PM PDT 24 Jul 26 05:39:25 PM PDT 24 115598661 ps
T882 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.547399939 Jul 26 05:39:19 PM PDT 24 Jul 26 05:39:20 PM PDT 24 245587440 ps
T883 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.752391585 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 130810195 ps
T884 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2910692319 Jul 26 05:39:23 PM PDT 24 Jul 26 05:39:24 PM PDT 24 50717317 ps
T885 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.914746500 Jul 26 05:39:11 PM PDT 24 Jul 26 05:39:13 PM PDT 24 49662012 ps
T886 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3270099650 Jul 26 05:39:25 PM PDT 24 Jul 26 05:39:27 PM PDT 24 62011869 ps
T887 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2307783035 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 173002682 ps
T888 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3786215141 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 106533640 ps
T889 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.855945881 Jul 26 05:39:11 PM PDT 24 Jul 26 05:39:13 PM PDT 24 237190951 ps
T890 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1400831276 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 81360323 ps
T891 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3977747491 Jul 26 05:39:23 PM PDT 24 Jul 26 05:39:25 PM PDT 24 304135421 ps
T892 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1547192272 Jul 26 05:39:02 PM PDT 24 Jul 26 05:39:03 PM PDT 24 33340805 ps
T893 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1834400288 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 36407390 ps
T894 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3437538000 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 91801092 ps
T895 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.717244215 Jul 26 05:39:24 PM PDT 24 Jul 26 05:39:25 PM PDT 24 59414072 ps
T896 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4076476056 Jul 26 05:39:04 PM PDT 24 Jul 26 05:39:05 PM PDT 24 154604785 ps
T897 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2931483659 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 29556903 ps
T898 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1868567887 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 585956511 ps
T899 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98946103 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 224509272 ps
T900 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749685906 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 192475011 ps
T901 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3845294921 Jul 26 05:39:11 PM PDT 24 Jul 26 05:39:13 PM PDT 24 207923624 ps
T902 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3242119317 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:02 PM PDT 24 144633866 ps
T903 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1999925415 Jul 26 05:39:19 PM PDT 24 Jul 26 05:39:20 PM PDT 24 153802707 ps
T904 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2838624130 Jul 26 05:39:01 PM PDT 24 Jul 26 05:39:02 PM PDT 24 66631898 ps
T905 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3033265149 Jul 26 05:39:29 PM PDT 24 Jul 26 05:39:30 PM PDT 24 49073583 ps
T906 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2822908559 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:14 PM PDT 24 234298000 ps
T907 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2451883208 Jul 26 05:39:11 PM PDT 24 Jul 26 05:39:12 PM PDT 24 76384458 ps
T908 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1512904843 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:02 PM PDT 24 236562201 ps
T909 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.319924645 Jul 26 05:39:04 PM PDT 24 Jul 26 05:39:05 PM PDT 24 60154564 ps
T910 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1389706484 Jul 26 05:39:11 PM PDT 24 Jul 26 05:39:13 PM PDT 24 54166165 ps
T911 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4204449303 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 156479884 ps
T912 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3633320369 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:02 PM PDT 24 40496009 ps
T913 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4194973282 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 67247864 ps
T914 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1931768669 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 78787769 ps
T915 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1392936386 Jul 26 05:39:26 PM PDT 24 Jul 26 05:39:28 PM PDT 24 79833459 ps
T916 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3631125486 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 64633850 ps
T917 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4071153155 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:14 PM PDT 24 73661273 ps
T918 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3214241441 Jul 26 05:39:29 PM PDT 24 Jul 26 05:39:30 PM PDT 24 26911623 ps
T919 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.559735980 Jul 26 05:39:10 PM PDT 24 Jul 26 05:39:11 PM PDT 24 35032393 ps
T920 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2981454428 Jul 26 05:39:27 PM PDT 24 Jul 26 05:39:29 PM PDT 24 42592711 ps
T921 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2142898174 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:01 PM PDT 24 63017240 ps
T922 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3647953817 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:15 PM PDT 24 74683277 ps
T923 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.529245175 Jul 26 05:38:58 PM PDT 24 Jul 26 05:38:59 PM PDT 24 38923695 ps
T924 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3544289124 Jul 26 05:39:28 PM PDT 24 Jul 26 05:39:29 PM PDT 24 318489824 ps
T925 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2325534872 Jul 26 05:39:19 PM PDT 24 Jul 26 05:39:20 PM PDT 24 39632357 ps
T926 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2787442721 Jul 26 05:39:22 PM PDT 24 Jul 26 05:39:23 PM PDT 24 72637229 ps
T927 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1547554335 Jul 26 05:39:21 PM PDT 24 Jul 26 05:39:22 PM PDT 24 96637484 ps
T928 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2060078387 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 43995324 ps
T929 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3172627224 Jul 26 05:39:03 PM PDT 24 Jul 26 05:39:04 PM PDT 24 36231879 ps
T930 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2864299344 Jul 26 05:39:29 PM PDT 24 Jul 26 05:39:30 PM PDT 24 55292160 ps
T931 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3754596185 Jul 26 05:39:02 PM PDT 24 Jul 26 05:39:03 PM PDT 24 339238107 ps
T932 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2168562443 Jul 26 05:39:25 PM PDT 24 Jul 26 05:39:26 PM PDT 24 113869249 ps
T933 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3632045814 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 90256147 ps
T934 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1114778590 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 53609667 ps
T935 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2065070680 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 51083267 ps
T936 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.939781433 Jul 26 05:39:39 PM PDT 24 Jul 26 05:39:40 PM PDT 24 39970715 ps
T937 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3067363838 Jul 26 05:39:13 PM PDT 24 Jul 26 05:39:14 PM PDT 24 40784683 ps
T938 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2376266020 Jul 26 05:39:01 PM PDT 24 Jul 26 05:39:03 PM PDT 24 620420398 ps
T939 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1256061424 Jul 26 05:39:00 PM PDT 24 Jul 26 05:39:02 PM PDT 24 286909507 ps
T940 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1316425053 Jul 26 05:39:10 PM PDT 24 Jul 26 05:39:12 PM PDT 24 144707071 ps
T941 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1384646155 Jul 26 05:39:10 PM PDT 24 Jul 26 05:39:12 PM PDT 24 77020118 ps
T942 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2806459425 Jul 26 05:39:23 PM PDT 24 Jul 26 05:39:24 PM PDT 24 338182862 ps
T943 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3738477724 Jul 26 05:39:20 PM PDT 24 Jul 26 05:39:22 PM PDT 24 194116220 ps
T944 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1581388568 Jul 26 05:39:27 PM PDT 24 Jul 26 05:39:28 PM PDT 24 132273243 ps
T945 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4138933625 Jul 26 05:39:12 PM PDT 24 Jul 26 05:39:13 PM PDT 24 184336168 ps
T946 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.67325518 Jul 26 05:39:24 PM PDT 24 Jul 26 05:39:25 PM PDT 24 40762752 ps
T947 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2600083221 Jul 26 05:39:28 PM PDT 24 Jul 26 05:39:29 PM PDT 24 99812243 ps
T948 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2098221030 Jul 26 05:39:02 PM PDT 24 Jul 26 05:39:04 PM PDT 24 112042949 ps

Test location /workspace/coverage/default/9.gpio_stress_all.21471615
Short name T30
Test name
Test status
Simulation time 2776179766 ps
CPU time 38.73 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:40:23 PM PDT 24
Peak memory 198568 kb
Host smart-37bfe944-19ad-4703-b685-f7a4caf4ba90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21471615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpi
o_stress_all.21471615
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1610048584
Short name T37
Test name
Test status
Simulation time 132266340 ps
CPU time 1.48 seconds
Started Jul 26 05:39:34 PM PDT 24
Finished Jul 26 05:39:35 PM PDT 24
Peak memory 198696 kb
Host smart-bc87224f-0123-48ec-9a2b-d90ae785d554
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610048584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1610048584
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2209797473
Short name T7
Test name
Test status
Simulation time 107232871811 ps
CPU time 509.86 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:49:17 PM PDT 24
Peak memory 198780 kb
Host smart-e901579b-2aa2-4668-bf62-3e19f9725ccd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2209797473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2209797473
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3172581666
Short name T26
Test name
Test status
Simulation time 65654053 ps
CPU time 0.77 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 214324 kb
Host smart-43c251db-860d-445c-be3b-25f6b8e08084
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172581666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3172581666
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.620829349
Short name T93
Test name
Test status
Simulation time 62655741 ps
CPU time 0.64 seconds
Started Jul 26 05:38:38 PM PDT 24
Finished Jul 26 05:38:38 PM PDT 24
Peak memory 194668 kb
Host smart-4f378cb9-9468-4fe9-9a8c-bb125a495e84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620829349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.620829349
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.423567801
Short name T45
Test name
Test status
Simulation time 439548172 ps
CPU time 1.42 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:51 PM PDT 24
Peak memory 198360 kb
Host smart-d4f70128-a7e7-4d7a-a8a8-776ee71f768b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423567801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.423567801
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3918884172
Short name T32
Test name
Test status
Simulation time 236701962 ps
CPU time 12.24 seconds
Started Jul 26 05:40:13 PM PDT 24
Finished Jul 26 05:40:26 PM PDT 24
Peak memory 197240 kb
Host smart-4db44238-c49f-458e-8ecf-8a9618c4d762
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918884172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3918884172
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3268841699
Short name T184
Test name
Test status
Simulation time 20215261 ps
CPU time 0.56 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:48 PM PDT 24
Peak memory 195256 kb
Host smart-553501e0-f73a-40f9-83c2-1a7f1807f286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268841699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3268841699
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1679717027
Short name T119
Test name
Test status
Simulation time 94380433 ps
CPU time 0.61 seconds
Started Jul 26 05:38:39 PM PDT 24
Finished Jul 26 05:38:40 PM PDT 24
Peak memory 195216 kb
Host smart-c1bfae00-6154-42c6-a511-a82c4e533e10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679717027 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1679717027
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.gpio_full_random.1006399461
Short name T1
Test name
Test status
Simulation time 41861444 ps
CPU time 0.7 seconds
Started Jul 26 05:39:58 PM PDT 24
Finished Jul 26 05:39:59 PM PDT 24
Peak memory 195064 kb
Host smart-3354e4dd-39cc-4b2f-bab6-51cce3c2ed67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006399461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1006399461
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2343873376
Short name T814
Test name
Test status
Simulation time 117911423 ps
CPU time 1.53 seconds
Started Jul 26 05:38:54 PM PDT 24
Finished Jul 26 05:38:56 PM PDT 24
Peak memory 198112 kb
Host smart-ed4d5803-c30d-484f-abb7-437d8ac5138e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343873376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2343873376
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.329046660
Short name T42
Test name
Test status
Simulation time 169316020 ps
CPU time 0.85 seconds
Started Jul 26 05:38:44 PM PDT 24
Finished Jul 26 05:38:45 PM PDT 24
Peak memory 197148 kb
Host smart-740e2c2d-e338-4cda-ac8f-fd793d4928b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329046660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.329046660
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1242675032
Short name T768
Test name
Test status
Simulation time 1263566802 ps
CPU time 1.52 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 198236 kb
Host smart-f5be8407-5235-4c52-b79b-978002b6fbd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242675032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1242675032
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3346038448
Short name T760
Test name
Test status
Simulation time 15915216 ps
CPU time 0.69 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 195672 kb
Host smart-bd0315d6-2da0-458f-b50d-2758ee07f1e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346038448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3346038448
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2806283807
Short name T731
Test name
Test status
Simulation time 59471683 ps
CPU time 1.47 seconds
Started Jul 26 05:38:37 PM PDT 24
Finished Jul 26 05:38:39 PM PDT 24
Peak memory 198396 kb
Host smart-dc178bc5-7b2c-4aa3-aeb7-b115e01b2561
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806283807 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2806283807
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.660482519
Short name T103
Test name
Test status
Simulation time 14837120 ps
CPU time 0.62 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 194912 kb
Host smart-c4166651-9de9-4f74-b999-f3c6ac2100b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660482519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.660482519
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.917873277
Short name T776
Test name
Test status
Simulation time 13639941 ps
CPU time 0.61 seconds
Started Jul 26 05:38:42 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 194148 kb
Host smart-3b7c5864-59be-47d0-b8db-a5a7b5579059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917873277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.917873277
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3658481077
Short name T837
Test name
Test status
Simulation time 26242353 ps
CPU time 0.61 seconds
Started Jul 26 05:38:36 PM PDT 24
Finished Jul 26 05:38:37 PM PDT 24
Peak memory 194816 kb
Host smart-1f18a3d0-de42-47af-96dc-65dff6777a1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658481077 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3658481077
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.409591651
Short name T806
Test name
Test status
Simulation time 684365252 ps
CPU time 2.61 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:44 PM PDT 24
Peak memory 198408 kb
Host smart-c2806d23-3ae1-44a2-b563-34a979cd3ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409591651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.409591651
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3905293120
Short name T775
Test name
Test status
Simulation time 357410262 ps
CPU time 1.41 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 198304 kb
Host smart-4a5ebd18-70dd-4221-944b-df187eb12836
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905293120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3905293120
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3659870117
Short name T92
Test name
Test status
Simulation time 21642366 ps
CPU time 0.67 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 194640 kb
Host smart-da747e88-c275-49d0-a01e-7d0ca4f96866
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659870117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3659870117
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4191808682
Short name T96
Test name
Test status
Simulation time 2246017673 ps
CPU time 2.52 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:51 PM PDT 24
Peak memory 197420 kb
Host smart-1d9c6290-76e6-42cc-9050-851682167cd2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191808682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.4191808682
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1183299780
Short name T107
Test name
Test status
Simulation time 17566059 ps
CPU time 0.66 seconds
Started Jul 26 05:38:42 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 195648 kb
Host smart-63ec17f2-9253-4d4b-9198-ec6add7fba44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183299780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1183299780
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.312159876
Short name T839
Test name
Test status
Simulation time 236691263 ps
CPU time 0.9 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 198228 kb
Host smart-d3edd530-8f5e-4236-92e9-88993d21fc4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312159876 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.312159876
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.433068998
Short name T97
Test name
Test status
Simulation time 41689999 ps
CPU time 0.63 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 195580 kb
Host smart-13ea854c-2f1d-43a7-8038-65f16ec9ec79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433068998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.433068998
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3396501556
Short name T809
Test name
Test status
Simulation time 23397913 ps
CPU time 0.58 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 194764 kb
Host smart-6a036004-118f-44be-8112-be598935b975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396501556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3396501556
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2020895645
Short name T735
Test name
Test status
Simulation time 194186392 ps
CPU time 1.23 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 198328 kb
Host smart-b5300052-ec5b-4dd2-9d87-ec885f51c635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020895645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2020895645
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1657951196
Short name T842
Test name
Test status
Simulation time 304371925 ps
CPU time 0.84 seconds
Started Jul 26 05:38:39 PM PDT 24
Finished Jul 26 05:38:40 PM PDT 24
Peak memory 197484 kb
Host smart-8bc874fd-3283-4d55-9085-7722407e5eeb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657951196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1657951196
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1745467045
Short name T763
Test name
Test status
Simulation time 32111132 ps
CPU time 1.35 seconds
Started Jul 26 05:38:42 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 198384 kb
Host smart-56ab7ed6-c601-4f70-8ba0-ec8774bb9ee3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745467045 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1745467045
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1179013930
Short name T121
Test name
Test status
Simulation time 14226329 ps
CPU time 0.64 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 195268 kb
Host smart-97148b27-8a39-4b82-baf9-356d77c9cccc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179013930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1179013930
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1713965579
Short name T767
Test name
Test status
Simulation time 23462424 ps
CPU time 0.61 seconds
Started Jul 26 05:38:45 PM PDT 24
Finished Jul 26 05:38:45 PM PDT 24
Peak memory 194092 kb
Host smart-b65e82c6-e157-4b70-b395-2f212d4d4c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713965579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1713965579
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3455526152
Short name T114
Test name
Test status
Simulation time 56087381 ps
CPU time 0.72 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 196292 kb
Host smart-0afe1813-222c-4f19-9b22-62d3937cf90f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455526152 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3455526152
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.876458357
Short name T749
Test name
Test status
Simulation time 106460204 ps
CPU time 1.24 seconds
Started Jul 26 05:38:45 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 198404 kb
Host smart-64a3993c-e2a1-4f6a-9b07-5c7958860845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876458357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.876458357
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2772112922
Short name T44
Test name
Test status
Simulation time 79043061 ps
CPU time 1.15 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 198368 kb
Host smart-26a4452d-9b8f-46a2-ae53-48d8e18101ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772112922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2772112922
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3312929782
Short name T733
Test name
Test status
Simulation time 17021117 ps
CPU time 0.84 seconds
Started Jul 26 05:38:52 PM PDT 24
Finished Jul 26 05:38:53 PM PDT 24
Peak memory 198232 kb
Host smart-d028887a-a713-452f-9f87-4d63429fcbb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312929782 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3312929782
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2140327643
Short name T120
Test name
Test status
Simulation time 46264257 ps
CPU time 0.64 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 195172 kb
Host smart-fd94f32c-d6e9-49b1-9f02-594b7867fade
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140327643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2140327643
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2803516430
Short name T734
Test name
Test status
Simulation time 17739603 ps
CPU time 0.57 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 194076 kb
Host smart-760ef2d2-de98-4ba2-8477-d8ca43f94fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803516430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2803516430
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2290818391
Short name T111
Test name
Test status
Simulation time 120256005 ps
CPU time 0.71 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 196080 kb
Host smart-72c14c3a-5b70-4e10-bd84-5b22d3999a77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290818391 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2290818391
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3475458453
Short name T726
Test name
Test status
Simulation time 242469276 ps
CPU time 1.4 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 198404 kb
Host smart-c460c166-3c35-4ac9-8786-e0a1ba75742e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475458453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3475458453
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3315465104
Short name T53
Test name
Test status
Simulation time 163267163 ps
CPU time 0.87 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 198148 kb
Host smart-4917fab5-6819-4cbe-897b-33fe18499f53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315465104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3315465104
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4215189600
Short name T802
Test name
Test status
Simulation time 24757047 ps
CPU time 0.7 seconds
Started Jul 26 05:38:53 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 197160 kb
Host smart-710bcfe2-60d3-40a2-ae7a-430b3d4764ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215189600 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.4215189600
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2316748103
Short name T799
Test name
Test status
Simulation time 12560574 ps
CPU time 0.58 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 193956 kb
Host smart-b6a28baa-143b-4956-a7e0-36eb3fccd612
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316748103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2316748103
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3634073779
Short name T834
Test name
Test status
Simulation time 55152468 ps
CPU time 0.58 seconds
Started Jul 26 05:38:43 PM PDT 24
Finished Jul 26 05:38:44 PM PDT 24
Peak memory 194048 kb
Host smart-960cccbd-58df-4fd1-afc7-7c888fca129b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634073779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3634073779
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4026075200
Short name T95
Test name
Test status
Simulation time 51984407 ps
CPU time 0.67 seconds
Started Jul 26 05:38:52 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 195656 kb
Host smart-2f1c88b6-137d-4de5-9dab-caa8e7ad7e01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026075200 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4026075200
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.941070456
Short name T803
Test name
Test status
Simulation time 53842728 ps
CPU time 2.65 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:51 PM PDT 24
Peak memory 198368 kb
Host smart-0b459ffa-5ff5-4186-830d-6dc2e367e8f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941070456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.941070456
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1207761731
Short name T123
Test name
Test status
Simulation time 130668244 ps
CPU time 0.81 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 197552 kb
Host smart-6cd5ced4-3c97-4f16-b1e7-9e0b39bfa68c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207761731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1207761731
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3137219054
Short name T787
Test name
Test status
Simulation time 70036255 ps
CPU time 1.01 seconds
Started Jul 26 05:38:42 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 198220 kb
Host smart-f5c7f491-c1af-403c-87a2-186d610b5d78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137219054 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3137219054
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1243410863
Short name T108
Test name
Test status
Simulation time 33467538 ps
CPU time 0.61 seconds
Started Jul 26 05:38:44 PM PDT 24
Finished Jul 26 05:38:45 PM PDT 24
Peak memory 195444 kb
Host smart-6054743b-f5d2-4fbe-a659-304d3e7bd93b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243410863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1243410863
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.88074438
Short name T732
Test name
Test status
Simulation time 14589085 ps
CPU time 0.62 seconds
Started Jul 26 05:38:53 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 194028 kb
Host smart-70767c51-ad19-43a7-ada4-932331b1db39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88074438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.88074438
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2235576834
Short name T838
Test name
Test status
Simulation time 15035917 ps
CPU time 0.64 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 194984 kb
Host smart-996f87d0-a13d-46a9-9d35-48583f7289c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235576834 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2235576834
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2867939067
Short name T793
Test name
Test status
Simulation time 176033082 ps
CPU time 1.07 seconds
Started Jul 26 05:38:44 PM PDT 24
Finished Jul 26 05:38:45 PM PDT 24
Peak memory 198176 kb
Host smart-81e4a2fa-449e-41e3-be2f-89f69e19b56e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867939067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2867939067
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1790216266
Short name T845
Test name
Test status
Simulation time 149650328 ps
CPU time 0.92 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 197512 kb
Host smart-b4309501-ecde-441b-9c0e-a1498ba9630a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790216266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1790216266
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1469799369
Short name T813
Test name
Test status
Simulation time 174703308 ps
CPU time 1.25 seconds
Started Jul 26 05:38:52 PM PDT 24
Finished Jul 26 05:38:53 PM PDT 24
Peak memory 198412 kb
Host smart-0ad2591e-a05d-4017-8043-0bf6cc7f6f8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469799369 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1469799369
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2414994200
Short name T98
Test name
Test status
Simulation time 12086588 ps
CPU time 0.63 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 195268 kb
Host smart-57e4b92b-e736-4067-9b14-b35493582fdd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414994200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2414994200
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1231050513
Short name T829
Test name
Test status
Simulation time 23882238 ps
CPU time 0.64 seconds
Started Jul 26 05:38:52 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 194072 kb
Host smart-c4d65932-bb3a-448b-b8ad-a17d8fd44369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231050513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1231050513
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1588922635
Short name T118
Test name
Test status
Simulation time 17739685 ps
CPU time 0.61 seconds
Started Jul 26 05:38:44 PM PDT 24
Finished Jul 26 05:38:45 PM PDT 24
Peak memory 195308 kb
Host smart-dc992386-af28-4b6f-a873-dfb5fabfffea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588922635 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1588922635
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4290645689
Short name T766
Test name
Test status
Simulation time 42397286 ps
CPU time 2.24 seconds
Started Jul 26 05:38:52 PM PDT 24
Finished Jul 26 05:38:55 PM PDT 24
Peak memory 198384 kb
Host smart-eb5cfb9f-ad00-4687-9883-eefe01d86300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290645689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4290645689
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.740823791
Short name T55
Test name
Test status
Simulation time 86751781 ps
CPU time 1.15 seconds
Started Jul 26 05:38:52 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 198340 kb
Host smart-f594164b-e922-4c6e-8a16-52191fa53ace
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740823791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.740823791
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1831650581
Short name T805
Test name
Test status
Simulation time 27189258 ps
CPU time 0.82 seconds
Started Jul 26 05:38:53 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 198256 kb
Host smart-2c295ac5-7241-4762-a0ea-bf9425f17f4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831650581 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1831650581
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3349487264
Short name T99
Test name
Test status
Simulation time 29457642 ps
CPU time 0.62 seconds
Started Jul 26 05:38:52 PM PDT 24
Finished Jul 26 05:38:52 PM PDT 24
Peak memory 195892 kb
Host smart-ddc66503-8e60-45a0-be82-38b77673474a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349487264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3349487264
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2121975401
Short name T761
Test name
Test status
Simulation time 56427134 ps
CPU time 0.58 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 194088 kb
Host smart-3c9a4ae1-11f6-402f-b881-3de2bda4092a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121975401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2121975401
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.606804785
Short name T115
Test name
Test status
Simulation time 20209824 ps
CPU time 0.68 seconds
Started Jul 26 05:38:54 PM PDT 24
Finished Jul 26 05:38:55 PM PDT 24
Peak memory 195020 kb
Host smart-2e4e1f5d-59dd-4905-9208-fafea16d359c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606804785 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.606804785
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4092692299
Short name T772
Test name
Test status
Simulation time 18671784 ps
CPU time 0.95 seconds
Started Jul 26 05:38:53 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 198212 kb
Host smart-5ef80c88-8c5f-4de4-bcd1-a9233298ace1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092692299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.4092692299
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.260641308
Short name T51
Test name
Test status
Simulation time 520612780 ps
CPU time 1.43 seconds
Started Jul 26 05:38:45 PM PDT 24
Finished Jul 26 05:38:46 PM PDT 24
Peak memory 198376 kb
Host smart-71780b63-5746-47fd-9f75-813493c3448b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260641308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.260641308
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.364731104
Short name T792
Test name
Test status
Simulation time 36316727 ps
CPU time 0.72 seconds
Started Jul 26 05:38:55 PM PDT 24
Finished Jul 26 05:38:56 PM PDT 24
Peak memory 197812 kb
Host smart-23ed85da-6fe3-466a-b993-c86826d42102
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364731104 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.364731104
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1333207359
Short name T791
Test name
Test status
Simulation time 22220235 ps
CPU time 0.6 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 194960 kb
Host smart-fbd3c623-3138-4630-acb5-806531c3bdf1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333207359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1333207359
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2572198417
Short name T744
Test name
Test status
Simulation time 39688484 ps
CPU time 0.59 seconds
Started Jul 26 05:38:59 PM PDT 24
Finished Jul 26 05:39:00 PM PDT 24
Peak memory 193968 kb
Host smart-bc7ee259-0acc-41aa-ab6c-58fc0013d25a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572198417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2572198417
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2433134723
Short name T112
Test name
Test status
Simulation time 69549805 ps
CPU time 0.85 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 196528 kb
Host smart-1dfdea72-246c-4af4-a566-9523d1c906d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433134723 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2433134723
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3058994361
Short name T770
Test name
Test status
Simulation time 106109044 ps
CPU time 1.34 seconds
Started Jul 26 05:38:51 PM PDT 24
Finished Jul 26 05:38:52 PM PDT 24
Peak memory 198360 kb
Host smart-5a70e26d-a37c-4ee3-80df-c030b095f8c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058994361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3058994361
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.688340853
Short name T750
Test name
Test status
Simulation time 197667391 ps
CPU time 1.03 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 198212 kb
Host smart-3f8ac5cd-86d2-437d-bce7-bef644d4b602
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688340853 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.688340853
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2403120060
Short name T746
Test name
Test status
Simulation time 14795527 ps
CPU time 0.58 seconds
Started Jul 26 05:38:51 PM PDT 24
Finished Jul 26 05:38:52 PM PDT 24
Peak memory 193640 kb
Host smart-fe62ed59-085f-4a7a-8d45-494b39831fd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403120060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2403120060
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3424587079
Short name T780
Test name
Test status
Simulation time 35918101 ps
CPU time 0.58 seconds
Started Jul 26 05:38:54 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 194076 kb
Host smart-399a831a-3049-4edd-b226-d5ac602a6ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424587079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3424587079
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2156469765
Short name T831
Test name
Test status
Simulation time 193865406 ps
CPU time 0.76 seconds
Started Jul 26 05:38:56 PM PDT 24
Finished Jul 26 05:38:57 PM PDT 24
Peak memory 196224 kb
Host smart-8f0e9274-d3b9-42bc-a44e-dc9ef2b19059
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156469765 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2156469765
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1748829619
Short name T788
Test name
Test status
Simulation time 41127233 ps
CPU time 2.24 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:52 PM PDT 24
Peak memory 198592 kb
Host smart-b42f6a87-84d1-4185-a362-97b2fb2efc27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748829619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1748829619
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2884632742
Short name T758
Test name
Test status
Simulation time 32479568 ps
CPU time 0.84 seconds
Started Jul 26 05:38:57 PM PDT 24
Finished Jul 26 05:38:57 PM PDT 24
Peak memory 198196 kb
Host smart-70bbf2ce-3403-4788-b153-53982f3cf2cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884632742 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2884632742
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1533501840
Short name T109
Test name
Test status
Simulation time 60546564 ps
CPU time 0.56 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 193896 kb
Host smart-d7a036b6-6f1c-480e-b6db-893265213dd1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533501840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1533501840
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1114230363
Short name T810
Test name
Test status
Simulation time 36361411 ps
CPU time 0.59 seconds
Started Jul 26 05:38:59 PM PDT 24
Finished Jul 26 05:39:00 PM PDT 24
Peak memory 194692 kb
Host smart-8c7c5209-b58b-4b27-8223-5d6fc142658c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114230363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1114230363
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.527917639
Short name T844
Test name
Test status
Simulation time 66961458 ps
CPU time 0.84 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 196336 kb
Host smart-d1b0d5f5-1df4-4e56-bebb-763fb74df4cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527917639 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.527917639
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2208207578
Short name T800
Test name
Test status
Simulation time 124071684 ps
CPU time 2.63 seconds
Started Jul 26 05:38:57 PM PDT 24
Finished Jul 26 05:38:59 PM PDT 24
Peak memory 198348 kb
Host smart-90a5362e-abbf-4ec8-afcc-fc48dd7b4c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208207578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2208207578
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1293678574
Short name T794
Test name
Test status
Simulation time 251852006 ps
CPU time 1.1 seconds
Started Jul 26 05:38:54 PM PDT 24
Finished Jul 26 05:38:55 PM PDT 24
Peak memory 198360 kb
Host smart-8c74250b-06d1-4b2b-a304-c257b941f5b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293678574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1293678574
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3377614136
Short name T729
Test name
Test status
Simulation time 39511169 ps
CPU time 1.8 seconds
Started Jul 26 05:38:59 PM PDT 24
Finished Jul 26 05:39:00 PM PDT 24
Peak memory 198420 kb
Host smart-8679bc9e-cc25-487d-97ae-953043866895
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377614136 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3377614136
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2524052460
Short name T752
Test name
Test status
Simulation time 50289682 ps
CPU time 0.6 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 195136 kb
Host smart-3d19ca56-0cc8-4132-9afa-8d45e8fe6a78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524052460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2524052460
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1376283449
Short name T808
Test name
Test status
Simulation time 14709193 ps
CPU time 0.6 seconds
Started Jul 26 05:38:51 PM PDT 24
Finished Jul 26 05:38:52 PM PDT 24
Peak memory 194732 kb
Host smart-d9141f8f-cef0-4612-81f1-e790db6da275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376283449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1376283449
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2747429578
Short name T820
Test name
Test status
Simulation time 17232847 ps
CPU time 0.76 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 196380 kb
Host smart-6c7ea4e6-1698-4721-8815-0414bd6b00e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747429578 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2747429578
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3913411226
Short name T781
Test name
Test status
Simulation time 150133659 ps
CPU time 2.2 seconds
Started Jul 26 05:38:56 PM PDT 24
Finished Jul 26 05:38:59 PM PDT 24
Peak memory 198416 kb
Host smart-071e8625-cef5-4207-a44f-e682dbfaa7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913411226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3913411226
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3630250653
Short name T43
Test name
Test status
Simulation time 52112582 ps
CPU time 0.89 seconds
Started Jul 26 05:38:57 PM PDT 24
Finished Jul 26 05:38:58 PM PDT 24
Peak memory 198108 kb
Host smart-695527b5-2a24-40c1-90f6-784960fd8066
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630250653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3630250653
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3471557251
Short name T106
Test name
Test status
Simulation time 17245999 ps
CPU time 0.73 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 195968 kb
Host smart-71728cd3-6f7d-4c5b-a445-df476b45e96e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471557251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3471557251
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1129593655
Short name T747
Test name
Test status
Simulation time 326115599 ps
CPU time 3.47 seconds
Started Jul 26 05:38:51 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 198328 kb
Host smart-c81f798e-44ad-4f63-ba97-1ef84037f457
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129593655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1129593655
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.690986707
Short name T102
Test name
Test status
Simulation time 21953014 ps
CPU time 0.61 seconds
Started Jul 26 05:38:45 PM PDT 24
Finished Jul 26 05:38:46 PM PDT 24
Peak memory 194844 kb
Host smart-714e9d1f-3962-4a7d-9201-4405e8b29076
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690986707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.690986707
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3910765691
Short name T751
Test name
Test status
Simulation time 25128253 ps
CPU time 0.85 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 198264 kb
Host smart-5cd77bd7-7085-4c6b-b615-0d2e78e72636
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910765691 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3910765691
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.346865914
Short name T753
Test name
Test status
Simulation time 12883406 ps
CPU time 0.67 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 195068 kb
Host smart-7773c2d8-451c-43a8-96ea-c1b98287a2e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346865914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.346865914
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.352592551
Short name T771
Test name
Test status
Simulation time 11768069 ps
CPU time 0.57 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 193996 kb
Host smart-4375adad-6866-4c90-a719-116df3869031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352592551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.352592551
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2563660267
Short name T113
Test name
Test status
Simulation time 50591043 ps
CPU time 0.67 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 194844 kb
Host smart-874dadc4-22e6-4bda-bafa-2ff2c393fa4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563660267 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2563660267
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3165739465
Short name T789
Test name
Test status
Simulation time 235385075 ps
CPU time 1.33 seconds
Started Jul 26 05:38:51 PM PDT 24
Finished Jul 26 05:38:52 PM PDT 24
Peak memory 198348 kb
Host smart-b3eea1fb-556c-4506-8c83-eeceb1474607
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165739465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3165739465
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.561894234
Short name T728
Test name
Test status
Simulation time 17423565 ps
CPU time 0.58 seconds
Started Jul 26 05:38:50 PM PDT 24
Finished Jul 26 05:38:51 PM PDT 24
Peak memory 194044 kb
Host smart-646518a9-048d-4027-bbf3-434aa25b3da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561894234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.561894234
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3390691872
Short name T756
Test name
Test status
Simulation time 16417966 ps
CPU time 0.6 seconds
Started Jul 26 05:38:57 PM PDT 24
Finished Jul 26 05:38:57 PM PDT 24
Peak memory 194172 kb
Host smart-023e7810-5768-4d0d-a2f6-01fcb52e958a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390691872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3390691872
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4214048609
Short name T773
Test name
Test status
Simulation time 16179307 ps
CPU time 0.63 seconds
Started Jul 26 05:38:54 PM PDT 24
Finished Jul 26 05:38:55 PM PDT 24
Peak memory 194732 kb
Host smart-add7d188-13a4-4e86-9bcf-35f6333bd7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214048609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4214048609
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2716824632
Short name T825
Test name
Test status
Simulation time 37001096 ps
CPU time 0.59 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 194060 kb
Host smart-a0782bc9-3d45-4fbd-b234-8fb0dce2990c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716824632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2716824632
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3223924253
Short name T755
Test name
Test status
Simulation time 44366155 ps
CPU time 0.61 seconds
Started Jul 26 05:38:58 PM PDT 24
Finished Jul 26 05:38:59 PM PDT 24
Peak memory 194656 kb
Host smart-38ca81b8-96fe-40f4-bef8-a43ee01416ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223924253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3223924253
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3231454824
Short name T782
Test name
Test status
Simulation time 27797385 ps
CPU time 0.58 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 194700 kb
Host smart-004d1721-a03a-4dc9-8fcf-ee3bd7d9a65b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231454824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3231454824
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3749380926
Short name T762
Test name
Test status
Simulation time 11648041 ps
CPU time 0.63 seconds
Started Jul 26 05:38:54 PM PDT 24
Finished Jul 26 05:38:55 PM PDT 24
Peak memory 194632 kb
Host smart-be90eb72-db66-43d5-b15d-3b0feb746a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749380926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3749380926
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3789540876
Short name T822
Test name
Test status
Simulation time 77092443 ps
CPU time 0.59 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 194752 kb
Host smart-2e8a4aa2-8cb4-475c-a523-9855e4d4219e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789540876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3789540876
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3266209643
Short name T748
Test name
Test status
Simulation time 14178973 ps
CPU time 0.56 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 193636 kb
Host smart-95ae05f8-6ae7-4c87-9837-af8acd3bf763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266209643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3266209643
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2623801927
Short name T824
Test name
Test status
Simulation time 20236619 ps
CPU time 0.64 seconds
Started Jul 26 05:38:55 PM PDT 24
Finished Jul 26 05:38:56 PM PDT 24
Peak memory 194080 kb
Host smart-4058af3f-1bcd-48e3-930a-a303d8e33db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623801927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2623801927
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2012115967
Short name T815
Test name
Test status
Simulation time 288894311 ps
CPU time 0.85 seconds
Started Jul 26 05:38:51 PM PDT 24
Finished Jul 26 05:38:52 PM PDT 24
Peak memory 196276 kb
Host smart-344d83e5-ef0e-4406-a38f-4e7d574eb8a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012115967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2012115967
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.765313102
Short name T778
Test name
Test status
Simulation time 1492868545 ps
CPU time 3.38 seconds
Started Jul 26 05:38:50 PM PDT 24
Finished Jul 26 05:38:54 PM PDT 24
Peak memory 197480 kb
Host smart-19744e59-2549-4a6f-89bc-63e869c3e605
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765313102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.765313102
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1072983819
Short name T769
Test name
Test status
Simulation time 18850631 ps
CPU time 0.61 seconds
Started Jul 26 05:38:43 PM PDT 24
Finished Jul 26 05:38:44 PM PDT 24
Peak memory 195852 kb
Host smart-f8b4437b-da41-4d4a-8a43-85e68ea63764
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072983819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1072983819
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3113576397
Short name T730
Test name
Test status
Simulation time 79315501 ps
CPU time 0.77 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 198180 kb
Host smart-5143a2fe-1e6c-4f4d-8bc2-616d3e673360
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113576397 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3113576397
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1887627890
Short name T104
Test name
Test status
Simulation time 28090614 ps
CPU time 0.61 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 195268 kb
Host smart-3044f3ff-6816-42cb-a60a-15a14f797ccf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887627890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1887627890
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3870697591
Short name T801
Test name
Test status
Simulation time 21512575 ps
CPU time 0.62 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 194628 kb
Host smart-2001acf6-0aea-4334-bf90-33bf328dcd5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870697591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3870697591
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1287049483
Short name T117
Test name
Test status
Simulation time 60189801 ps
CPU time 0.75 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 196316 kb
Host smart-c6bce28c-8a25-41d3-a08a-901e5ead34ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287049483 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1287049483
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2048689286
Short name T740
Test name
Test status
Simulation time 69927151 ps
CPU time 1.36 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 198344 kb
Host smart-5687a27d-5d81-4ac8-8be0-ae7988bd8225
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048689286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2048689286
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1233564847
Short name T50
Test name
Test status
Simulation time 535964554 ps
CPU time 1.31 seconds
Started Jul 26 05:38:43 PM PDT 24
Finished Jul 26 05:38:45 PM PDT 24
Peak memory 198308 kb
Host smart-312f6569-cf3e-4201-b117-7241ce601565
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233564847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1233564847
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1667612190
Short name T798
Test name
Test status
Simulation time 41912957 ps
CPU time 0.6 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 194160 kb
Host smart-9c25edf0-70a8-4e59-ad72-7400c93ccc97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667612190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1667612190
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.537640799
Short name T828
Test name
Test status
Simulation time 10649933 ps
CPU time 0.61 seconds
Started Jul 26 05:38:58 PM PDT 24
Finished Jul 26 05:38:59 PM PDT 24
Peak memory 193976 kb
Host smart-b6b665d8-50c1-41bf-a20d-31d45b422a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537640799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.537640799
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2303502727
Short name T738
Test name
Test status
Simulation time 43870165 ps
CPU time 0.57 seconds
Started Jul 26 05:38:55 PM PDT 24
Finished Jul 26 05:38:55 PM PDT 24
Peak memory 194680 kb
Host smart-384a68e6-853d-4128-b4ab-6fa920e1e752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303502727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2303502727
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2142388267
Short name T785
Test name
Test status
Simulation time 14743507 ps
CPU time 0.6 seconds
Started Jul 26 05:38:54 PM PDT 24
Finished Jul 26 05:38:55 PM PDT 24
Peak memory 194736 kb
Host smart-470c1474-f39a-4cea-87e2-68c0a4eb64f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142388267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2142388267
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3897114752
Short name T804
Test name
Test status
Simulation time 18550729 ps
CPU time 0.57 seconds
Started Jul 26 05:38:55 PM PDT 24
Finished Jul 26 05:38:55 PM PDT 24
Peak memory 194640 kb
Host smart-53c4ffa0-8d7c-4bd5-ab3c-01c7f09b1aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897114752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3897114752
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.634766445
Short name T754
Test name
Test status
Simulation time 13068293 ps
CPU time 0.58 seconds
Started Jul 26 05:39:06 PM PDT 24
Finished Jul 26 05:39:07 PM PDT 24
Peak memory 194636 kb
Host smart-3ced9473-e943-423e-a77d-331feb40ae5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634766445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.634766445
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3144006017
Short name T823
Test name
Test status
Simulation time 22207709 ps
CPU time 0.55 seconds
Started Jul 26 05:38:59 PM PDT 24
Finished Jul 26 05:39:00 PM PDT 24
Peak memory 193960 kb
Host smart-5602d408-b310-4058-8a21-fcd4d7e468b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144006017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3144006017
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2459588134
Short name T812
Test name
Test status
Simulation time 38061325 ps
CPU time 0.59 seconds
Started Jul 26 05:38:50 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 194176 kb
Host smart-a7fc13e2-3b7a-429a-8680-d8643c782a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459588134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2459588134
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.22813435
Short name T777
Test name
Test status
Simulation time 12977005 ps
CPU time 0.58 seconds
Started Jul 26 05:39:01 PM PDT 24
Finished Jul 26 05:39:02 PM PDT 24
Peak memory 193932 kb
Host smart-0f467d3f-5f13-4356-a9c4-7314aad6153e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22813435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.22813435
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.873038657
Short name T841
Test name
Test status
Simulation time 15869694 ps
CPU time 0.63 seconds
Started Jul 26 05:38:58 PM PDT 24
Finished Jul 26 05:38:59 PM PDT 24
Peak memory 194720 kb
Host smart-0b9fa97c-13e7-40b5-bb72-5582d931752e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873038657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.873038657
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.4143304613
Short name T101
Test name
Test status
Simulation time 32687324 ps
CPU time 0.7 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 195424 kb
Host smart-b89cafe9-b21f-49ee-9a73-4e8192ae7884
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143304613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.4143304613
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.952300019
Short name T817
Test name
Test status
Simulation time 394845055 ps
CPU time 3.27 seconds
Started Jul 26 05:38:50 PM PDT 24
Finished Jul 26 05:38:53 PM PDT 24
Peak memory 197220 kb
Host smart-398c2367-77cc-4a17-8ea2-bdc36d140948
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952300019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.952300019
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.139910651
Short name T843
Test name
Test status
Simulation time 15268386 ps
CPU time 0.65 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 195120 kb
Host smart-c0cd1d79-1032-4232-bd9f-3164f2db4b6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139910651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.139910651
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1437840213
Short name T846
Test name
Test status
Simulation time 17710663 ps
CPU time 0.92 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 198180 kb
Host smart-5a1d318b-7c8b-4f3f-9ee9-bd269e6fc052
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437840213 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1437840213
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2678707246
Short name T110
Test name
Test status
Simulation time 16375263 ps
CPU time 0.59 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 195860 kb
Host smart-91216d02-aeb5-4ef3-9de3-35b9a983cb3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678707246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2678707246
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3158610967
Short name T797
Test name
Test status
Simulation time 14033859 ps
CPU time 0.59 seconds
Started Jul 26 05:38:46 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 194012 kb
Host smart-7e841a91-e9bc-4b5d-a7a8-7811eea0976d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158610967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3158610967
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1728149163
Short name T835
Test name
Test status
Simulation time 48985781 ps
CPU time 0.7 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 195128 kb
Host smart-c15f32eb-bcc5-47a0-a100-2b58b4ceeafb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728149163 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1728149163
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.117002269
Short name T759
Test name
Test status
Simulation time 221396723 ps
CPU time 1.97 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:51 PM PDT 24
Peak memory 198368 kb
Host smart-3619e0a5-dd0b-4b41-9516-770ef235e830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117002269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.117002269
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2010733155
Short name T52
Test name
Test status
Simulation time 241746081 ps
CPU time 1.13 seconds
Started Jul 26 05:38:50 PM PDT 24
Finished Jul 26 05:38:52 PM PDT 24
Peak memory 198320 kb
Host smart-5e27af43-343d-4092-90a7-69b4c4969b8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010733155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2010733155
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1681521622
Short name T819
Test name
Test status
Simulation time 43160084 ps
CPU time 0.58 seconds
Started Jul 26 05:39:06 PM PDT 24
Finished Jul 26 05:39:07 PM PDT 24
Peak memory 194604 kb
Host smart-598262b8-e58b-401b-a4e5-1185cd9e691a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681521622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1681521622
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3307296624
Short name T836
Test name
Test status
Simulation time 32627435 ps
CPU time 0.64 seconds
Started Jul 26 05:38:58 PM PDT 24
Finished Jul 26 05:38:59 PM PDT 24
Peak memory 194032 kb
Host smart-4fcfec95-fb21-4102-9f1d-782c8708d4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307296624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3307296624
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2051305673
Short name T736
Test name
Test status
Simulation time 14761228 ps
CPU time 0.59 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 193924 kb
Host smart-92aadc58-66eb-4caa-9964-4f1bb43b368b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051305673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2051305673
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1627602482
Short name T826
Test name
Test status
Simulation time 36216496 ps
CPU time 0.58 seconds
Started Jul 26 05:38:58 PM PDT 24
Finished Jul 26 05:38:59 PM PDT 24
Peak memory 194608 kb
Host smart-ad9f88d7-fc5a-4c28-9826-7d48440b7582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627602482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1627602482
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1876094236
Short name T790
Test name
Test status
Simulation time 105175228 ps
CPU time 0.58 seconds
Started Jul 26 05:39:06 PM PDT 24
Finished Jul 26 05:39:07 PM PDT 24
Peak memory 193976 kb
Host smart-22b9a3ba-7477-4184-8e48-78411970ddce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876094236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1876094236
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2009132892
Short name T796
Test name
Test status
Simulation time 30606788 ps
CPU time 0.58 seconds
Started Jul 26 05:38:49 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 194688 kb
Host smart-9ec9884e-4398-4c23-abd8-bfaafe2db0d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009132892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2009132892
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3572874533
Short name T795
Test name
Test status
Simulation time 12055969 ps
CPU time 0.58 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 194248 kb
Host smart-704220f4-fc43-4485-8cf3-45fa49158df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572874533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3572874533
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3246967250
Short name T742
Test name
Test status
Simulation time 41605046 ps
CPU time 0.6 seconds
Started Jul 26 05:38:59 PM PDT 24
Finished Jul 26 05:39:00 PM PDT 24
Peak memory 194056 kb
Host smart-f868563c-f3c7-4483-b817-f82745cfcf92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246967250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3246967250
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.937292289
Short name T807
Test name
Test status
Simulation time 51062162 ps
CPU time 0.6 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 194748 kb
Host smart-3e9d6a3a-e6b2-41c2-9d1e-04e83675721d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937292289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.937292289
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.992899356
Short name T739
Test name
Test status
Simulation time 34077180 ps
CPU time 0.59 seconds
Started Jul 26 05:39:03 PM PDT 24
Finished Jul 26 05:39:04 PM PDT 24
Peak memory 194584 kb
Host smart-d301fa52-f033-47e4-818f-4be43fb8d220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992899356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.992899356
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.49505912
Short name T743
Test name
Test status
Simulation time 47415479 ps
CPU time 0.8 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 198208 kb
Host smart-0d1fcc96-b5e8-4be3-b981-f77e7ad68f64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49505912 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.49505912
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2569688125
Short name T105
Test name
Test status
Simulation time 30798718 ps
CPU time 0.64 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 195736 kb
Host smart-c1edfcc4-5b5b-4bc9-85d7-05e94ce9145b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569688125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2569688125
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.930153980
Short name T830
Test name
Test status
Simulation time 20632717 ps
CPU time 0.57 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 193996 kb
Host smart-ca86a7cd-0605-4a77-b107-732181bdbaea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930153980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.930153980
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2345309298
Short name T840
Test name
Test status
Simulation time 70160004 ps
CPU time 0.83 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 196508 kb
Host smart-fad517eb-42e1-44d6-b139-4f0b94c7f575
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345309298 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2345309298
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3831587137
Short name T774
Test name
Test status
Simulation time 101503831 ps
CPU time 2.71 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:52 PM PDT 24
Peak memory 198408 kb
Host smart-961409a2-afed-4ed9-9270-b5eeb02e4098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831587137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3831587137
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.507481410
Short name T54
Test name
Test status
Simulation time 129082614 ps
CPU time 1.47 seconds
Started Jul 26 05:38:46 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 198344 kb
Host smart-01d6accd-3ddd-4292-a551-03c667e20158
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507481410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.507481410
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1799969050
Short name T784
Test name
Test status
Simulation time 32016635 ps
CPU time 0.81 seconds
Started Jul 26 05:38:46 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 198228 kb
Host smart-06dbfe02-e6df-49d6-b45e-26a2689f06fd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799969050 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1799969050
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1095545380
Short name T786
Test name
Test status
Simulation time 15124899 ps
CPU time 0.63 seconds
Started Jul 26 05:38:46 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 195800 kb
Host smart-3dc92e49-5f25-4607-9049-f15b52c1acdb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095545380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1095545380
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1553257432
Short name T821
Test name
Test status
Simulation time 13189379 ps
CPU time 0.57 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 193996 kb
Host smart-f9bced81-eaee-4a6a-a9dd-13adfd33c12a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553257432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1553257432
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3494470005
Short name T832
Test name
Test status
Simulation time 17352322 ps
CPU time 0.7 seconds
Started Jul 26 05:38:44 PM PDT 24
Finished Jul 26 05:38:45 PM PDT 24
Peak memory 195188 kb
Host smart-344f59b1-3565-4e81-acf4-04fbfd89b6aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494470005 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3494470005
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3290154669
Short name T847
Test name
Test status
Simulation time 109791049 ps
CPU time 1.67 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 198368 kb
Host smart-ab5084ac-daac-461a-9467-98c00dc2ed4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290154669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3290154669
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1937269011
Short name T757
Test name
Test status
Simulation time 76671919 ps
CPU time 0.89 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 197560 kb
Host smart-74a10e14-0b33-40b6-b427-08fcb0c886ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937269011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1937269011
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3802249599
Short name T765
Test name
Test status
Simulation time 24995995 ps
CPU time 0.65 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 196616 kb
Host smart-25b8696a-bd5b-4b85-a7a2-5fcdeb55c9e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802249599 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3802249599
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2484599244
Short name T100
Test name
Test status
Simulation time 45478480 ps
CPU time 0.6 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 195020 kb
Host smart-575d35b2-d5b1-424f-a6ab-9b15e2ce75af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484599244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2484599244
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3997035118
Short name T811
Test name
Test status
Simulation time 16387354 ps
CPU time 0.63 seconds
Started Jul 26 05:38:41 PM PDT 24
Finished Jul 26 05:38:42 PM PDT 24
Peak memory 194096 kb
Host smart-a827ac68-bde5-4450-9683-34b60d7fe22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997035118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3997035118
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1084694940
Short name T848
Test name
Test status
Simulation time 16144638 ps
CPU time 0.62 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 194920 kb
Host smart-ff9d219c-c07d-43cd-ba12-13f68d249fd0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084694940 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1084694940
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.290732487
Short name T833
Test name
Test status
Simulation time 23117834 ps
CPU time 1.18 seconds
Started Jul 26 05:38:46 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 198376 kb
Host smart-e41374f3-6e1c-45b1-9f91-3a37c92adb6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290732487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.290732487
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3648457017
Short name T818
Test name
Test status
Simulation time 157394071 ps
CPU time 1.16 seconds
Started Jul 26 05:38:42 PM PDT 24
Finished Jul 26 05:38:43 PM PDT 24
Peak memory 198420 kb
Host smart-80b1d0a9-aee7-40e9-ae9b-e6b0facfddb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648457017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3648457017
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2461040695
Short name T737
Test name
Test status
Simulation time 91275268 ps
CPU time 0.83 seconds
Started Jul 26 05:38:40 PM PDT 24
Finished Jul 26 05:38:41 PM PDT 24
Peak memory 198192 kb
Host smart-e07c280d-a8d5-4ec8-91d3-d4141c2aec9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461040695 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2461040695
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1243183892
Short name T816
Test name
Test status
Simulation time 16457389 ps
CPU time 0.58 seconds
Started Jul 26 05:38:47 PM PDT 24
Finished Jul 26 05:38:48 PM PDT 24
Peak memory 194624 kb
Host smart-6ada526f-8714-42db-86ba-39e506f16de8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243183892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1243183892
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1163645561
Short name T727
Test name
Test status
Simulation time 14440045 ps
CPU time 0.63 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 193964 kb
Host smart-84163e64-0622-458a-848d-672c105cbba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163645561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1163645561
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.779562425
Short name T827
Test name
Test status
Simulation time 13629664 ps
CPU time 0.67 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 195888 kb
Host smart-99e99e83-243c-4fd5-89a6-2f8605d80f1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779562425 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.779562425
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2967640199
Short name T745
Test name
Test status
Simulation time 112851373 ps
CPU time 2.8 seconds
Started Jul 26 05:38:43 PM PDT 24
Finished Jul 26 05:38:46 PM PDT 24
Peak memory 198348 kb
Host smart-718fd088-fed2-4f3e-a871-ba2f47a52738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967640199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2967640199
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2206489514
Short name T56
Test name
Test status
Simulation time 601659541 ps
CPU time 1.35 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:50 PM PDT 24
Peak memory 198272 kb
Host smart-6fb1b51f-a7a1-45c6-b835-56a627ce1210
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206489514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2206489514
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1809816326
Short name T764
Test name
Test status
Simulation time 81354465 ps
CPU time 1.11 seconds
Started Jul 26 05:38:44 PM PDT 24
Finished Jul 26 05:38:45 PM PDT 24
Peak memory 198356 kb
Host smart-278a4cd2-e54c-4463-9802-9f02f9ab061c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809816326 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1809816326
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3132409540
Short name T94
Test name
Test status
Simulation time 18074279 ps
CPU time 0.62 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 195056 kb
Host smart-ecae0265-083e-40ea-b269-29762a180eda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132409540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3132409540
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.765014678
Short name T741
Test name
Test status
Simulation time 38852790 ps
CPU time 0.59 seconds
Started Jul 26 05:38:46 PM PDT 24
Finished Jul 26 05:38:47 PM PDT 24
Peak memory 194100 kb
Host smart-5e28fb63-1da0-4e8a-9e89-e926aff588e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765014678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.765014678
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2162541617
Short name T116
Test name
Test status
Simulation time 33708465 ps
CPU time 0.63 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 194572 kb
Host smart-2945c29b-b5d8-495c-8dfe-0c06beb50f53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162541617 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2162541617
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3537401830
Short name T783
Test name
Test status
Simulation time 121727847 ps
CPU time 1.31 seconds
Started Jul 26 05:38:42 PM PDT 24
Finished Jul 26 05:38:44 PM PDT 24
Peak memory 198392 kb
Host smart-d13cb031-d085-4dc7-9054-1b5311edd902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537401830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3537401830
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.971546420
Short name T779
Test name
Test status
Simulation time 334345828 ps
CPU time 1.23 seconds
Started Jul 26 05:38:48 PM PDT 24
Finished Jul 26 05:38:49 PM PDT 24
Peak memory 198356 kb
Host smart-5c5eb764-0dd9-4931-9715-11a5efd0cfbc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971546420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.971546420
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3115239039
Short name T597
Test name
Test status
Simulation time 19614476 ps
CPU time 0.57 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 195100 kb
Host smart-0a18e816-955c-452b-93d7-b51eeeba66f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115239039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3115239039
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.66527746
Short name T435
Test name
Test status
Simulation time 22743335 ps
CPU time 0.72 seconds
Started Jul 26 05:39:22 PM PDT 24
Finished Jul 26 05:39:23 PM PDT 24
Peak memory 195508 kb
Host smart-bf93c5ee-8d00-4904-9b8d-7e6755d91779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66527746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.66527746
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2915125308
Short name T537
Test name
Test status
Simulation time 6124296127 ps
CPU time 19.45 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 197512 kb
Host smart-6684c4b9-3677-405d-abf3-467fa93addbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915125308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2915125308
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1923929426
Short name T513
Test name
Test status
Simulation time 943622165 ps
CPU time 0.89 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 197424 kb
Host smart-c4c1f801-43a4-40d6-aa9e-e755d836880e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923929426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1923929426
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1551282757
Short name T172
Test name
Test status
Simulation time 80125981 ps
CPU time 0.71 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 195612 kb
Host smart-1b09577a-cc7f-43b0-a344-bfa9239fa69d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551282757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1551282757
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1698122859
Short name T227
Test name
Test status
Simulation time 44242813 ps
CPU time 1.03 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:24 PM PDT 24
Peak memory 197668 kb
Host smart-ff0e7a46-74a2-4cbd-a8be-b248ade1f7cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698122859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1698122859
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.324620260
Short name T232
Test name
Test status
Simulation time 99251075 ps
CPU time 1.65 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 196368 kb
Host smart-af005681-3053-4ef8-90b1-60be4eecc054
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324620260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.324620260
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2964299929
Short name T336
Test name
Test status
Simulation time 63297972 ps
CPU time 1.24 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 196300 kb
Host smart-9b1d8c1d-b79f-473b-8b21-c56b04fdfd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964299929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2964299929
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.427411497
Short name T576
Test name
Test status
Simulation time 54434786 ps
CPU time 0.69 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 194816 kb
Host smart-bf4be66a-a90a-4697-8f69-c77a7540df43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427411497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.427411497
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3882715032
Short name T254
Test name
Test status
Simulation time 265998172 ps
CPU time 3.11 seconds
Started Jul 26 05:39:29 PM PDT 24
Finished Jul 26 05:39:33 PM PDT 24
Peak memory 198424 kb
Host smart-19f4a283-d4ed-4c49-bddf-c5dbb3fdcec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882715032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3882715032
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.343628661
Short name T46
Test name
Test status
Simulation time 277757363 ps
CPU time 1.01 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 215536 kb
Host smart-dbd81b88-e1c5-46fd-b399-79e91132aca5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343628661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.343628661
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.502898157
Short name T34
Test name
Test status
Simulation time 331540522 ps
CPU time 1.48 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 198504 kb
Host smart-cd1bef0d-5403-460f-9d2f-671264efbfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502898157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.502898157
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.203377650
Short name T355
Test name
Test status
Simulation time 150972218 ps
CPU time 1.27 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:24 PM PDT 24
Peak memory 197200 kb
Host smart-247dbcc1-285a-415b-ac56-52c188cdaa22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203377650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.203377650
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.350253967
Short name T602
Test name
Test status
Simulation time 11803524818 ps
CPU time 105.47 seconds
Started Jul 26 05:39:24 PM PDT 24
Finished Jul 26 05:41:10 PM PDT 24
Peak memory 198548 kb
Host smart-73aa4c2a-bc31-44af-8967-ea5bb5db515e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350253967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.350253967
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.854893425
Short name T584
Test name
Test status
Simulation time 334932504594 ps
CPU time 2172 seconds
Started Jul 26 05:39:28 PM PDT 24
Finished Jul 26 06:15:41 PM PDT 24
Peak memory 198632 kb
Host smart-6b94ba81-cdd5-425a-9d42-dae337ba335f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=854893425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.854893425
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3950462870
Short name T569
Test name
Test status
Simulation time 54491359 ps
CPU time 0.55 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 194476 kb
Host smart-cbdfce0c-1fe8-4b99-ba16-74cb77fc300a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950462870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3950462870
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3247525338
Short name T422
Test name
Test status
Simulation time 24571123 ps
CPU time 0.85 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 196908 kb
Host smart-05835b2c-a926-4f27-8923-6bf9efe6f28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247525338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3247525338
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3141412504
Short name T643
Test name
Test status
Simulation time 2258766558 ps
CPU time 20.16 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:45 PM PDT 24
Peak memory 197280 kb
Host smart-e54b0dd0-204c-4024-b626-80e265f9aa6d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141412504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3141412504
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3886411081
Short name T14
Test name
Test status
Simulation time 142928727 ps
CPU time 0.77 seconds
Started Jul 26 05:39:22 PM PDT 24
Finished Jul 26 05:39:24 PM PDT 24
Peak memory 196884 kb
Host smart-ccfbda58-b14d-4f1f-b835-d7f71e40d319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886411081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3886411081
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1384302825
Short name T578
Test name
Test status
Simulation time 62741510 ps
CPU time 1.12 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 196592 kb
Host smart-ad9823ae-0fd8-499f-aba6-076bd24c0b11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384302825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1384302825
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2913742816
Short name T264
Test name
Test status
Simulation time 299427541 ps
CPU time 2.8 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:29 PM PDT 24
Peak memory 198548 kb
Host smart-db3f3835-4fad-402d-b3db-997b0b642814
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913742816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2913742816
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.472078771
Short name T566
Test name
Test status
Simulation time 33528729 ps
CPU time 1.22 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:29 PM PDT 24
Peak memory 197824 kb
Host smart-fd91878b-0525-4060-8975-641939cdf9cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472078771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.472078771
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3079961112
Short name T509
Test name
Test status
Simulation time 25991133 ps
CPU time 0.77 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 195828 kb
Host smart-43e387e1-7a74-446b-b7a1-6722806cdf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079961112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3079961112
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3238859053
Short name T434
Test name
Test status
Simulation time 34591217 ps
CPU time 1.13 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 197328 kb
Host smart-ab93e950-06ef-45ac-ab04-a7fa6db07da9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238859053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3238859053
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3850848125
Short name T362
Test name
Test status
Simulation time 172899091 ps
CPU time 4.12 seconds
Started Jul 26 05:39:24 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 198420 kb
Host smart-7781fb04-8e5a-462f-9c17-e1fdeb3576d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850848125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3850848125
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1287066729
Short name T58
Test name
Test status
Simulation time 204484210 ps
CPU time 0.86 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 215288 kb
Host smart-c62b04c4-1c3c-4bbd-996a-3280eaa973f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287066729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1287066729
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3543165001
Short name T591
Test name
Test status
Simulation time 32997719 ps
CPU time 0.96 seconds
Started Jul 26 05:39:24 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 196060 kb
Host smart-127d0017-ccbe-4b8e-8ea5-cdf8bb69a225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543165001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3543165001
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3965834800
Short name T365
Test name
Test status
Simulation time 60107500 ps
CPU time 1.16 seconds
Started Jul 26 05:39:29 PM PDT 24
Finished Jul 26 05:39:31 PM PDT 24
Peak memory 196232 kb
Host smart-c9bb936b-3048-4d98-9bdf-51cbead5e221
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965834800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3965834800
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.78102013
Short name T145
Test name
Test status
Simulation time 30116402682 ps
CPU time 66.94 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 198620 kb
Host smart-35a7a382-bb38-4897-8f47-3fc26938f8ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78102013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpi
o_stress_all.78102013
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3268682844
Short name T701
Test name
Test status
Simulation time 71706344125 ps
CPU time 877.58 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:54:04 PM PDT 24
Peak memory 198840 kb
Host smart-32b7c7c4-3a85-427b-8026-b46872c80c96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3268682844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3268682844
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1589155690
Short name T644
Test name
Test status
Simulation time 11882283 ps
CPU time 0.54 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 194404 kb
Host smart-775e2469-e065-4c01-95f1-95997992ad1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589155690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1589155690
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1244265940
Short name T409
Test name
Test status
Simulation time 15908800 ps
CPU time 0.75 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 194524 kb
Host smart-7746c51f-5549-451c-aebc-ede621b9b1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244265940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1244265940
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3747567831
Short name T369
Test name
Test status
Simulation time 1591627461 ps
CPU time 21.39 seconds
Started Jul 26 05:39:42 PM PDT 24
Finished Jul 26 05:40:03 PM PDT 24
Peak memory 196544 kb
Host smart-8bd342e8-7e89-4f94-96f8-6f01f5f5e811
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747567831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3747567831
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2568321865
Short name T510
Test name
Test status
Simulation time 237449520 ps
CPU time 0.86 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 196560 kb
Host smart-b8b04d61-f2b1-48ed-aae3-41361bb9c7be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568321865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2568321865
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2668049446
Short name T447
Test name
Test status
Simulation time 42060098 ps
CPU time 0.87 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 196360 kb
Host smart-8be4ca61-1f96-487a-8fad-628bbf6b4bcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668049446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2668049446
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2009537388
Short name T527
Test name
Test status
Simulation time 288156523 ps
CPU time 3.51 seconds
Started Jul 26 05:39:52 PM PDT 24
Finished Jul 26 05:39:56 PM PDT 24
Peak memory 198640 kb
Host smart-25b7fdd4-9955-4999-9174-3266b35e709c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009537388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2009537388
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2653216138
Short name T25
Test name
Test status
Simulation time 115696088 ps
CPU time 2.53 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:48 PM PDT 24
Peak memory 196264 kb
Host smart-b3cf6cc3-9bf9-401e-b3b7-bd12608e1117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653216138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2653216138
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.650837015
Short name T265
Test name
Test status
Simulation time 514068192 ps
CPU time 1.02 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 196224 kb
Host smart-472f25d6-97f3-4a93-99df-84fd1a2e6696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650837015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.650837015
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1982668502
Short name T206
Test name
Test status
Simulation time 33885507 ps
CPU time 0.98 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 196308 kb
Host smart-4378589e-7c85-49ce-b376-08b157b61a26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982668502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1982668502
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1367176869
Short name T276
Test name
Test status
Simulation time 455076829 ps
CPU time 2.05 seconds
Started Jul 26 05:39:49 PM PDT 24
Finished Jul 26 05:39:52 PM PDT 24
Peak memory 198484 kb
Host smart-bffb8613-a601-418d-9c10-1696eae6396e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367176869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1367176869
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2965674668
Short name T23
Test name
Test status
Simulation time 80233844 ps
CPU time 0.78 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 195668 kb
Host smart-fdc4a8fe-dbc2-45dd-ac17-2fac78b11ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965674668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2965674668
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1481459326
Short name T190
Test name
Test status
Simulation time 247841267 ps
CPU time 1.17 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 195952 kb
Host smart-71350be0-5227-4d53-9cdc-cbcfe45d4a91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481459326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1481459326
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1503865625
Short name T38
Test name
Test status
Simulation time 16883592956 ps
CPU time 114.14 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:41:39 PM PDT 24
Peak memory 198632 kb
Host smart-2c62040b-8847-4d13-ae3f-e6e1aa70eaa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503865625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1503865625
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.2099305007
Short name T69
Test name
Test status
Simulation time 9402489907 ps
CPU time 170.35 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 198784 kb
Host smart-3c5d7698-6e93-4e75-8ae5-ee0ac9e35b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2099305007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.2099305007
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1361790169
Short name T451
Test name
Test status
Simulation time 23186952 ps
CPU time 0.56 seconds
Started Jul 26 05:39:40 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 193172 kb
Host smart-8f3a7671-adf6-43f6-8ba9-d77df5642818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361790169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1361790169
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3471027196
Short name T579
Test name
Test status
Simulation time 100919017 ps
CPU time 1.03 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:39 PM PDT 24
Peak memory 197172 kb
Host smart-884fc31a-07e1-4f82-ac9f-0fbdf20e7534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471027196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3471027196
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.351824141
Short name T673
Test name
Test status
Simulation time 282655141 ps
CPU time 9.01 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:52 PM PDT 24
Peak memory 198416 kb
Host smart-aae912aa-0187-4576-ae5c-ed1880a955d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351824141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.351824141
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2366019196
Short name T263
Test name
Test status
Simulation time 91130537 ps
CPU time 1 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 197168 kb
Host smart-972d6aef-2b19-4cc2-9d58-f5a2fa9943c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366019196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2366019196
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.909161070
Short name T89
Test name
Test status
Simulation time 175460995 ps
CPU time 1.36 seconds
Started Jul 26 05:39:35 PM PDT 24
Finished Jul 26 05:39:36 PM PDT 24
Peak memory 197916 kb
Host smart-034db07b-6038-4f26-9cfc-69e822a98728
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909161070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.909161070
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.83432587
Short name T230
Test name
Test status
Simulation time 243903455 ps
CPU time 0.95 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 197284 kb
Host smart-adf5bd42-8407-45c3-8070-ae1050360010
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83432587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.gpio_intr_with_filter_rand_intr_event.83432587
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1557858469
Short name T248
Test name
Test status
Simulation time 27750064 ps
CPU time 0.92 seconds
Started Jul 26 05:39:37 PM PDT 24
Finished Jul 26 05:39:38 PM PDT 24
Peak memory 194896 kb
Host smart-b9cdc5e2-e2d7-48a2-833b-7dd529338c80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557858469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1557858469
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1395350903
Short name T77
Test name
Test status
Simulation time 195118671 ps
CPU time 1.01 seconds
Started Jul 26 05:39:35 PM PDT 24
Finished Jul 26 05:39:36 PM PDT 24
Peak memory 196384 kb
Host smart-54d17e7a-810d-4a92-bd97-d1229cab69a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395350903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1395350903
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.4005151184
Short name T465
Test name
Test status
Simulation time 76999040 ps
CPU time 1.42 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:41 PM PDT 24
Peak memory 197492 kb
Host smart-d41646a9-c90c-429c-82c9-aabac30e1a0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005151184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.4005151184
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1328325935
Short name T562
Test name
Test status
Simulation time 436541737 ps
CPU time 4.92 seconds
Started Jul 26 05:39:35 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 198476 kb
Host smart-c1e86959-3be2-41a1-af03-c78829568a2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328325935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1328325935
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1294252463
Short name T164
Test name
Test status
Simulation time 167913212 ps
CPU time 1.21 seconds
Started Jul 26 05:39:42 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 196308 kb
Host smart-bba8ab3e-8fb6-4f46-b359-2df9bf81af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294252463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1294252463
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.563764943
Short name T672
Test name
Test status
Simulation time 51625419 ps
CPU time 1.18 seconds
Started Jul 26 05:39:37 PM PDT 24
Finished Jul 26 05:39:38 PM PDT 24
Peak memory 196092 kb
Host smart-568f9984-ce74-432f-98f4-b883f51e56ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563764943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.563764943
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3692520212
Short name T376
Test name
Test status
Simulation time 3555432471 ps
CPU time 94.5 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:41:16 PM PDT 24
Peak memory 198552 kb
Host smart-5a97a8bb-c745-46e2-8f41-af8e317c9d1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692520212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3692520212
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2167175920
Short name T635
Test name
Test status
Simulation time 38320338 ps
CPU time 0.6 seconds
Started Jul 26 05:39:47 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 194372 kb
Host smart-8ff2d530-f6a3-4132-83d7-dc56b9c97683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167175920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2167175920
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.98368450
Short name T553
Test name
Test status
Simulation time 34991556 ps
CPU time 0.85 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:52 PM PDT 24
Peak memory 195868 kb
Host smart-d12c5377-b6e9-4403-a0d5-29d9306eedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98368450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.98368450
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2292452094
Short name T546
Test name
Test status
Simulation time 2627293987 ps
CPU time 19.09 seconds
Started Jul 26 05:40:07 PM PDT 24
Finished Jul 26 05:40:27 PM PDT 24
Peak memory 198472 kb
Host smart-77db97a3-29ba-43a0-a52c-aa9d1c95a66e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292452094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2292452094
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4268772939
Short name T714
Test name
Test status
Simulation time 463766784 ps
CPU time 1.03 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:56 PM PDT 24
Peak memory 197020 kb
Host smart-b744c8c2-93a6-4a9d-bc3f-d68035008b55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268772939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4268772939
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2082206588
Short name T367
Test name
Test status
Simulation time 100225652 ps
CPU time 1.35 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:46 PM PDT 24
Peak memory 196944 kb
Host smart-83b3e8b6-efb1-4f7f-af50-b95e810da1e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082206588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2082206588
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2968075478
Short name T180
Test name
Test status
Simulation time 131709274 ps
CPU time 2.71 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:51 PM PDT 24
Peak memory 198524 kb
Host smart-2cdce77d-c1c7-4433-99f5-e24e069e3549
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968075478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2968075478
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.126891692
Short name T663
Test name
Test status
Simulation time 343715977 ps
CPU time 1.87 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:48 PM PDT 24
Peak memory 196276 kb
Host smart-b6b18009-7d53-4e46-9d8f-b621b22b2e9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126891692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
126891692
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1955433655
Short name T613
Test name
Test status
Simulation time 39263755 ps
CPU time 0.82 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:52 PM PDT 24
Peak memory 196968 kb
Host smart-9f36b0eb-d940-4a63-a222-383db4e07ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955433655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1955433655
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2883635471
Short name T418
Test name
Test status
Simulation time 50934122 ps
CPU time 1.1 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 197100 kb
Host smart-85e61cb8-5102-4039-a609-84f1f4bd674e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883635471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2883635471
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1691341756
Short name T182
Test name
Test status
Simulation time 26391897 ps
CPU time 1.16 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:49 PM PDT 24
Peak memory 198432 kb
Host smart-a6026ae3-8514-402d-bc09-f288654b6ee5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691341756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1691341756
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.825030236
Short name T374
Test name
Test status
Simulation time 142433955 ps
CPU time 1.15 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:41 PM PDT 24
Peak memory 196044 kb
Host smart-cfb58d1a-ca36-4648-8e7f-d5710ba77f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825030236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.825030236
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1378466920
Short name T495
Test name
Test status
Simulation time 205298294 ps
CPU time 1 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:52 PM PDT 24
Peak memory 196280 kb
Host smart-74c064c1-7029-47a2-8336-0bec1e40a4ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378466920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1378466920
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1631671291
Short name T463
Test name
Test status
Simulation time 24672971074 ps
CPU time 131.49 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:41:56 PM PDT 24
Peak memory 198676 kb
Host smart-55a79d35-90ce-4be0-b32a-68969a14ed3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631671291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1631671291
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1299096884
Short name T489
Test name
Test status
Simulation time 50693773 ps
CPU time 0.59 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:49 PM PDT 24
Peak memory 195136 kb
Host smart-fc30e9c8-de7b-40ea-9bb1-0aa8df4dd28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299096884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1299096884
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2403327134
Short name T652
Test name
Test status
Simulation time 53361188 ps
CPU time 0.76 seconds
Started Jul 26 05:39:53 PM PDT 24
Finished Jul 26 05:39:54 PM PDT 24
Peak memory 195656 kb
Host smart-821c7e99-7a71-4489-8300-f65d44dc8973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403327134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2403327134
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.576783482
Short name T179
Test name
Test status
Simulation time 6472479428 ps
CPU time 13.29 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:40:09 PM PDT 24
Peak memory 197108 kb
Host smart-0a3f1d82-aa5a-4ad7-9102-5c1b44b01697
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576783482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.576783482
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1044589003
Short name T349
Test name
Test status
Simulation time 268316966 ps
CPU time 0.61 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 195548 kb
Host smart-aa14e2c1-b5ea-42be-8d9b-4a41635bf94b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044589003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1044589003
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.870462180
Short name T680
Test name
Test status
Simulation time 115426135 ps
CPU time 1.3 seconds
Started Jul 26 05:40:07 PM PDT 24
Finished Jul 26 05:40:09 PM PDT 24
Peak memory 197360 kb
Host smart-8ec3f751-4275-4153-8fff-9f1dfbccc385
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870462180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.870462180
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.75657520
Short name T715
Test name
Test status
Simulation time 87422093 ps
CPU time 3.41 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 198548 kb
Host smart-765ad355-cb9f-435e-8790-e012b8db65c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75657520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.gpio_intr_with_filter_rand_intr_event.75657520
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3507939501
Short name T521
Test name
Test status
Simulation time 191662666 ps
CPU time 1.28 seconds
Started Jul 26 05:39:56 PM PDT 24
Finished Jul 26 05:39:57 PM PDT 24
Peak memory 197356 kb
Host smart-2fa85e16-24f0-4ebe-b676-f68de6b4e009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507939501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3507939501
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3591626508
Short name T650
Test name
Test status
Simulation time 60286339 ps
CPU time 0.92 seconds
Started Jul 26 05:40:07 PM PDT 24
Finished Jul 26 05:40:08 PM PDT 24
Peak memory 196408 kb
Host smart-c9be9f67-6dbc-49b0-86e6-0225c9a9705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591626508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3591626508
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.262549433
Short name T81
Test name
Test status
Simulation time 77827294 ps
CPU time 1.37 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 197400 kb
Host smart-d87eca81-d1c0-41e0-81d8-c531df423e8a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262549433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.262549433
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2490105589
Short name T339
Test name
Test status
Simulation time 2245817143 ps
CPU time 5.38 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:53 PM PDT 24
Peak memory 197048 kb
Host smart-7d1c78b4-0234-4d40-b448-ac9799428287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490105589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2490105589
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3118483054
Short name T148
Test name
Test status
Simulation time 200146995 ps
CPU time 1.21 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:49 PM PDT 24
Peak memory 196148 kb
Host smart-456f2389-dda5-4fbd-aa75-449d138bfb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118483054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3118483054
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3525559908
Short name T594
Test name
Test status
Simulation time 91397971 ps
CPU time 0.76 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:52 PM PDT 24
Peak memory 195736 kb
Host smart-32d134de-248d-4e1d-b1b2-0a4b1c558a76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525559908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3525559908
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.4135623719
Short name T647
Test name
Test status
Simulation time 4250937923 ps
CPU time 103.6 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:41:35 PM PDT 24
Peak memory 198620 kb
Host smart-cd547394-36f9-4252-9705-29140c8d8e60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135623719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.4135623719
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3948534126
Short name T625
Test name
Test status
Simulation time 102051568398 ps
CPU time 1264.93 seconds
Started Jul 26 05:40:07 PM PDT 24
Finished Jul 26 06:01:13 PM PDT 24
Peak memory 198696 kb
Host smart-00b2d9a4-16d5-48a5-bbae-da3311fde04a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3948534126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3948534126
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1952633032
Short name T517
Test name
Test status
Simulation time 52386136 ps
CPU time 0.62 seconds
Started Jul 26 05:39:47 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 195308 kb
Host smart-51e0aa3c-bbe3-48d8-8990-37de4538b94f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952633032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1952633032
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2067434442
Short name T618
Test name
Test status
Simulation time 31131045 ps
CPU time 0.86 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:49 PM PDT 24
Peak memory 197588 kb
Host smart-37a2b370-962c-4901-9665-11ea4e24c49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067434442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2067434442
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2124616906
Short name T360
Test name
Test status
Simulation time 730287862 ps
CPU time 21.65 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:40:06 PM PDT 24
Peak memory 198512 kb
Host smart-62371599-f61c-4696-977b-1d1b741ea81a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124616906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2124616906
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1495431948
Short name T525
Test name
Test status
Simulation time 105031127 ps
CPU time 0.78 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 196220 kb
Host smart-aef3356f-67c9-45e2-b3f5-7c842d5770b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495431948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1495431948
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2092425580
Short name T486
Test name
Test status
Simulation time 70618046 ps
CPU time 1.1 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:46 PM PDT 24
Peak memory 196464 kb
Host smart-af1396bf-588c-4f54-8f07-6f8418717378
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092425580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2092425580
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1688825341
Short name T243
Test name
Test status
Simulation time 24903121 ps
CPU time 0.97 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 196156 kb
Host smart-a48e3318-9753-4c36-9a08-26443ff99caf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688825341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1688825341
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.690733156
Short name T268
Test name
Test status
Simulation time 472414422 ps
CPU time 2.19 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:53 PM PDT 24
Peak memory 197424 kb
Host smart-89b5f5bd-d20e-41db-8299-c7ee0f9e0dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690733156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
690733156
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3787925167
Short name T452
Test name
Test status
Simulation time 40126729 ps
CPU time 0.92 seconds
Started Jul 26 05:39:47 PM PDT 24
Finished Jul 26 05:39:48 PM PDT 24
Peak memory 196452 kb
Host smart-83357ffc-8cfc-4340-9ae1-445283c31443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787925167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3787925167
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1497333888
Short name T384
Test name
Test status
Simulation time 225275935 ps
CPU time 1.04 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:46 PM PDT 24
Peak memory 196312 kb
Host smart-8d7e07c5-0c24-45d9-891e-c85251ecc37b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497333888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1497333888
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2028246175
Short name T423
Test name
Test status
Simulation time 177297149 ps
CPU time 1.78 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 198480 kb
Host smart-e47e8ab0-51bf-425b-8e4f-2e458b29a40b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028246175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2028246175
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3775401903
Short name T80
Test name
Test status
Simulation time 293899268 ps
CPU time 1.34 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:48 PM PDT 24
Peak memory 197420 kb
Host smart-fa35a5f0-e64a-427a-982b-70bc153966df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775401903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3775401903
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1951194045
Short name T221
Test name
Test status
Simulation time 68567792 ps
CPU time 1.17 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 196048 kb
Host smart-e87b5cb0-54f0-40de-83f1-e694d3144f0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951194045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1951194045
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2394146678
Short name T299
Test name
Test status
Simulation time 18022740425 ps
CPU time 109.76 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:41:45 PM PDT 24
Peak memory 198564 kb
Host smart-811e0993-d15a-4241-bf1a-273f16f1f15a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394146678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2394146678
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2408135756
Short name T383
Test name
Test status
Simulation time 156911455 ps
CPU time 0.94 seconds
Started Jul 26 05:39:58 PM PDT 24
Finished Jul 26 05:39:59 PM PDT 24
Peak memory 196156 kb
Host smart-1d473051-8675-44e1-913f-0862cf99f564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408135756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2408135756
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2378534512
Short name T412
Test name
Test status
Simulation time 852068062 ps
CPU time 7.83 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:59 PM PDT 24
Peak memory 197664 kb
Host smart-54f59a3b-91ac-4c4f-86c5-c818938aab4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378534512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2378534512
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2365954429
Short name T361
Test name
Test status
Simulation time 421571664 ps
CPU time 1.18 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:57 PM PDT 24
Peak memory 197312 kb
Host smart-9e89c04a-9fc7-454e-bd1d-ebe1d1a5aa4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365954429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2365954429
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2184594965
Short name T83
Test name
Test status
Simulation time 76560415 ps
CPU time 3.06 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:59 PM PDT 24
Peak memory 198640 kb
Host smart-04e87c85-2bf3-4cd7-8e30-ae3d86ad5d9e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184594965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2184594965
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1601211366
Short name T505
Test name
Test status
Simulation time 98017957 ps
CPU time 2.11 seconds
Started Jul 26 05:39:47 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 197700 kb
Host smart-7dfc35f9-e290-412f-a1c4-af2c1feddf9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601211366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1601211366
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3785142810
Short name T62
Test name
Test status
Simulation time 58679908 ps
CPU time 1.3 seconds
Started Jul 26 05:39:49 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 197392 kb
Host smart-06a1fbd9-05e6-4402-86cc-ebb31ece1621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785142810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3785142810
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.171103917
Short name T211
Test name
Test status
Simulation time 37475221 ps
CPU time 0.7 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:56 PM PDT 24
Peak memory 194792 kb
Host smart-ed20b479-c2b1-4984-979a-8e7384def65d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171103917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.171103917
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1589416206
Short name T2
Test name
Test status
Simulation time 102211818 ps
CPU time 1.54 seconds
Started Jul 26 05:40:10 PM PDT 24
Finished Jul 26 05:40:11 PM PDT 24
Peak memory 198392 kb
Host smart-361ea4f4-1f57-4078-89cc-5b9ec5b8bce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589416206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1589416206
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2247754910
Short name T687
Test name
Test status
Simulation time 422384571 ps
CPU time 1.1 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:49 PM PDT 24
Peak memory 196048 kb
Host smart-f1649714-ff5a-4b8b-9a82-8de6fdb1d286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247754910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2247754910
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2808824475
Short name T488
Test name
Test status
Simulation time 52527562 ps
CPU time 1.02 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 196408 kb
Host smart-72633d09-f62f-406f-a65a-22745c747f6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808824475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2808824475
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1498680580
Short name T638
Test name
Test status
Simulation time 1345669226 ps
CPU time 40.26 seconds
Started Jul 26 05:40:07 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 198468 kb
Host smart-c3e55307-80d9-4c34-a358-81ae34a20597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498680580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1498680580
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.4109538728
Short name T721
Test name
Test status
Simulation time 18744527 ps
CPU time 0.59 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:52 PM PDT 24
Peak memory 194352 kb
Host smart-e05f346d-dc42-4f5f-b714-4206d2e8a4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109538728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.4109538728
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3273625484
Short name T189
Test name
Test status
Simulation time 39629771 ps
CPU time 0.86 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:49 PM PDT 24
Peak memory 196688 kb
Host smart-493229ec-bf0c-47e1-bd32-b3aefed125f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273625484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3273625484
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.990952101
Short name T197
Test name
Test status
Simulation time 1639858942 ps
CPU time 10.94 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:40:02 PM PDT 24
Peak memory 197348 kb
Host smart-946a42e5-dbec-47d7-9af9-1f2ba8e5bc38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990952101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.990952101
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1374834729
Short name T17
Test name
Test status
Simulation time 42360991 ps
CPU time 0.76 seconds
Started Jul 26 05:39:59 PM PDT 24
Finished Jul 26 05:40:00 PM PDT 24
Peak memory 196248 kb
Host smart-c4ece904-cf74-4e3a-a100-a831bed541c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374834729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1374834729
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2638110874
Short name T697
Test name
Test status
Simulation time 79687887 ps
CPU time 0.71 seconds
Started Jul 26 05:39:52 PM PDT 24
Finished Jul 26 05:39:53 PM PDT 24
Peak memory 195544 kb
Host smart-e0103c70-ae67-45d3-8042-ae85e4e0df3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638110874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2638110874
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.558263820
Short name T149
Test name
Test status
Simulation time 372496838 ps
CPU time 2.08 seconds
Started Jul 26 05:40:09 PM PDT 24
Finished Jul 26 05:40:11 PM PDT 24
Peak memory 198292 kb
Host smart-6a3c5d8d-e450-4165-b825-52c9872d72f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558263820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.558263820
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3286268479
Short name T312
Test name
Test status
Simulation time 1376569011 ps
CPU time 2.23 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 198592 kb
Host smart-39e86343-07b7-481b-b4db-759e2d53e604
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286268479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3286268479
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3012865895
Short name T397
Test name
Test status
Simulation time 29776939 ps
CPU time 0.89 seconds
Started Jul 26 05:39:57 PM PDT 24
Finished Jul 26 05:39:58 PM PDT 24
Peak memory 197132 kb
Host smart-75258150-af3f-42f3-ac62-bb78de718067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012865895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3012865895
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1502479215
Short name T82
Test name
Test status
Simulation time 30904035 ps
CPU time 0.7 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:39:49 PM PDT 24
Peak memory 195476 kb
Host smart-7e51bda0-acf0-4538-ba0c-fbcf918a694a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502479215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1502479215
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3102337775
Short name T634
Test name
Test status
Simulation time 38564324 ps
CPU time 1.55 seconds
Started Jul 26 05:39:58 PM PDT 24
Finished Jul 26 05:40:00 PM PDT 24
Peak memory 198400 kb
Host smart-551fe900-b8bf-4863-bced-ce178f18c74d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102337775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3102337775
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.691054781
Short name T477
Test name
Test status
Simulation time 244674639 ps
CPU time 1.14 seconds
Started Jul 26 05:40:12 PM PDT 24
Finished Jul 26 05:40:14 PM PDT 24
Peak memory 196820 kb
Host smart-a5ce3a2f-dc92-4199-9008-8be6730b6523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691054781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.691054781
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3458665536
Short name T563
Test name
Test status
Simulation time 63409845 ps
CPU time 1.12 seconds
Started Jul 26 05:40:14 PM PDT 24
Finished Jul 26 05:40:15 PM PDT 24
Peak memory 195688 kb
Host smart-8bb7b14d-592b-44ad-b5b9-15424783e160
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458665536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3458665536
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1267294864
Short name T636
Test name
Test status
Simulation time 13284782875 ps
CPU time 86.32 seconds
Started Jul 26 05:39:49 PM PDT 24
Finished Jul 26 05:41:16 PM PDT 24
Peak memory 198600 kb
Host smart-c83f5f37-d68c-42aa-9cd4-c7e1099c0cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267294864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1267294864
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2509838341
Short name T466
Test name
Test status
Simulation time 49264873 ps
CPU time 0.57 seconds
Started Jul 26 05:39:53 PM PDT 24
Finished Jul 26 05:39:54 PM PDT 24
Peak memory 194400 kb
Host smart-6a20a1ba-f3e7-4576-a8ca-c4b2b12a3dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509838341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2509838341
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.63550378
Short name T324
Test name
Test status
Simulation time 43809771 ps
CPU time 0.78 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 195668 kb
Host smart-b710f947-47c9-48a0-bc31-ebb57d0dc896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63550378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.63550378
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1991656272
Short name T138
Test name
Test status
Simulation time 340337313 ps
CPU time 12.79 seconds
Started Jul 26 05:40:01 PM PDT 24
Finished Jul 26 05:40:14 PM PDT 24
Peak memory 198424 kb
Host smart-e154339e-0448-480a-a6f0-9bcaa11cb85e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991656272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1991656272
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4278126727
Short name T208
Test name
Test status
Simulation time 54175461 ps
CPU time 0.81 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:56 PM PDT 24
Peak memory 196492 kb
Host smart-bfcb5afb-cf3b-4732-8a0a-fb8b5e3b1e13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278126727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4278126727
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1724815924
Short name T502
Test name
Test status
Simulation time 140833939 ps
CPU time 1.27 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 198560 kb
Host smart-ffdd6e52-d023-4811-9383-5a0aab28e0b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724815924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1724815924
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1046402001
Short name T470
Test name
Test status
Simulation time 126644752 ps
CPU time 2.56 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:39:57 PM PDT 24
Peak memory 198472 kb
Host smart-5e08c835-f6fd-43d2-aeda-7c14c29681b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046402001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1046402001
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.823645338
Short name T334
Test name
Test status
Simulation time 163658651 ps
CPU time 2.44 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:54 PM PDT 24
Peak memory 197736 kb
Host smart-37666cff-6235-4858-8f2a-1634826c624c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823645338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
823645338
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1242960733
Short name T192
Test name
Test status
Simulation time 36274141 ps
CPU time 0.63 seconds
Started Jul 26 05:40:14 PM PDT 24
Finished Jul 26 05:40:15 PM PDT 24
Peak memory 194820 kb
Host smart-cf67b30e-6970-430a-bd62-a3fb3660ebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242960733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1242960733
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4156968095
Short name T142
Test name
Test status
Simulation time 29633243 ps
CPU time 1.02 seconds
Started Jul 26 05:40:12 PM PDT 24
Finished Jul 26 05:40:13 PM PDT 24
Peak memory 196344 kb
Host smart-ef4106ed-af33-4ceb-a278-decdcb1565b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156968095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.4156968095
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3495577281
Short name T490
Test name
Test status
Simulation time 104203533 ps
CPU time 2.9 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:39:57 PM PDT 24
Peak memory 198436 kb
Host smart-624a3aba-38ab-48fd-ab43-1cfa00b824b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495577281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3495577281
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3630396697
Short name T491
Test name
Test status
Simulation time 65772514 ps
CPU time 1.12 seconds
Started Jul 26 05:40:09 PM PDT 24
Finished Jul 26 05:40:11 PM PDT 24
Peak memory 195932 kb
Host smart-bc4da3bc-c5fc-4a30-9fc1-060aa15982eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630396697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3630396697
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.301700403
Short name T173
Test name
Test status
Simulation time 74053064 ps
CPU time 1.13 seconds
Started Jul 26 05:40:12 PM PDT 24
Finished Jul 26 05:40:14 PM PDT 24
Peak memory 196064 kb
Host smart-9feb9b3c-6cb9-4792-9d80-09e5154c7fe5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301700403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.301700403
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.524476746
Short name T196
Test name
Test status
Simulation time 5543080447 ps
CPU time 81.26 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 198580 kb
Host smart-6c8a3f9c-d846-4fc6-b0ee-891a7683f122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524476746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.524476746
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.4259645058
Short name T153
Test name
Test status
Simulation time 51701352 ps
CPU time 0.6 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 194828 kb
Host smart-7301d00a-d5dd-491d-a21a-afe657822537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259645058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.4259645058
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.4119342776
Short name T36
Test name
Test status
Simulation time 53727188 ps
CPU time 0.8 seconds
Started Jul 26 05:39:56 PM PDT 24
Finished Jul 26 05:39:57 PM PDT 24
Peak memory 196448 kb
Host smart-1ca9441d-f3b7-4e49-ba29-fe2fef5e0336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119342776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.4119342776
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2603836049
Short name T215
Test name
Test status
Simulation time 499905272 ps
CPU time 25.29 seconds
Started Jul 26 05:39:58 PM PDT 24
Finished Jul 26 05:40:23 PM PDT 24
Peak memory 197280 kb
Host smart-fbfb31e3-4174-418b-a50f-7e6e05dd5b10
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603836049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2603836049
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.895790694
Short name T653
Test name
Test status
Simulation time 259993985 ps
CPU time 0.92 seconds
Started Jul 26 05:40:14 PM PDT 24
Finished Jul 26 05:40:15 PM PDT 24
Peak memory 196800 kb
Host smart-e2b60fb9-3976-4e82-bb0d-644147a8b27b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895790694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.895790694
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.455778786
Short name T396
Test name
Test status
Simulation time 56141598 ps
CPU time 1.07 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 196488 kb
Host smart-aeb7cb14-5930-4691-bd02-072005b6d5ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455778786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.455778786
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.4160260939
Short name T519
Test name
Test status
Simulation time 31595695 ps
CPU time 1.33 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:57 PM PDT 24
Peak memory 197132 kb
Host smart-dffbbbd6-5e30-4d85-9466-4eea8199a3f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160260939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.4160260939
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4114745971
Short name T674
Test name
Test status
Simulation time 323192323 ps
CPU time 2.33 seconds
Started Jul 26 05:40:01 PM PDT 24
Finished Jul 26 05:40:03 PM PDT 24
Peak memory 197604 kb
Host smart-805c3ab0-6b84-49d1-901d-26a62d6c133b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114745971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4114745971
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1793525542
Short name T445
Test name
Test status
Simulation time 41086472 ps
CPU time 0.99 seconds
Started Jul 26 05:39:57 PM PDT 24
Finished Jul 26 05:39:58 PM PDT 24
Peak memory 196480 kb
Host smart-d1ea02df-acdd-414e-9f05-980e235a5d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793525542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1793525542
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3530386933
Short name T400
Test name
Test status
Simulation time 65808592 ps
CPU time 1.25 seconds
Started Jul 26 05:39:56 PM PDT 24
Finished Jul 26 05:39:57 PM PDT 24
Peak memory 197512 kb
Host smart-51a69a66-e03b-471b-8984-fb6c8869be4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530386933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3530386933
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1303608969
Short name T548
Test name
Test status
Simulation time 238798629 ps
CPU time 2.93 seconds
Started Jul 26 05:39:58 PM PDT 24
Finished Jul 26 05:40:01 PM PDT 24
Peak memory 198524 kb
Host smart-14daae87-4f6e-45bb-ac13-36972a970a65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303608969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1303608969
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3955560113
Short name T270
Test name
Test status
Simulation time 113162827 ps
CPU time 1.22 seconds
Started Jul 26 05:39:58 PM PDT 24
Finished Jul 26 05:39:59 PM PDT 24
Peak memory 196296 kb
Host smart-38b39828-d673-49a1-8053-45a957fe9d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955560113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3955560113
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1607897001
Short name T371
Test name
Test status
Simulation time 497782593 ps
CPU time 1.11 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:56 PM PDT 24
Peak memory 196300 kb
Host smart-f881670e-1d19-497a-a123-7a78b3409377
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607897001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1607897001
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.690654859
Short name T183
Test name
Test status
Simulation time 12993855903 ps
CPU time 198.29 seconds
Started Jul 26 05:39:56 PM PDT 24
Finished Jul 26 05:43:14 PM PDT 24
Peak memory 198644 kb
Host smart-783d8bea-60ab-461c-8bd6-ea74659ac653
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690654859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.690654859
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.839173373
Short name T165
Test name
Test status
Simulation time 16842782 ps
CPU time 0.58 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 194592 kb
Host smart-faffaba9-1aa4-48cb-8a87-5d57f678eec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839173373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.839173373
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2704725336
Short name T395
Test name
Test status
Simulation time 233423185 ps
CPU time 0.91 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 196160 kb
Host smart-a5a7d3d8-be5b-45a0-be5c-8df56872f174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704725336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2704725336
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3479328200
Short name T518
Test name
Test status
Simulation time 3432049424 ps
CPU time 14.61 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:40:09 PM PDT 24
Peak memory 197464 kb
Host smart-89c6e51f-175a-4d2e-9086-0d623ff93135
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479328200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3479328200
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1236516594
Short name T225
Test name
Test status
Simulation time 159742187 ps
CPU time 0.74 seconds
Started Jul 26 05:39:53 PM PDT 24
Finished Jul 26 05:39:54 PM PDT 24
Peak memory 197088 kb
Host smart-0c462ff5-2daa-41ed-b1e1-7960641b4f99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236516594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1236516594
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1236958036
Short name T487
Test name
Test status
Simulation time 258518980 ps
CPU time 1.15 seconds
Started Jul 26 05:40:01 PM PDT 24
Finished Jul 26 05:40:02 PM PDT 24
Peak memory 196204 kb
Host smart-0fe801e6-740d-4f73-98a3-a4dd7fc9a5f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236958036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1236958036
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1702355230
Short name T479
Test name
Test status
Simulation time 194809852 ps
CPU time 1.99 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 196732 kb
Host smart-8602edec-b8c4-45ce-8958-da7e5b556f49
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702355230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1702355230
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1631028717
Short name T585
Test name
Test status
Simulation time 130534274 ps
CPU time 2.4 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:58 PM PDT 24
Peak memory 196224 kb
Host smart-c62a4060-b36f-4e2d-96cb-5fd10ac44ce6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631028717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1631028717
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.703495233
Short name T181
Test name
Test status
Simulation time 242329762 ps
CPU time 1.25 seconds
Started Jul 26 05:39:56 PM PDT 24
Finished Jul 26 05:39:58 PM PDT 24
Peak memory 196272 kb
Host smart-bcb94800-a73a-485a-b44d-8074b4c1e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703495233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.703495233
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2304565640
Short name T686
Test name
Test status
Simulation time 105923212 ps
CPU time 0.95 seconds
Started Jul 26 05:39:57 PM PDT 24
Finished Jul 26 05:39:58 PM PDT 24
Peak memory 196376 kb
Host smart-33dd00ab-e8a8-4730-a1f8-9a9a98ac50f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304565640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2304565640
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3163584335
Short name T79
Test name
Test status
Simulation time 123115300 ps
CPU time 1.59 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:40:01 PM PDT 24
Peak memory 198480 kb
Host smart-957bedc0-5968-44aa-94db-3918536ce842
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163584335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3163584335
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3748864394
Short name T544
Test name
Test status
Simulation time 38277691 ps
CPU time 1.29 seconds
Started Jul 26 05:39:52 PM PDT 24
Finished Jul 26 05:39:54 PM PDT 24
Peak memory 197724 kb
Host smart-3f5988af-2e24-4056-be3f-f1658eda4c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748864394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3748864394
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2083570146
Short name T293
Test name
Test status
Simulation time 75146233 ps
CPU time 1.1 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 196012 kb
Host smart-049e1f69-5306-4eb9-8bcc-3c3f3d9b3f19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083570146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2083570146
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1062160291
Short name T661
Test name
Test status
Simulation time 8879372093 ps
CPU time 60.4 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:40:56 PM PDT 24
Peak memory 198608 kb
Host smart-58799f1b-9f6e-4d7c-aa8e-1d47e01179eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062160291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1062160291
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.497773035
Short name T628
Test name
Test status
Simulation time 54142043193 ps
CPU time 1066.73 seconds
Started Jul 26 05:40:07 PM PDT 24
Finished Jul 26 05:57:54 PM PDT 24
Peak memory 198736 kb
Host smart-1e8d3117-f140-4fd3-a070-aa3a01c99625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=497773035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.497773035
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3627521351
Short name T387
Test name
Test status
Simulation time 14196154 ps
CPU time 0.57 seconds
Started Jul 26 05:39:29 PM PDT 24
Finished Jul 26 05:39:30 PM PDT 24
Peak memory 194372 kb
Host smart-35df23c9-5724-4d0f-9f25-942c26ca49f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627521351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3627521351
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2807629685
Short name T28
Test name
Test status
Simulation time 34333765 ps
CPU time 0.74 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 195604 kb
Host smart-729a398e-79aa-4406-9e9b-125431670ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807629685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2807629685
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3431148869
Short name T251
Test name
Test status
Simulation time 892575487 ps
CPU time 13.05 seconds
Started Jul 26 05:39:28 PM PDT 24
Finished Jul 26 05:39:41 PM PDT 24
Peak memory 197592 kb
Host smart-4cbaac6a-dcda-4758-b353-fdd36cd4321b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431148869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3431148869
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.111690008
Short name T201
Test name
Test status
Simulation time 385246620 ps
CPU time 0.95 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 196980 kb
Host smart-27b511e0-1cf9-45c6-b794-4bd9f99f30f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111690008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.111690008
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2948117760
Short name T326
Test name
Test status
Simulation time 129976985 ps
CPU time 0.86 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 197196 kb
Host smart-e364d883-687c-4e4b-a10e-ffbfa4eba2d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948117760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2948117760
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3280171512
Short name T620
Test name
Test status
Simulation time 406868280 ps
CPU time 1.93 seconds
Started Jul 26 05:39:28 PM PDT 24
Finished Jul 26 05:39:30 PM PDT 24
Peak memory 198604 kb
Host smart-a160fba5-87d3-4890-b231-bce1ca68ad8c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280171512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3280171512
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3636949956
Short name T695
Test name
Test status
Simulation time 102343340 ps
CPU time 2.88 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 05:39:29 PM PDT 24
Peak memory 196328 kb
Host smart-92129e5f-94c9-45a6-b804-3cb332b49a67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636949956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3636949956
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3537137435
Short name T420
Test name
Test status
Simulation time 88697627 ps
CPU time 1 seconds
Started Jul 26 05:39:24 PM PDT 24
Finished Jul 26 05:39:25 PM PDT 24
Peak memory 196280 kb
Host smart-7ede6db1-add0-4906-9e61-b70feaac65de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537137435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3537137435
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1322983074
Short name T614
Test name
Test status
Simulation time 319999476 ps
CPU time 1.05 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 196340 kb
Host smart-ad86088b-8f35-4a78-8354-eb139f376575
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322983074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1322983074
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1908804483
Short name T39
Test name
Test status
Simulation time 2836840344 ps
CPU time 3.73 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:31 PM PDT 24
Peak memory 198556 kb
Host smart-a5bc42b6-698e-412c-95c3-fac2ce496d0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908804483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1908804483
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.2918287132
Short name T462
Test name
Test status
Simulation time 126706085 ps
CPU time 1.01 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 197008 kb
Host smart-c53ee5ec-7a2f-43c8-824c-cc083695be42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918287132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2918287132
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1653629745
Short name T718
Test name
Test status
Simulation time 43817739 ps
CPU time 0.88 seconds
Started Jul 26 05:39:31 PM PDT 24
Finished Jul 26 05:39:32 PM PDT 24
Peak memory 195584 kb
Host smart-08fba949-4124-46af-b294-1bb3d45cb8d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653629745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1653629745
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.4240145865
Short name T681
Test name
Test status
Simulation time 17310216652 ps
CPU time 180.63 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 05:42:27 PM PDT 24
Peak memory 198612 kb
Host smart-4d10a58e-639c-44e7-9d72-a76f3163bdd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240145865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.4240145865
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.3337290226
Short name T40
Test name
Test status
Simulation time 122647139107 ps
CPU time 1752.36 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 06:08:39 PM PDT 24
Peak memory 198652 kb
Host smart-a119e881-c957-4d37-9c89-e9f23e149d3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3337290226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.3337290226
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2852493564
Short name T590
Test name
Test status
Simulation time 25659986 ps
CPU time 0.59 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 196120 kb
Host smart-8d1a9516-ef2c-4ab5-89e2-b3782f7a0d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852493564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2852493564
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3883374841
Short name T459
Test name
Test status
Simulation time 25218970 ps
CPU time 0.75 seconds
Started Jul 26 05:39:58 PM PDT 24
Finished Jul 26 05:39:59 PM PDT 24
Peak memory 196444 kb
Host smart-66793290-431b-43b0-a349-29c95c293970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883374841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3883374841
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.615324871
Short name T341
Test name
Test status
Simulation time 2847210329 ps
CPU time 23.64 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:40:18 PM PDT 24
Peak memory 197872 kb
Host smart-1f26f52d-69e6-4015-87d3-0b95ae732cb7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615324871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.615324871
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.552317743
Short name T48
Test name
Test status
Simulation time 44920276 ps
CPU time 0.81 seconds
Started Jul 26 05:39:57 PM PDT 24
Finished Jul 26 05:39:58 PM PDT 24
Peak memory 196256 kb
Host smart-69a9ff9e-65a7-4871-8ee4-e49a24e22cbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552317743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.552317743
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3832281088
Short name T538
Test name
Test status
Simulation time 166385665 ps
CPU time 1.36 seconds
Started Jul 26 05:39:56 PM PDT 24
Finished Jul 26 05:39:57 PM PDT 24
Peak memory 198568 kb
Host smart-efb5ffd8-7759-4812-83b6-566cec83fe6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832281088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3832281088
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.493821272
Short name T202
Test name
Test status
Simulation time 115331927 ps
CPU time 3.07 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:58 PM PDT 24
Peak memory 198512 kb
Host smart-a2fd1852-e7b1-4f0e-be8f-4d5a71a4dca1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493821272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.493821272
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2466650402
Short name T186
Test name
Test status
Simulation time 60578341 ps
CPU time 1.32 seconds
Started Jul 26 05:39:57 PM PDT 24
Finished Jul 26 05:39:58 PM PDT 24
Peak memory 197056 kb
Host smart-f71157c8-d015-4c4e-bdbb-5a843b1aea0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466650402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2466650402
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2340916028
Short name T464
Test name
Test status
Simulation time 140563890 ps
CPU time 0.95 seconds
Started Jul 26 05:39:55 PM PDT 24
Finished Jul 26 05:39:56 PM PDT 24
Peak memory 196568 kb
Host smart-0c6f6169-0c71-4d12-b719-10ff05dea539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340916028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2340916028
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1445939886
Short name T13
Test name
Test status
Simulation time 29958097 ps
CPU time 0.84 seconds
Started Jul 26 05:39:53 PM PDT 24
Finished Jul 26 05:39:54 PM PDT 24
Peak memory 195968 kb
Host smart-4bab14d3-d166-4753-a43b-5d6d28608bf4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445939886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1445939886
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1215987114
Short name T453
Test name
Test status
Simulation time 104891440 ps
CPU time 3.48 seconds
Started Jul 26 05:39:57 PM PDT 24
Finished Jul 26 05:40:00 PM PDT 24
Peak memory 197568 kb
Host smart-5946c739-07ed-47be-9b67-761355ec6c4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215987114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1215987114
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1418508436
Short name T136
Test name
Test status
Simulation time 219912419 ps
CPU time 1.54 seconds
Started Jul 26 05:39:53 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 197328 kb
Host smart-581298a5-83cc-4913-810b-c295091bb201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418508436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1418508436
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.303927930
Short name T250
Test name
Test status
Simulation time 132870010 ps
CPU time 1.14 seconds
Started Jul 26 05:40:01 PM PDT 24
Finished Jul 26 05:40:03 PM PDT 24
Peak memory 196244 kb
Host smart-6bbe3fa0-d0a5-4e91-8d64-d34087f98f86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303927930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.303927930
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2712712888
Short name T393
Test name
Test status
Simulation time 4184992460 ps
CPU time 110 seconds
Started Jul 26 05:39:54 PM PDT 24
Finished Jul 26 05:41:44 PM PDT 24
Peak memory 198640 kb
Host smart-1f76c552-80a3-47e4-a6ad-193a48156918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712712888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2712712888
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.1448554823
Short name T73
Test name
Test status
Simulation time 62791520218 ps
CPU time 931.32 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:55:48 PM PDT 24
Peak memory 198776 kb
Host smart-bc6daff8-df76-47e0-b17c-215cbd079aa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1448554823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.1448554823
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1745857440
Short name T392
Test name
Test status
Simulation time 17161529 ps
CPU time 0.57 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:16 PM PDT 24
Peak memory 194436 kb
Host smart-38c50715-dc4d-493e-8ac7-ef3e6c388a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745857440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1745857440
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.4066054619
Short name T610
Test name
Test status
Simulation time 115982995 ps
CPU time 0.75 seconds
Started Jul 26 05:40:03 PM PDT 24
Finished Jul 26 05:40:04 PM PDT 24
Peak memory 196416 kb
Host smart-d163868f-681b-4cf4-8179-2de32b17e32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066054619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.4066054619
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1363762269
Short name T271
Test name
Test status
Simulation time 496021953 ps
CPU time 20.72 seconds
Started Jul 26 05:40:03 PM PDT 24
Finished Jul 26 05:40:24 PM PDT 24
Peak memory 197328 kb
Host smart-920a9a64-c791-42a1-8ee7-4294e9f41584
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363762269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1363762269
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.666726209
Short name T698
Test name
Test status
Simulation time 94417942 ps
CPU time 0.69 seconds
Started Jul 26 05:40:13 PM PDT 24
Finished Jul 26 05:40:13 PM PDT 24
Peak memory 195212 kb
Host smart-8243b372-4edb-4caa-816e-dde7670bd9d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666726209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.666726209
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1563770280
Short name T685
Test name
Test status
Simulation time 81472351 ps
CPU time 1.26 seconds
Started Jul 26 05:40:18 PM PDT 24
Finished Jul 26 05:40:19 PM PDT 24
Peak memory 197416 kb
Host smart-e7960c57-941e-48c7-b7ec-a0fc319d3178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563770280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1563770280
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2222320939
Short name T174
Test name
Test status
Simulation time 62389294 ps
CPU time 2.38 seconds
Started Jul 26 05:40:21 PM PDT 24
Finished Jul 26 05:40:24 PM PDT 24
Peak memory 198524 kb
Host smart-1efa6b97-84ec-4fb3-bd1e-11c6c55d09e9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222320939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2222320939
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3740810370
Short name T175
Test name
Test status
Simulation time 114347004 ps
CPU time 1.39 seconds
Started Jul 26 05:40:03 PM PDT 24
Finished Jul 26 05:40:05 PM PDT 24
Peak memory 197048 kb
Host smart-f198363e-2b66-48d9-b64d-5c2db44e623e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740810370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3740810370
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.351207892
Short name T274
Test name
Test status
Simulation time 28051096 ps
CPU time 1.05 seconds
Started Jul 26 05:40:08 PM PDT 24
Finished Jul 26 05:40:09 PM PDT 24
Peak memory 196464 kb
Host smart-c8578c17-53d9-4c25-b261-1a65336b8b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351207892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.351207892
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.413900876
Short name T140
Test name
Test status
Simulation time 31994478 ps
CPU time 0.9 seconds
Started Jul 26 05:40:20 PM PDT 24
Finished Jul 26 05:40:21 PM PDT 24
Peak memory 197028 kb
Host smart-9b902fc5-661f-42ac-98ef-62b009d8bba0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413900876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.413900876
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2284503177
Short name T155
Test name
Test status
Simulation time 686494244 ps
CPU time 4.99 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:20 PM PDT 24
Peak memory 198364 kb
Host smart-3093fc34-6d3a-4052-93a1-a13eb20c8c1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284503177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2284503177
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1511244661
Short name T281
Test name
Test status
Simulation time 67816816 ps
CPU time 1.25 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 196992 kb
Host smart-7f3418f8-ce6f-4879-b4cb-50dc6378bffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511244661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1511244661
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3955323139
Short name T679
Test name
Test status
Simulation time 38329776 ps
CPU time 1.19 seconds
Started Jul 26 05:40:03 PM PDT 24
Finished Jul 26 05:40:04 PM PDT 24
Peak memory 198488 kb
Host smart-cc1f054d-6a99-4fe9-9c26-8ca8e23e889b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955323139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3955323139
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1213490362
Short name T651
Test name
Test status
Simulation time 4634088121 ps
CPU time 41.29 seconds
Started Jul 26 05:40:20 PM PDT 24
Finished Jul 26 05:41:01 PM PDT 24
Peak memory 198600 kb
Host smart-d9b24666-ed38-44f4-9030-ad5e1d1dcc3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213490362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1213490362
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2226205867
Short name T612
Test name
Test status
Simulation time 17010879 ps
CPU time 0.62 seconds
Started Jul 26 05:40:17 PM PDT 24
Finished Jul 26 05:40:18 PM PDT 24
Peak memory 194616 kb
Host smart-1df12116-0ad1-4413-9712-c8a3564a3c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226205867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2226205867
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.60042520
Short name T210
Test name
Test status
Simulation time 72113002 ps
CPU time 0.85 seconds
Started Jul 26 05:40:12 PM PDT 24
Finished Jul 26 05:40:13 PM PDT 24
Peak memory 196612 kb
Host smart-b498ed72-293d-45df-bee8-e2a2b1459dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60042520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.60042520
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1184537944
Short name T624
Test name
Test status
Simulation time 312538340 ps
CPU time 10.77 seconds
Started Jul 26 05:40:02 PM PDT 24
Finished Jul 26 05:40:13 PM PDT 24
Peak memory 198416 kb
Host smart-867d9c59-6253-463d-b3ad-b114aa6be72f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184537944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1184537944
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1809237520
Short name T670
Test name
Test status
Simulation time 159242155 ps
CPU time 0.68 seconds
Started Jul 26 05:40:18 PM PDT 24
Finished Jul 26 05:40:19 PM PDT 24
Peak memory 195760 kb
Host smart-61b3d490-247d-4893-a18e-5d6b87bdae7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809237520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1809237520
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.413346299
Short name T630
Test name
Test status
Simulation time 40395927 ps
CPU time 0.86 seconds
Started Jul 26 05:40:20 PM PDT 24
Finished Jul 26 05:40:21 PM PDT 24
Peak memory 196204 kb
Host smart-c84e62f0-fe74-4fb5-8772-d1b74ca9ff6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413346299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.413346299
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.415070311
Short name T347
Test name
Test status
Simulation time 28308358 ps
CPU time 1.21 seconds
Started Jul 26 05:40:03 PM PDT 24
Finished Jul 26 05:40:05 PM PDT 24
Peak memory 197932 kb
Host smart-034e6019-8cbb-4dec-bea7-2495f1929338
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415070311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.415070311
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1946289898
Short name T260
Test name
Test status
Simulation time 51418149 ps
CPU time 1.21 seconds
Started Jul 26 05:40:02 PM PDT 24
Finished Jul 26 05:40:03 PM PDT 24
Peak memory 197888 kb
Host smart-e618a35e-a5ad-4196-ac00-9068994ffcb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946289898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1946289898
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2494782649
Short name T694
Test name
Test status
Simulation time 21680621 ps
CPU time 0.97 seconds
Started Jul 26 05:40:01 PM PDT 24
Finished Jul 26 05:40:02 PM PDT 24
Peak memory 196424 kb
Host smart-baac5318-467b-4924-a3ae-4987a713a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494782649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2494782649
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2413162976
Short name T433
Test name
Test status
Simulation time 48668023 ps
CPU time 0.98 seconds
Started Jul 26 05:40:03 PM PDT 24
Finished Jul 26 05:40:04 PM PDT 24
Peak memory 196300 kb
Host smart-cbed5d28-eef4-4889-a254-3fe7e215b7be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413162976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2413162976
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2861401445
Short name T595
Test name
Test status
Simulation time 153392790 ps
CPU time 2.21 seconds
Started Jul 26 05:40:24 PM PDT 24
Finished Jul 26 05:40:26 PM PDT 24
Peak memory 198432 kb
Host smart-a5be63b6-6d54-43b5-800e-670b9372e30c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861401445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2861401445
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2355088368
Short name T134
Test name
Test status
Simulation time 28797485 ps
CPU time 0.96 seconds
Started Jul 26 05:40:04 PM PDT 24
Finished Jul 26 05:40:05 PM PDT 24
Peak memory 196204 kb
Host smart-d6b544fa-ff8a-420c-9cd5-d23071673278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355088368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2355088368
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2241290641
Short name T709
Test name
Test status
Simulation time 467106011 ps
CPU time 1.25 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:40:18 PM PDT 24
Peak memory 196904 kb
Host smart-242b3c19-b389-47af-be29-2ea14c3857ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241290641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2241290641
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2521212908
Short name T3
Test name
Test status
Simulation time 52616488750 ps
CPU time 142.05 seconds
Started Jul 26 05:40:02 PM PDT 24
Finished Jul 26 05:42:24 PM PDT 24
Peak memory 198584 kb
Host smart-6c21955e-2eb5-4c51-b715-7eca9b66722d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521212908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2521212908
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2259674212
Short name T427
Test name
Test status
Simulation time 111190234726 ps
CPU time 2390.76 seconds
Started Jul 26 05:40:13 PM PDT 24
Finished Jul 26 06:20:04 PM PDT 24
Peak memory 198760 kb
Host smart-6e8f2560-d3ce-4e0d-abc4-6ead22d4c98a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2259674212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2259674212
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3953562973
Short name T406
Test name
Test status
Simulation time 13751200 ps
CPU time 0.55 seconds
Started Jul 26 05:40:10 PM PDT 24
Finished Jul 26 05:40:11 PM PDT 24
Peak memory 194620 kb
Host smart-a23c4a67-8c7f-427e-be10-581e6f78d6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953562973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3953562973
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2401451728
Short name T599
Test name
Test status
Simulation time 47129315 ps
CPU time 0.78 seconds
Started Jul 26 05:40:03 PM PDT 24
Finished Jul 26 05:40:04 PM PDT 24
Peak memory 195780 kb
Host smart-6f2beb70-87ab-4496-8682-5da2ded18d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401451728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2401451728
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3606818916
Short name T421
Test name
Test status
Simulation time 730939552 ps
CPU time 24.71 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:40:41 PM PDT 24
Peak memory 198512 kb
Host smart-0f588f87-4ded-4b9a-97f7-b10b29bdc872
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606818916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3606818916
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1694430682
Short name T552
Test name
Test status
Simulation time 78118873 ps
CPU time 0.71 seconds
Started Jul 26 05:40:17 PM PDT 24
Finished Jul 26 05:40:18 PM PDT 24
Peak memory 194680 kb
Host smart-1fc2abba-53e3-4f59-a2d3-90a44664182c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694430682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1694430682
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.148418616
Short name T688
Test name
Test status
Simulation time 86842351 ps
CPU time 1.37 seconds
Started Jul 26 05:40:04 PM PDT 24
Finished Jul 26 05:40:05 PM PDT 24
Peak memory 197456 kb
Host smart-6e44e6d9-5eae-4fea-bc21-1d7838b43a43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148418616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.148418616
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1144183068
Short name T59
Test name
Test status
Simulation time 204387754 ps
CPU time 2.23 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 196976 kb
Host smart-d3ca73ad-5f49-4f35-8093-7bdb97ae0ed2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144183068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1144183068
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2936060478
Short name T399
Test name
Test status
Simulation time 92027452 ps
CPU time 2.68 seconds
Started Jul 26 05:40:22 PM PDT 24
Finished Jul 26 05:40:25 PM PDT 24
Peak memory 198560 kb
Host smart-cb57320d-33aa-4672-b6de-003512efc04a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936060478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2936060478
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1438870812
Short name T19
Test name
Test status
Simulation time 30079483 ps
CPU time 0.84 seconds
Started Jul 26 05:40:01 PM PDT 24
Finished Jul 26 05:40:02 PM PDT 24
Peak memory 197004 kb
Host smart-112636d2-8328-4a7d-8ed4-ebbaf72bd4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438870812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1438870812
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1870025802
Short name T122
Test name
Test status
Simulation time 117131533 ps
CPU time 1.34 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:16 PM PDT 24
Peak memory 197628 kb
Host smart-e41cb6b9-892d-480b-9c14-5eb2010e6438
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870025802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1870025802
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.268650423
Short name T4
Test name
Test status
Simulation time 3484748574 ps
CPU time 6.57 seconds
Started Jul 26 05:40:20 PM PDT 24
Finished Jul 26 05:40:27 PM PDT 24
Peak memory 198456 kb
Host smart-774ec1d0-f2ba-434a-9fdf-94ffa39899d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268650423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.268650423
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2295950912
Short name T523
Test name
Test status
Simulation time 80995534 ps
CPU time 1.05 seconds
Started Jul 26 05:40:13 PM PDT 24
Finished Jul 26 05:40:14 PM PDT 24
Peak memory 196184 kb
Host smart-921977c2-d47c-42a5-a197-5763c99a5623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295950912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2295950912
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3725732093
Short name T343
Test name
Test status
Simulation time 24194946 ps
CPU time 0.85 seconds
Started Jul 26 05:40:13 PM PDT 24
Finished Jul 26 05:40:14 PM PDT 24
Peak memory 195732 kb
Host smart-550331b1-5759-41a3-bf7a-df22cb637500
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725732093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3725732093
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3551397609
Short name T483
Test name
Test status
Simulation time 44273065026 ps
CPU time 44.25 seconds
Started Jul 26 05:40:13 PM PDT 24
Finished Jul 26 05:40:57 PM PDT 24
Peak memory 198572 kb
Host smart-8b25cb13-386c-4412-88f9-165d6c588998
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551397609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3551397609
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3564102668
Short name T194
Test name
Test status
Simulation time 21554653 ps
CPU time 0.6 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 194372 kb
Host smart-822ce604-4337-4a1a-a998-ef1a65634815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564102668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3564102668
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2832515375
Short name T146
Test name
Test status
Simulation time 116167320 ps
CPU time 0.77 seconds
Started Jul 26 05:40:24 PM PDT 24
Finished Jul 26 05:40:25 PM PDT 24
Peak memory 195712 kb
Host smart-1e16b575-b259-43ad-bc5f-f6cd774dc444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832515375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2832515375
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2049787791
Short name T305
Test name
Test status
Simulation time 712034572 ps
CPU time 20.41 seconds
Started Jul 26 05:40:12 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 197264 kb
Host smart-979d323f-af86-4da0-93c8-46854a6fd4ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049787791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2049787791
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3760687013
Short name T357
Test name
Test status
Simulation time 180473387 ps
CPU time 1.04 seconds
Started Jul 26 05:40:11 PM PDT 24
Finished Jul 26 05:40:12 PM PDT 24
Peak memory 197112 kb
Host smart-9adb7ef6-ae23-4816-b1c4-d5d526ebf685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760687013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3760687013
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3062723736
Short name T424
Test name
Test status
Simulation time 65094991 ps
CPU time 0.72 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 195972 kb
Host smart-bcd946b7-69c2-41a5-9a42-45d0373f4a27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062723736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3062723736
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3512154706
Short name T404
Test name
Test status
Simulation time 99236798 ps
CPU time 3.29 seconds
Started Jul 26 05:40:23 PM PDT 24
Finished Jul 26 05:40:27 PM PDT 24
Peak memory 198672 kb
Host smart-b6fcc811-a6ce-4e55-b31d-63909e479871
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512154706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3512154706
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.239748511
Short name T308
Test name
Test status
Simulation time 516353562 ps
CPU time 2.75 seconds
Started Jul 26 05:40:09 PM PDT 24
Finished Jul 26 05:40:12 PM PDT 24
Peak memory 197768 kb
Host smart-2ef9d9a2-0592-438f-8c12-94c5cb1e654e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239748511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
239748511
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1723618597
Short name T631
Test name
Test status
Simulation time 86093875 ps
CPU time 0.69 seconds
Started Jul 26 05:40:21 PM PDT 24
Finished Jul 26 05:40:21 PM PDT 24
Peak memory 194832 kb
Host smart-70376545-f0cf-400b-8d1b-0dc56b761f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723618597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1723618597
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1960336974
Short name T571
Test name
Test status
Simulation time 71315679 ps
CPU time 0.91 seconds
Started Jul 26 05:40:26 PM PDT 24
Finished Jul 26 05:40:27 PM PDT 24
Peak memory 196516 kb
Host smart-deb1eaaf-7813-4f2b-888e-b26e8e13ccb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960336974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1960336974
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2271214639
Short name T157
Test name
Test status
Simulation time 51664549 ps
CPU time 1.4 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 198192 kb
Host smart-ed2b3ee5-5944-4b1c-8655-eb798616a299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271214639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2271214639
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.386739571
Short name T603
Test name
Test status
Simulation time 77888788 ps
CPU time 1.18 seconds
Started Jul 26 05:40:19 PM PDT 24
Finished Jul 26 05:40:20 PM PDT 24
Peak memory 195888 kb
Host smart-0938a862-f0d0-4c12-9b7b-96118bad2e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386739571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.386739571
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3526890870
Short name T530
Test name
Test status
Simulation time 134050659 ps
CPU time 1.04 seconds
Started Jul 26 05:40:14 PM PDT 24
Finished Jul 26 05:40:16 PM PDT 24
Peak memory 196180 kb
Host smart-d5a0fb02-b011-49ce-9992-92e184cc8f86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526890870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3526890870
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.344842562
Short name T645
Test name
Test status
Simulation time 7069732713 ps
CPU time 74.39 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:41:45 PM PDT 24
Peak memory 198580 kb
Host smart-d91bcfaa-baea-429b-9cde-aca8ede0713a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344842562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.344842562
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3176488078
Short name T416
Test name
Test status
Simulation time 366281270452 ps
CPU time 2058.44 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 06:14:33 PM PDT 24
Peak memory 198736 kb
Host smart-eaea05a4-43c8-4fc7-b0d6-65a3b965638f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3176488078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3176488078
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1401682643
Short name T21
Test name
Test status
Simulation time 19955572 ps
CPU time 0.58 seconds
Started Jul 26 05:40:27 PM PDT 24
Finished Jul 26 05:40:28 PM PDT 24
Peak memory 195120 kb
Host smart-a0bc097a-6b7c-4dda-a986-ffe7c87a9a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401682643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1401682643
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2331634446
Short name T565
Test name
Test status
Simulation time 31057001 ps
CPU time 0.72 seconds
Started Jul 26 05:40:31 PM PDT 24
Finished Jul 26 05:40:32 PM PDT 24
Peak memory 194444 kb
Host smart-7457b17f-690d-472f-bab6-8e217147245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331634446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2331634446
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3484542545
Short name T676
Test name
Test status
Simulation time 733054183 ps
CPU time 19.56 seconds
Started Jul 26 05:40:28 PM PDT 24
Finished Jul 26 05:40:47 PM PDT 24
Peak memory 197188 kb
Host smart-c845a913-c6cb-4c9a-acf1-7e30e53d62d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484542545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3484542545
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1762711693
Short name T84
Test name
Test status
Simulation time 361682639 ps
CPU time 0.9 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:16 PM PDT 24
Peak memory 198248 kb
Host smart-56240b51-0467-4e7a-9597-0fd838ccf8e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762711693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1762711693
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.762961593
Short name T492
Test name
Test status
Simulation time 34768131 ps
CPU time 0.82 seconds
Started Jul 26 05:40:21 PM PDT 24
Finished Jul 26 05:40:22 PM PDT 24
Peak memory 196040 kb
Host smart-1304869e-a82a-46f2-8a47-bfdc74f942dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762961593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.762961593
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1610197952
Short name T379
Test name
Test status
Simulation time 26458887 ps
CPU time 1.16 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 198504 kb
Host smart-db35622e-ca89-47d8-8665-036486c1f972
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610197952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1610197952
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.432934511
Short name T555
Test name
Test status
Simulation time 113846172 ps
CPU time 1.62 seconds
Started Jul 26 05:40:19 PM PDT 24
Finished Jul 26 05:40:20 PM PDT 24
Peak memory 196944 kb
Host smart-bcd59931-700a-4f69-b76e-84a63daf3c57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432934511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
432934511
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.4135228845
Short name T713
Test name
Test status
Simulation time 58380170 ps
CPU time 1.25 seconds
Started Jul 26 05:40:10 PM PDT 24
Finished Jul 26 05:40:11 PM PDT 24
Peak memory 197516 kb
Host smart-60993591-f364-4bf5-9a5e-c8a638bc9da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135228845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.4135228845
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2524333932
Short name T133
Test name
Test status
Simulation time 16255810 ps
CPU time 0.64 seconds
Started Jul 26 05:40:12 PM PDT 24
Finished Jul 26 05:40:13 PM PDT 24
Peak memory 194772 kb
Host smart-571188f9-7f46-409c-be95-101d8e39caad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524333932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2524333932
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3856926292
Short name T385
Test name
Test status
Simulation time 628009737 ps
CPU time 4.92 seconds
Started Jul 26 05:40:13 PM PDT 24
Finished Jul 26 05:40:18 PM PDT 24
Peak memory 198404 kb
Host smart-d8bf0e5c-dfb3-4391-876f-e4c330752c92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856926292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3856926292
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.855544751
Short name T314
Test name
Test status
Simulation time 62907174 ps
CPU time 1.09 seconds
Started Jul 26 05:40:25 PM PDT 24
Finished Jul 26 05:40:26 PM PDT 24
Peak memory 196372 kb
Host smart-60897efd-2ba5-475d-a6e6-c2eae62e3642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855544751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.855544751
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1226351563
Short name T333
Test name
Test status
Simulation time 51524700 ps
CPU time 0.92 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 195932 kb
Host smart-1cce6faf-1693-4275-9f85-413056f6d852
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226351563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1226351563
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.986155971
Short name T65
Test name
Test status
Simulation time 32947105322 ps
CPU time 64.18 seconds
Started Jul 26 05:40:24 PM PDT 24
Finished Jul 26 05:41:28 PM PDT 24
Peak memory 198568 kb
Host smart-8ef914ea-87a0-4380-9031-4295e631f9d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986155971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.986155971
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.865625283
Short name T91
Test name
Test status
Simulation time 73554653756 ps
CPU time 2003.88 seconds
Started Jul 26 05:40:13 PM PDT 24
Finished Jul 26 06:13:37 PM PDT 24
Peak memory 198676 kb
Host smart-fbe9d2e9-a738-4ebe-86f5-0175b601dab1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=865625283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.865625283
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.732598847
Short name T159
Test name
Test status
Simulation time 40828956 ps
CPU time 0.57 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:16 PM PDT 24
Peak memory 195240 kb
Host smart-f37843c4-0faa-4b96-ba14-2a76d451638d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732598847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.732598847
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.201543356
Short name T575
Test name
Test status
Simulation time 28834887 ps
CPU time 0.8 seconds
Started Jul 26 05:40:13 PM PDT 24
Finished Jul 26 05:40:14 PM PDT 24
Peak memory 196484 kb
Host smart-e725a635-4417-4bb0-81e4-90e03a9509a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201543356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.201543356
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.349972447
Short name T655
Test name
Test status
Simulation time 796691119 ps
CPU time 28.47 seconds
Started Jul 26 05:40:12 PM PDT 24
Finished Jul 26 05:40:41 PM PDT 24
Peak memory 197432 kb
Host smart-1a717fe7-6084-40cb-a38d-8d6c62cc2cb2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349972447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.349972447
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3840991651
Short name T437
Test name
Test status
Simulation time 1403684716 ps
CPU time 0.88 seconds
Started Jul 26 05:40:27 PM PDT 24
Finished Jul 26 05:40:28 PM PDT 24
Peak memory 197420 kb
Host smart-51536ed4-eeca-4a27-b90e-3d79c77b3876
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840991651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3840991651
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1037322899
Short name T704
Test name
Test status
Simulation time 253708505 ps
CPU time 1.25 seconds
Started Jul 26 05:40:18 PM PDT 24
Finished Jul 26 05:40:20 PM PDT 24
Peak memory 198480 kb
Host smart-c5702426-514d-47dd-bb9c-889cc470ba16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037322899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1037322899
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1477057234
Short name T255
Test name
Test status
Simulation time 343081197 ps
CPU time 3.46 seconds
Started Jul 26 05:40:22 PM PDT 24
Finished Jul 26 05:40:26 PM PDT 24
Peak memory 198504 kb
Host smart-be62d479-c876-4b8e-9923-46a762426228
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477057234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1477057234
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.679507967
Short name T703
Test name
Test status
Simulation time 220474154 ps
CPU time 1.85 seconds
Started Jul 26 05:40:18 PM PDT 24
Finished Jul 26 05:40:20 PM PDT 24
Peak memory 197220 kb
Host smart-b590bf16-be44-46cf-933c-0ac213f5cde4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679507967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
679507967
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3439727361
Short name T402
Test name
Test status
Simulation time 34159184 ps
CPU time 0.95 seconds
Started Jul 26 05:40:18 PM PDT 24
Finished Jul 26 05:40:19 PM PDT 24
Peak memory 196536 kb
Host smart-af994994-7841-43d7-9b60-4b1576f0ace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439727361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3439727361
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4232030670
Short name T589
Test name
Test status
Simulation time 39830668 ps
CPU time 1.33 seconds
Started Jul 26 05:40:14 PM PDT 24
Finished Jul 26 05:40:16 PM PDT 24
Peak memory 197436 kb
Host smart-4639fa72-6df2-420a-8ce6-7f0d12baf220
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232030670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4232030670
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.4004446131
Short name T15
Test name
Test status
Simulation time 92535510 ps
CPU time 4.12 seconds
Started Jul 26 05:40:12 PM PDT 24
Finished Jul 26 05:40:16 PM PDT 24
Peak memory 198696 kb
Host smart-fb3faf23-a83d-4232-a97b-43fc35e2740a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004446131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.4004446131
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2720988778
Short name T504
Test name
Test status
Simulation time 30932413 ps
CPU time 0.85 seconds
Started Jul 26 05:40:15 PM PDT 24
Finished Jul 26 05:40:16 PM PDT 24
Peak memory 195812 kb
Host smart-9dd33c8a-ddd6-47c1-9111-cf80ed387d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720988778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2720988778
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3544329933
Short name T151
Test name
Test status
Simulation time 31188385 ps
CPU time 0.8 seconds
Started Jul 26 05:40:26 PM PDT 24
Finished Jul 26 05:40:27 PM PDT 24
Peak memory 195768 kb
Host smart-992920e5-4dae-4617-9ce7-186c8c463857
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544329933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3544329933
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.746239178
Short name T473
Test name
Test status
Simulation time 77002737517 ps
CPU time 201.23 seconds
Started Jul 26 05:40:24 PM PDT 24
Finished Jul 26 05:43:46 PM PDT 24
Peak memory 198672 kb
Host smart-caf52cba-00ea-4163-9b77-fab63c1f3500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746239178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.746239178
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.326617636
Short name T214
Test name
Test status
Simulation time 27441073014 ps
CPU time 382.18 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:46:39 PM PDT 24
Peak memory 198772 kb
Host smart-771ab8f7-aeb4-44b0-82e1-9cd19829da29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=326617636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.326617636
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2467203013
Short name T520
Test name
Test status
Simulation time 63385864 ps
CPU time 0.56 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 193208 kb
Host smart-aae76e81-914a-41ca-b122-be6921ba1ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467203013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2467203013
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1479210162
Short name T535
Test name
Test status
Simulation time 60227228 ps
CPU time 0.62 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 195184 kb
Host smart-c57f83d5-148a-4706-a2a8-887ac8593dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479210162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1479210162
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_full_random.2858166052
Short name T382
Test name
Test status
Simulation time 79562781 ps
CPU time 0.64 seconds
Started Jul 26 05:40:19 PM PDT 24
Finished Jul 26 05:40:20 PM PDT 24
Peak memory 195724 kb
Host smart-dabbfced-d9a2-4f60-ab44-034911e50103
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858166052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2858166052
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.279006605
Short name T622
Test name
Test status
Simulation time 58934793 ps
CPU time 0.86 seconds
Started Jul 26 05:40:20 PM PDT 24
Finished Jul 26 05:40:21 PM PDT 24
Peak memory 197900 kb
Host smart-12d0fa62-e921-4fb2-ab2e-e77343083b97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279006605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.279006605
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1204473221
Short name T475
Test name
Test status
Simulation time 86193246 ps
CPU time 3.3 seconds
Started Jul 26 05:40:23 PM PDT 24
Finished Jul 26 05:40:27 PM PDT 24
Peak memory 198608 kb
Host smart-2a455b71-eb40-41dc-93b8-a4b54dc3b2e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204473221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1204473221
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1822474528
Short name T316
Test name
Test status
Simulation time 205270877 ps
CPU time 2.51 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:35 PM PDT 24
Peak memory 198544 kb
Host smart-45f0c4bd-9e59-4e95-bec4-9dd9d438ddea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822474528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1822474528
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3469612063
Short name T346
Test name
Test status
Simulation time 42679331 ps
CPU time 0.88 seconds
Started Jul 26 05:40:24 PM PDT 24
Finished Jul 26 05:40:25 PM PDT 24
Peak memory 197028 kb
Host smart-bcf97773-d4b3-465d-a5e6-9b78a93611a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469612063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3469612063
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.30327819
Short name T277
Test name
Test status
Simulation time 31028800 ps
CPU time 0.81 seconds
Started Jul 26 05:40:18 PM PDT 24
Finished Jul 26 05:40:19 PM PDT 24
Peak memory 196676 kb
Host smart-7f52cba4-8617-4f86-bc43-4b6167389413
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30327819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup_
pulldown.30327819
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1206492954
Short name T482
Test name
Test status
Simulation time 169704133 ps
CPU time 1.88 seconds
Started Jul 26 05:40:19 PM PDT 24
Finished Jul 26 05:40:21 PM PDT 24
Peak memory 198432 kb
Host smart-8a9e93a8-c913-4356-8ba5-bab495d506fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206492954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1206492954
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.66182274
Short name T389
Test name
Test status
Simulation time 90756096 ps
CPU time 1.44 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 197228 kb
Host smart-d8404a17-a061-49ec-9004-c9e7e927c50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66182274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.66182274
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2309753608
Short name T261
Test name
Test status
Simulation time 92356406 ps
CPU time 0.84 seconds
Started Jul 26 05:40:16 PM PDT 24
Finished Jul 26 05:40:17 PM PDT 24
Peak memory 195752 kb
Host smart-999289b8-ad3a-43e7-b8be-cc11b7e658b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309753608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2309753608
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3251875204
Short name T10
Test name
Test status
Simulation time 79397858750 ps
CPU time 119.05 seconds
Started Jul 26 05:40:29 PM PDT 24
Finished Jul 26 05:42:29 PM PDT 24
Peak memory 198548 kb
Host smart-4086d0f0-e9db-4d96-ae12-25b57c21208a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251875204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3251875204
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1896240274
Short name T267
Test name
Test status
Simulation time 266354193096 ps
CPU time 849.32 seconds
Started Jul 26 05:40:31 PM PDT 24
Finished Jul 26 05:54:41 PM PDT 24
Peak memory 198744 kb
Host smart-1ad1e186-2885-4c81-8f9f-219d01fc5a9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1896240274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1896240274
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3526086842
Short name T494
Test name
Test status
Simulation time 30837491 ps
CPU time 0.55 seconds
Started Jul 26 05:40:28 PM PDT 24
Finished Jul 26 05:40:29 PM PDT 24
Peak memory 194408 kb
Host smart-dc829604-e590-4b4d-8cb6-cbac8d26bfdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526086842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3526086842
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.827188961
Short name T573
Test name
Test status
Simulation time 71896425 ps
CPU time 0.73 seconds
Started Jul 26 05:40:27 PM PDT 24
Finished Jul 26 05:40:28 PM PDT 24
Peak memory 196480 kb
Host smart-1f817148-ff95-4143-9087-4343a8c0ea90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827188961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.827188961
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.827604640
Short name T524
Test name
Test status
Simulation time 865533921 ps
CPU time 28.59 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:41:01 PM PDT 24
Peak memory 197152 kb
Host smart-b5a28db2-b351-43bd-84e7-23b647c9dc9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827604640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.827604640
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2700583541
Short name T287
Test name
Test status
Simulation time 126400883 ps
CPU time 0.92 seconds
Started Jul 26 05:40:28 PM PDT 24
Finished Jul 26 05:40:29 PM PDT 24
Peak memory 198388 kb
Host smart-f965022e-158f-4ef3-ad28-e20329dbe516
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700583541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2700583541
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3765554182
Short name T481
Test name
Test status
Simulation time 172589823 ps
CPU time 1.6 seconds
Started Jul 26 05:40:33 PM PDT 24
Finished Jul 26 05:40:35 PM PDT 24
Peak memory 198564 kb
Host smart-2b46389a-0966-4669-a7c5-6850c6a512a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765554182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3765554182
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1535779601
Short name T498
Test name
Test status
Simulation time 24102143 ps
CPU time 1.01 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 196396 kb
Host smart-37026dbf-40c5-40e2-bcc7-da8f495ffcb0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535779601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1535779601
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4178102424
Short name T22
Test name
Test status
Simulation time 28351159 ps
CPU time 1.04 seconds
Started Jul 26 05:40:29 PM PDT 24
Finished Jul 26 05:40:30 PM PDT 24
Peak memory 196024 kb
Host smart-3e87c5b8-398f-4548-ab1d-412ae5906094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178102424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4178102424
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1201433512
Short name T691
Test name
Test status
Simulation time 547408683 ps
CPU time 1.3 seconds
Started Jul 26 05:40:35 PM PDT 24
Finished Jul 26 05:40:36 PM PDT 24
Peak memory 197640 kb
Host smart-ec82c87b-db92-4162-aaa4-9f072fdaa701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201433512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1201433512
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2019710876
Short name T303
Test name
Test status
Simulation time 29316231 ps
CPU time 1.11 seconds
Started Jul 26 05:40:29 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 197300 kb
Host smart-e0dfc112-9f6c-4d7d-ab10-9c48a9f1093c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019710876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2019710876
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2309197117
Short name T195
Test name
Test status
Simulation time 281965273 ps
CPU time 4.82 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:37 PM PDT 24
Peak memory 198464 kb
Host smart-ae69cd17-7757-4f8c-9e62-f6733318703c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309197117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2309197117
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3161065120
Short name T345
Test name
Test status
Simulation time 53609972 ps
CPU time 1.28 seconds
Started Jul 26 05:40:31 PM PDT 24
Finished Jul 26 05:40:32 PM PDT 24
Peak memory 197000 kb
Host smart-315fe506-9f70-4fde-bb54-cbc100a64cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161065120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3161065120
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2182458136
Short name T664
Test name
Test status
Simulation time 377742014 ps
CPU time 1.35 seconds
Started Jul 26 05:40:26 PM PDT 24
Finished Jul 26 05:40:28 PM PDT 24
Peak memory 197292 kb
Host smart-771c597f-bc88-4c3a-bfa2-7986e7f9c156
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182458136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2182458136
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2346812101
Short name T315
Test name
Test status
Simulation time 61403436370 ps
CPU time 154.55 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:43:04 PM PDT 24
Peak memory 198640 kb
Host smart-ef29780e-8c7c-430e-a204-12d4f40fa530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346812101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2346812101
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3546370415
Short name T649
Test name
Test status
Simulation time 37076949 ps
CPU time 0.58 seconds
Started Jul 26 05:40:31 PM PDT 24
Finished Jul 26 05:40:32 PM PDT 24
Peak memory 194388 kb
Host smart-f90f01a3-0e2e-43cc-8dcc-2c6857c58395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546370415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3546370415
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3128804708
Short name T273
Test name
Test status
Simulation time 61646383 ps
CPU time 0.79 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 195744 kb
Host smart-42d4dbcf-fdd5-4312-98b1-91a3b45604b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128804708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3128804708
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.617075184
Short name T683
Test name
Test status
Simulation time 304959351 ps
CPU time 10.43 seconds
Started Jul 26 05:40:28 PM PDT 24
Finished Jul 26 05:40:39 PM PDT 24
Peak memory 197524 kb
Host smart-95d9188f-bb74-4da0-b1dd-7a551ad89d52
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617075184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.617075184
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.874674285
Short name T222
Test name
Test status
Simulation time 85373856 ps
CPU time 0.84 seconds
Started Jul 26 05:40:29 PM PDT 24
Finished Jul 26 05:40:30 PM PDT 24
Peak memory 197012 kb
Host smart-f20f4ea0-d23c-41f5-8f2a-2a2f655e8f40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874674285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.874674285
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2917279658
Short name T554
Test name
Test status
Simulation time 42741388 ps
CPU time 1.07 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 196692 kb
Host smart-419d4f41-f5ac-4924-9d11-cdb5fc5e6710
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917279658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2917279658
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2277181378
Short name T236
Test name
Test status
Simulation time 254187299 ps
CPU time 1.58 seconds
Started Jul 26 05:40:27 PM PDT 24
Finished Jul 26 05:40:29 PM PDT 24
Peak memory 197280 kb
Host smart-ae46845b-ac39-40bf-8acc-3a8cd121750a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277181378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2277181378
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2811515799
Short name T226
Test name
Test status
Simulation time 264966578 ps
CPU time 2.33 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:34 PM PDT 24
Peak memory 198548 kb
Host smart-8435d5f8-dc21-4030-84e8-651e087c63e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811515799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2811515799
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2792054793
Short name T161
Test name
Test status
Simulation time 129107143 ps
CPU time 0.83 seconds
Started Jul 26 05:40:31 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 196688 kb
Host smart-2f901332-361e-4379-9d1c-51747ef2286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792054793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2792054793
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2459449708
Short name T332
Test name
Test status
Simulation time 37783029 ps
CPU time 0.67 seconds
Started Jul 26 05:40:34 PM PDT 24
Finished Jul 26 05:40:35 PM PDT 24
Peak memory 195528 kb
Host smart-488e3aa1-7471-4183-8a74-0d5c2a2106df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459449708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2459449708
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2906775973
Short name T615
Test name
Test status
Simulation time 119129430 ps
CPU time 5.4 seconds
Started Jul 26 05:40:26 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 198512 kb
Host smart-2d476495-d91e-47ae-8cf0-4753eef1e68b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906775973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2906775973
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1832804333
Short name T443
Test name
Test status
Simulation time 102281779 ps
CPU time 0.89 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 195748 kb
Host smart-7fc32c07-c0e6-451c-b114-22b8cf93aa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832804333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1832804333
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3698004247
Short name T588
Test name
Test status
Simulation time 133288315 ps
CPU time 0.87 seconds
Started Jul 26 05:40:28 PM PDT 24
Finished Jul 26 05:40:29 PM PDT 24
Peak memory 195860 kb
Host smart-9f2ca685-ae90-42ec-9bc3-f097d4fbfbb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698004247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3698004247
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3688372508
Short name T593
Test name
Test status
Simulation time 4260763585 ps
CPU time 47.27 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:41:18 PM PDT 24
Peak memory 198588 kb
Host smart-72b7220c-72c1-41da-92c8-6554cc168cd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688372508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3688372508
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.491267426
Short name T723
Test name
Test status
Simulation time 207117554674 ps
CPU time 352.74 seconds
Started Jul 26 05:40:33 PM PDT 24
Finished Jul 26 05:46:26 PM PDT 24
Peak memory 198696 kb
Host smart-ffcd8018-25fe-4989-9447-d740537e1cd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=491267426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.491267426
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3703569465
Short name T229
Test name
Test status
Simulation time 15334818 ps
CPU time 0.58 seconds
Started Jul 26 05:39:40 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 194544 kb
Host smart-d82cb239-adff-45a6-8326-29148a15e599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703569465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3703569465
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3740103891
Short name T659
Test name
Test status
Simulation time 133645491 ps
CPU time 0.87 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 196552 kb
Host smart-e0a211df-d179-4294-9af9-e33a1eef6b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740103891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3740103891
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.4188651448
Short name T717
Test name
Test status
Simulation time 396446875 ps
CPU time 5.18 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 197300 kb
Host smart-f4c233ac-36d2-4064-899f-439e4159dc4d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188651448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.4188651448
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3438616441
Short name T675
Test name
Test status
Simulation time 42356773 ps
CPU time 0.83 seconds
Started Jul 26 05:39:42 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 196428 kb
Host smart-8559925b-d7df-41f2-9ab3-bfd7105a1a2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438616441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3438616441
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2337745525
Short name T156
Test name
Test status
Simulation time 76879945 ps
CPU time 0.9 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 197116 kb
Host smart-bb499832-0c17-4822-8d58-e5f4a4fa5e97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337745525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2337745525
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3410360725
Short name T137
Test name
Test status
Simulation time 726288112 ps
CPU time 3.58 seconds
Started Jul 26 05:39:28 PM PDT 24
Finished Jul 26 05:39:32 PM PDT 24
Peak memory 197740 kb
Host smart-81c276dd-de36-4a69-8b6f-56dda42a718a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410360725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3410360725
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1934534774
Short name T127
Test name
Test status
Simulation time 69806423 ps
CPU time 1.4 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:29 PM PDT 24
Peak memory 198572 kb
Host smart-dab96838-898e-450a-ac1c-6af7eeea0cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934534774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1934534774
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3745894437
Short name T359
Test name
Test status
Simulation time 14866948 ps
CPU time 0.67 seconds
Started Jul 26 05:39:29 PM PDT 24
Finished Jul 26 05:39:30 PM PDT 24
Peak memory 194764 kb
Host smart-6c2ba323-0b9c-4e6d-a1d2-e482f60db1a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745894437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3745894437
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1927187073
Short name T448
Test name
Test status
Simulation time 499480160 ps
CPU time 5.63 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:45 PM PDT 24
Peak memory 198352 kb
Host smart-b1ad20bc-e80b-4694-9694-be4d4104c2be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927187073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1927187073
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.740954449
Short name T57
Test name
Test status
Simulation time 59248283 ps
CPU time 0.93 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 214376 kb
Host smart-90b973eb-f6ba-4906-aabe-8ef81290491a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740954449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.740954449
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3103296262
Short name T311
Test name
Test status
Simulation time 172642025 ps
CPU time 1.17 seconds
Started Jul 26 05:39:28 PM PDT 24
Finished Jul 26 05:39:29 PM PDT 24
Peak memory 198480 kb
Host smart-428717d3-c159-4f8f-abb4-6dbea504a5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103296262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3103296262
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3041822175
Short name T558
Test name
Test status
Simulation time 44575734 ps
CPU time 0.82 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 196308 kb
Host smart-662c93c3-6c8f-4632-8dc2-9cc0103ea2e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041822175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3041822175
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.468474139
Short name T193
Test name
Test status
Simulation time 6161503216 ps
CPU time 170.32 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:42:34 PM PDT 24
Peak memory 198568 kb
Host smart-fc59a700-7aa9-4c36-90fa-cbf0f828d97d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468474139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.468474139
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.766127900
Short name T405
Test name
Test status
Simulation time 19138724 ps
CPU time 0.58 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 194436 kb
Host smart-274f7f26-84a3-41be-ab96-7c5c75935b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766127900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.766127900
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1584340936
Short name T480
Test name
Test status
Simulation time 42954417 ps
CPU time 0.6 seconds
Started Jul 26 05:40:28 PM PDT 24
Finished Jul 26 05:40:29 PM PDT 24
Peak memory 194360 kb
Host smart-120beade-115d-4e19-98f6-9b388d016efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584340936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1584340936
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2926057628
Short name T596
Test name
Test status
Simulation time 3315425083 ps
CPU time 24.57 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:57 PM PDT 24
Peak memory 197044 kb
Host smart-8dacbbef-93dc-4a7e-939d-13348d8fb7cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926057628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2926057628
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1226457869
Short name T440
Test name
Test status
Simulation time 173595358 ps
CPU time 0.97 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 197640 kb
Host smart-32ecf12b-498a-4a85-a614-5db81df83fcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226457869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1226457869
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1882108817
Short name T456
Test name
Test status
Simulation time 158896612 ps
CPU time 1.18 seconds
Started Jul 26 05:40:31 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 196672 kb
Host smart-c3ef83a4-3426-45ff-ae95-e8118dde23eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882108817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1882108817
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.938427891
Short name T143
Test name
Test status
Simulation time 94270841 ps
CPU time 2.02 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:34 PM PDT 24
Peak memory 198504 kb
Host smart-b39a518f-b5ec-4a52-954a-9cf73077eb88
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938427891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.938427891
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.52652772
Short name T76
Test name
Test status
Simulation time 110390016 ps
CPU time 0.98 seconds
Started Jul 26 05:40:27 PM PDT 24
Finished Jul 26 05:40:28 PM PDT 24
Peak memory 196504 kb
Host smart-7fd6d4ba-8292-4037-b2be-83f5e6fa723d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52652772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.52652772
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1918317963
Short name T322
Test name
Test status
Simulation time 83003518 ps
CPU time 0.79 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 195812 kb
Host smart-190c1afd-c076-4930-9cf0-9a4940b7e5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918317963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1918317963
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1728314342
Short name T702
Test name
Test status
Simulation time 62515062 ps
CPU time 0.71 seconds
Started Jul 26 05:40:29 PM PDT 24
Finished Jul 26 05:40:30 PM PDT 24
Peak memory 194644 kb
Host smart-7eba8289-9af9-4514-afd8-bcef0a019d5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728314342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1728314342
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2228346758
Short name T8
Test name
Test status
Simulation time 223346834 ps
CPU time 2.52 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:35 PM PDT 24
Peak memory 198416 kb
Host smart-503dc7c4-55af-4a80-9b0e-e806bee4acdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228346758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2228346758
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.512707354
Short name T611
Test name
Test status
Simulation time 49563436 ps
CPU time 1.07 seconds
Started Jul 26 05:40:27 PM PDT 24
Finished Jul 26 05:40:28 PM PDT 24
Peak memory 196348 kb
Host smart-143f6514-c229-4779-aaf6-c8bb9c0e329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512707354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.512707354
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2106901675
Short name T279
Test name
Test status
Simulation time 35334417 ps
CPU time 1.05 seconds
Started Jul 26 05:40:29 PM PDT 24
Finished Jul 26 05:40:30 PM PDT 24
Peak memory 196040 kb
Host smart-6aaf6521-12da-4d60-8661-7f48d1cbcb89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106901675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2106901675
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1574949484
Short name T419
Test name
Test status
Simulation time 27330664615 ps
CPU time 193.62 seconds
Started Jul 26 05:40:25 PM PDT 24
Finished Jul 26 05:43:39 PM PDT 24
Peak memory 198592 kb
Host smart-0651685a-803b-4f3f-9c61-f2cbc8fb1003
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574949484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1574949484
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2452525463
Short name T706
Test name
Test status
Simulation time 57859007175 ps
CPU time 1502.23 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 06:05:35 PM PDT 24
Peak memory 199024 kb
Host smart-5449424f-7086-42e7-ba45-dbf23f141dc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2452525463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2452525463
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3145747469
Short name T711
Test name
Test status
Simulation time 12682901 ps
CPU time 0.61 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 194416 kb
Host smart-3d42b93d-5471-453c-8481-910d67a6fe3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145747469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3145747469
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1728860918
Short name T522
Test name
Test status
Simulation time 68406377 ps
CPU time 0.61 seconds
Started Jul 26 05:40:29 PM PDT 24
Finished Jul 26 05:40:30 PM PDT 24
Peak memory 194448 kb
Host smart-7cd99f54-6f2c-410e-a720-a022d64d1cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728860918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1728860918
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.671699568
Short name T237
Test name
Test status
Simulation time 1020361515 ps
CPU time 26.69 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:57 PM PDT 24
Peak memory 197216 kb
Host smart-af917a4b-94a9-46a4-ae6f-55fd0f8df836
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671699568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.671699568
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1977624084
Short name T291
Test name
Test status
Simulation time 96724649 ps
CPU time 1.07 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 197084 kb
Host smart-7eeae0dd-8795-4917-9931-f34b97e66629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977624084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1977624084
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2938093266
Short name T283
Test name
Test status
Simulation time 339534807 ps
CPU time 1.33 seconds
Started Jul 26 05:40:27 PM PDT 24
Finished Jul 26 05:40:29 PM PDT 24
Peak memory 197432 kb
Host smart-9de3d070-9c50-4597-84ff-03adc90449d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938093266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2938093266
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1645179380
Short name T18
Test name
Test status
Simulation time 119424750 ps
CPU time 2.78 seconds
Started Jul 26 05:40:28 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 198568 kb
Host smart-fd6db7d0-f09f-42ad-8f95-45c06e32cd99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645179380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1645179380
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3925148092
Short name T304
Test name
Test status
Simulation time 436571498 ps
CPU time 1 seconds
Started Jul 26 05:40:31 PM PDT 24
Finished Jul 26 05:40:32 PM PDT 24
Peak memory 195940 kb
Host smart-c8f41760-f828-4950-a076-0e68254bb500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925148092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3925148092
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2717197387
Short name T378
Test name
Test status
Simulation time 85441045 ps
CPU time 1.4 seconds
Started Jul 26 05:40:29 PM PDT 24
Finished Jul 26 05:40:31 PM PDT 24
Peak memory 197312 kb
Host smart-9372288e-b6b0-4dd7-b40e-1e8b3133ca3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717197387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2717197387
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.816124181
Short name T391
Test name
Test status
Simulation time 20790528 ps
CPU time 0.87 seconds
Started Jul 26 05:40:28 PM PDT 24
Finished Jul 26 05:40:29 PM PDT 24
Peak memory 197052 kb
Host smart-aa6d7ca3-2f9f-4180-a52c-691ba826d37b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816124181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.816124181
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2992026804
Short name T306
Test name
Test status
Simulation time 50410058 ps
CPU time 2.56 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:35 PM PDT 24
Peak memory 198448 kb
Host smart-bbe70d51-6d30-4c03-894d-322cc5367796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992026804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2992026804
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.666980507
Short name T604
Test name
Test status
Simulation time 58233421 ps
CPU time 1.26 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 197020 kb
Host smart-5eab6197-1396-4eff-8649-42fa3d5ae9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666980507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.666980507
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1207896717
Short name T31
Test name
Test status
Simulation time 178078409 ps
CPU time 1.15 seconds
Started Jul 26 05:40:33 PM PDT 24
Finished Jul 26 05:40:34 PM PDT 24
Peak memory 196228 kb
Host smart-12db3b83-0749-4d96-b9e3-0ff7e0733b32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207896717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1207896717
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.568430045
Short name T252
Test name
Test status
Simulation time 211226393520 ps
CPU time 180.1 seconds
Started Jul 26 05:40:30 PM PDT 24
Finished Jul 26 05:43:30 PM PDT 24
Peak memory 198640 kb
Host smart-252e06f2-1632-456b-8c29-690f1a3e7375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568430045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.568430045
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.302504976
Short name T242
Test name
Test status
Simulation time 71932361 ps
CPU time 0.58 seconds
Started Jul 26 05:40:41 PM PDT 24
Finished Jul 26 05:40:42 PM PDT 24
Peak memory 194364 kb
Host smart-5047e85b-0edb-45f4-99c4-3c247c221915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302504976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.302504976
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.361749522
Short name T350
Test name
Test status
Simulation time 49650449 ps
CPU time 0.98 seconds
Started Jul 26 05:40:42 PM PDT 24
Finished Jul 26 05:40:44 PM PDT 24
Peak memory 196316 kb
Host smart-0ac70513-242e-4153-a4c4-1ef96c472b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361749522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.361749522
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3990056040
Short name T601
Test name
Test status
Simulation time 302815444 ps
CPU time 15.48 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:40:59 PM PDT 24
Peak memory 197420 kb
Host smart-43a991f2-3780-4bf6-8248-f4c99ecffb4b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990056040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3990056040
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1483417700
Short name T725
Test name
Test status
Simulation time 50122704 ps
CPU time 0.81 seconds
Started Jul 26 05:40:42 PM PDT 24
Finished Jul 26 05:40:43 PM PDT 24
Peak memory 196176 kb
Host smart-4d106858-f1e8-486c-b857-c887488aebdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483417700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1483417700
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.4182460440
Short name T86
Test name
Test status
Simulation time 498700255 ps
CPU time 0.99 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:40:45 PM PDT 24
Peak memory 196616 kb
Host smart-e659df79-b244-4e6c-82f6-d4aa26f88427
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182460440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.4182460440
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3184948884
Short name T199
Test name
Test status
Simulation time 73098845 ps
CPU time 1.57 seconds
Started Jul 26 05:40:41 PM PDT 24
Finished Jul 26 05:40:42 PM PDT 24
Peak memory 196968 kb
Host smart-d5ae21ee-97ac-425a-b30f-4d38c3bd23f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184948884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3184948884
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2885471653
Short name T356
Test name
Test status
Simulation time 535847806 ps
CPU time 2.71 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 197712 kb
Host smart-af4ca62b-07c1-4adb-8556-5f45587df570
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885471653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2885471653
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1934757562
Short name T233
Test name
Test status
Simulation time 32215244 ps
CPU time 1.12 seconds
Started Jul 26 05:40:34 PM PDT 24
Finished Jul 26 05:40:36 PM PDT 24
Peak memory 196556 kb
Host smart-cccf91cd-29bf-4e46-a594-5df38f7631e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934757562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1934757562
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2159706191
Short name T331
Test name
Test status
Simulation time 52985473 ps
CPU time 1.27 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:34 PM PDT 24
Peak memory 198532 kb
Host smart-a9edd7d5-cdc1-4d6b-9a81-9c99994a036e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159706191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2159706191
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4037601150
Short name T130
Test name
Test status
Simulation time 178445035 ps
CPU time 4.23 seconds
Started Jul 26 05:40:42 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 198512 kb
Host smart-cffc2110-d8f7-4d49-9741-14162824dfdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037601150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.4037601150
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2750374809
Short name T177
Test name
Test status
Simulation time 99371451 ps
CPU time 1.5 seconds
Started Jul 26 05:40:31 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 197376 kb
Host smart-d0c7edb8-2ec7-488d-837b-26d97f276c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750374809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2750374809
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1415209122
Short name T476
Test name
Test status
Simulation time 72401028 ps
CPU time 1.22 seconds
Started Jul 26 05:40:32 PM PDT 24
Finished Jul 26 05:40:33 PM PDT 24
Peak memory 196180 kb
Host smart-6eda7ea4-e6e3-4eae-a2aa-2671004b4c71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415209122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1415209122
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.587305919
Short name T439
Test name
Test status
Simulation time 15203547163 ps
CPU time 157.03 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:43:21 PM PDT 24
Peak memory 198640 kb
Host smart-5f8919a7-d6f9-40fc-b3d6-7258822dffd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587305919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.587305919
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.794312531
Short name T74
Test name
Test status
Simulation time 366261269145 ps
CPU time 685.71 seconds
Started Jul 26 05:40:44 PM PDT 24
Finished Jul 26 05:52:10 PM PDT 24
Peak memory 207000 kb
Host smart-5aac40df-bd92-4d49-a68a-12323e750194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=794312531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.794312531
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3439191438
Short name T386
Test name
Test status
Simulation time 34300652 ps
CPU time 0.56 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:45 PM PDT 24
Peak memory 194404 kb
Host smart-1f1be432-abff-418c-9de8-8f501e3e0da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439191438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3439191438
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2712235738
Short name T629
Test name
Test status
Simulation time 143587680 ps
CPU time 0.79 seconds
Started Jul 26 05:40:42 PM PDT 24
Finished Jul 26 05:40:43 PM PDT 24
Peak memory 196672 kb
Host smart-e6eba69b-b13a-4234-85f0-e854a2d46fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712235738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2712235738
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1427278533
Short name T85
Test name
Test status
Simulation time 115975315 ps
CPU time 5.68 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 197420 kb
Host smart-a09907f3-edb3-4e40-af2a-9460cc95f8ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427278533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1427278533
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2046681519
Short name T568
Test name
Test status
Simulation time 133119564 ps
CPU time 0.63 seconds
Started Jul 26 05:40:46 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 194948 kb
Host smart-312919d4-bafa-4f7e-8773-44612adb5cf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046681519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2046681519
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.718603870
Short name T657
Test name
Test status
Simulation time 43770558 ps
CPU time 1.29 seconds
Started Jul 26 05:40:42 PM PDT 24
Finished Jul 26 05:40:44 PM PDT 24
Peak memory 196644 kb
Host smart-e435dc4a-4695-4eec-b511-d03e29c84b97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718603870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.718603870
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1240859008
Short name T158
Test name
Test status
Simulation time 78514064 ps
CPU time 3.2 seconds
Started Jul 26 05:40:41 PM PDT 24
Finished Jul 26 05:40:44 PM PDT 24
Peak memory 198600 kb
Host smart-1874c722-1467-497b-8b8a-9d3d2e2da0df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240859008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1240859008
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1547315919
Short name T128
Test name
Test status
Simulation time 47154284 ps
CPU time 1.14 seconds
Started Jul 26 05:40:44 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 196088 kb
Host smart-4d994c2b-091c-4935-857a-1104ad01b3e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547315919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1547315919
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1239240034
Short name T436
Test name
Test status
Simulation time 29309312 ps
CPU time 0.84 seconds
Started Jul 26 05:40:42 PM PDT 24
Finished Jul 26 05:40:44 PM PDT 24
Peak memory 197092 kb
Host smart-a1eab285-35a3-406d-ac17-50bcb97a03c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239240034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1239240034
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3994823152
Short name T641
Test name
Test status
Simulation time 44762116 ps
CPU time 1.04 seconds
Started Jul 26 05:40:41 PM PDT 24
Finished Jul 26 05:40:42 PM PDT 24
Peak memory 196352 kb
Host smart-ebad20a8-2afb-4e97-aa20-4cd5cfed7427
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994823152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3994823152
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3376545818
Short name T6
Test name
Test status
Simulation time 1411109034 ps
CPU time 5.05 seconds
Started Jul 26 05:40:42 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 198380 kb
Host smart-2ef76c94-fa9e-4f81-84b9-09d9209ba765
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376545818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3376545818
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.850177140
Short name T126
Test name
Test status
Simulation time 70964351 ps
CPU time 1.09 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:40:44 PM PDT 24
Peak memory 196008 kb
Host smart-3bcd8755-a08b-4cdf-9d7d-50d599d4a708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850177140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.850177140
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1349197813
Short name T529
Test name
Test status
Simulation time 163765779 ps
CPU time 1.36 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 198496 kb
Host smart-de6a4f49-72f7-4728-b749-fb88ee34ef60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349197813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1349197813
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.24552153
Short name T351
Test name
Test status
Simulation time 15726382238 ps
CPU time 102.79 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:42:26 PM PDT 24
Peak memory 198632 kb
Host smart-19f1dca1-70db-4843-ad8f-f57df21418f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24552153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gp
io_stress_all.24552153
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1346653069
Short name T677
Test name
Test status
Simulation time 60085853 ps
CPU time 0.59 seconds
Started Jul 26 05:40:42 PM PDT 24
Finished Jul 26 05:40:43 PM PDT 24
Peak memory 194340 kb
Host smart-ee93162b-f2c6-4439-bcf7-c6b433509010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346653069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1346653069
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4277185376
Short name T296
Test name
Test status
Simulation time 28937199 ps
CPU time 0.78 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 194628 kb
Host smart-c09ff676-6764-4a72-82b0-3beed2d54520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277185376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4277185376
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3692878904
Short name T295
Test name
Test status
Simulation time 392597130 ps
CPU time 3.89 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:53 PM PDT 24
Peak memory 196356 kb
Host smart-40d4a68f-a21b-409c-9e8c-0f07a28acb1a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692878904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3692878904
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.912568197
Short name T621
Test name
Test status
Simulation time 24727155 ps
CPU time 0.61 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 194620 kb
Host smart-78f1683a-d55c-439e-9352-c7fbe70c57d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912568197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.912568197
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.4273618334
Short name T682
Test name
Test status
Simulation time 230787303 ps
CPU time 1.41 seconds
Started Jul 26 05:40:44 PM PDT 24
Finished Jul 26 05:40:45 PM PDT 24
Peak memory 196360 kb
Host smart-7eb9c584-78d3-4a18-b74f-3570f9342597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273618334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.4273618334
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.608294247
Short name T129
Test name
Test status
Simulation time 355987669 ps
CPU time 3.51 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 198388 kb
Host smart-333ee72f-9e1e-4398-8ef0-20d87156f01d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608294247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.608294247
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1627805748
Short name T560
Test name
Test status
Simulation time 319317253 ps
CPU time 3.2 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 198564 kb
Host smart-fa45f051-f2ac-4ace-9aef-6ef69257684f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627805748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1627805748
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1993716319
Short name T244
Test name
Test status
Simulation time 99727871 ps
CPU time 1.14 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 195708 kb
Host smart-bd68fcf4-412e-40e4-a4c1-6895594b56ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993716319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1993716319
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1965060911
Short name T278
Test name
Test status
Simulation time 68952779 ps
CPU time 1.19 seconds
Started Jul 26 05:40:42 PM PDT 24
Finished Jul 26 05:40:43 PM PDT 24
Peak memory 196396 kb
Host smart-d216d5ee-863c-47bc-93ba-71f7d2139e17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965060911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1965060911
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2628448896
Short name T561
Test name
Test status
Simulation time 512134094 ps
CPU time 3 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 198504 kb
Host smart-e8a971ce-5ae4-46a7-ad6a-450ec7728112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628448896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2628448896
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1673464908
Short name T327
Test name
Test status
Simulation time 220759204 ps
CPU time 1.08 seconds
Started Jul 26 05:40:44 PM PDT 24
Finished Jul 26 05:40:45 PM PDT 24
Peak memory 196304 kb
Host smart-a1d3118d-582e-4c16-8ad8-3ff81528c832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673464908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1673464908
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3689635625
Short name T235
Test name
Test status
Simulation time 31000340 ps
CPU time 0.94 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 196744 kb
Host smart-3f564383-409a-48ef-a438-0069f7d598a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689635625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3689635625
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.540704406
Short name T338
Test name
Test status
Simulation time 2241602900 ps
CPU time 62.75 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:41:51 PM PDT 24
Peak memory 198572 kb
Host smart-65368133-f883-4911-9a29-f5b8a36d88cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540704406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.540704406
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3022823178
Short name T469
Test name
Test status
Simulation time 20246605 ps
CPU time 0.57 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 194304 kb
Host smart-339ab5ee-ce58-4dbc-a43d-178ccef5bea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022823178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3022823178
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2166778645
Short name T626
Test name
Test status
Simulation time 112034343 ps
CPU time 0.76 seconds
Started Jul 26 05:40:46 PM PDT 24
Finished Jul 26 05:40:47 PM PDT 24
Peak memory 196492 kb
Host smart-b35abce8-65f0-42a6-9f51-1e1915f0202e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166778645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2166778645
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4137104340
Short name T178
Test name
Test status
Simulation time 2333497514 ps
CPU time 20.5 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:41:11 PM PDT 24
Peak memory 197004 kb
Host smart-6c5cb380-cc6b-4b86-8b6a-e05ed63778b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137104340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4137104340
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2545140452
Short name T696
Test name
Test status
Simulation time 65692576 ps
CPU time 0.93 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 196952 kb
Host smart-24183c19-435b-41e9-91fc-873a41b19ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545140452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2545140452
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2232791603
Short name T63
Test name
Test status
Simulation time 214569956 ps
CPU time 1.28 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 197656 kb
Host smart-3fb5d1d2-c6d0-4fd5-b0b1-38cad7bed21f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232791603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2232791603
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3583086620
Short name T258
Test name
Test status
Simulation time 969630086 ps
CPU time 3.66 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:54 PM PDT 24
Peak memory 198560 kb
Host smart-8a30bd8e-12e5-4779-a886-52b9d0b6b23c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583086620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3583086620
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.655105244
Short name T162
Test name
Test status
Simulation time 152533185 ps
CPU time 2.34 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 198436 kb
Host smart-52939bf6-e813-4c59-a5db-a59bcc992acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655105244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
655105244
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3434941452
Short name T169
Test name
Test status
Simulation time 34774247 ps
CPU time 1.32 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 197380 kb
Host smart-d71c5f4b-290f-417b-9d82-7114c1944f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434941452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3434941452
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.952138409
Short name T707
Test name
Test status
Simulation time 33226209 ps
CPU time 0.79 seconds
Started Jul 26 05:40:46 PM PDT 24
Finished Jul 26 05:40:47 PM PDT 24
Peak memory 195896 kb
Host smart-f64ecdc8-aded-4902-b4a7-18cb230071b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952138409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.952138409
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3633517515
Short name T623
Test name
Test status
Simulation time 456720742 ps
CPU time 4.08 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 198448 kb
Host smart-da54db3e-096a-4b6d-9a18-6e98afb4464c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633517515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3633517515
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.533921065
Short name T209
Test name
Test status
Simulation time 32567340 ps
CPU time 0.77 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 195744 kb
Host smart-dcf9951b-c3aa-4002-8a21-c2bbfecd87ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533921065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.533921065
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.958687769
Short name T204
Test name
Test status
Simulation time 195820414 ps
CPU time 1.1 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 196256 kb
Host smart-ee7e6120-d418-4056-a454-983ea150c11b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958687769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.958687769
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2600813632
Short name T710
Test name
Test status
Simulation time 6166125371 ps
CPU time 74.95 seconds
Started Jul 26 05:40:56 PM PDT 24
Finished Jul 26 05:42:11 PM PDT 24
Peak memory 198644 kb
Host smart-86307d45-ca98-46db-82f4-3f80df90173f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600813632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2600813632
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3194160506
Short name T394
Test name
Test status
Simulation time 69587148606 ps
CPU time 223.27 seconds
Started Jul 26 05:40:56 PM PDT 24
Finished Jul 26 05:44:39 PM PDT 24
Peak memory 198752 kb
Host smart-2ea8afb8-529d-4807-bda9-fbd794d376d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3194160506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3194160506
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2251569489
Short name T417
Test name
Test status
Simulation time 33159186 ps
CPU time 0.57 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:40:43 PM PDT 24
Peak memory 194532 kb
Host smart-75b5a5f0-8189-42fb-86df-5da19aba9d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251569489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2251569489
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1931078755
Short name T240
Test name
Test status
Simulation time 107692237 ps
CPU time 0.85 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 196412 kb
Host smart-f793d03e-73e6-403f-80bd-e440d3c67927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931078755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1931078755
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.202439847
Short name T458
Test name
Test status
Simulation time 219585576 ps
CPU time 11.03 seconds
Started Jul 26 05:41:00 PM PDT 24
Finished Jul 26 05:41:11 PM PDT 24
Peak memory 197240 kb
Host smart-1d1c21e5-906e-4251-9859-7708f147f0c0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202439847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.202439847
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.4096124054
Short name T135
Test name
Test status
Simulation time 136246745 ps
CPU time 1 seconds
Started Jul 26 05:40:51 PM PDT 24
Finished Jul 26 05:40:52 PM PDT 24
Peak memory 198440 kb
Host smart-6cc7af11-1e76-4f14-91ac-88b56ea7bb27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096124054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.4096124054
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2729669137
Short name T224
Test name
Test status
Simulation time 94054322 ps
CPU time 1.52 seconds
Started Jul 26 05:40:52 PM PDT 24
Finished Jul 26 05:40:54 PM PDT 24
Peak memory 197372 kb
Host smart-250a8ad8-ee53-4c38-8a6f-2e4b22d1a588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729669137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2729669137
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1219067973
Short name T684
Test name
Test status
Simulation time 39350810 ps
CPU time 1.69 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 197208 kb
Host smart-093c2a40-dfd4-49ff-8dbc-ab186a91a922
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219067973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1219067973
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.132578338
Short name T375
Test name
Test status
Simulation time 456017642 ps
CPU time 2.33 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 198552 kb
Host smart-ce42894c-aa2a-4d86-b332-937b44997f01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132578338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
132578338
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2909031564
Short name T449
Test name
Test status
Simulation time 32788516 ps
CPU time 0.94 seconds
Started Jul 26 05:40:56 PM PDT 24
Finished Jul 26 05:40:57 PM PDT 24
Peak memory 197044 kb
Host smart-356898f7-be7d-4631-9502-7691b5763ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909031564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2909031564
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.830365720
Short name T124
Test name
Test status
Simulation time 18058569 ps
CPU time 0.78 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 195856 kb
Host smart-77097e82-3b8a-44f3-b974-d8ab93691bac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830365720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.830365720
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.935141684
Short name T474
Test name
Test status
Simulation time 355736368 ps
CPU time 6 seconds
Started Jul 26 05:40:53 PM PDT 24
Finished Jul 26 05:40:59 PM PDT 24
Peak memory 198496 kb
Host smart-9a7cb2f8-e2c1-4aab-9fcd-fc0121a4dfa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935141684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.935141684
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.811281223
Short name T671
Test name
Test status
Simulation time 32337956 ps
CPU time 0.9 seconds
Started Jul 26 05:40:56 PM PDT 24
Finished Jul 26 05:40:57 PM PDT 24
Peak memory 196900 kb
Host smart-4b80b145-9dec-4ca5-94fa-d9b8e0709c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811281223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.811281223
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.628205352
Short name T246
Test name
Test status
Simulation time 107093015 ps
CPU time 0.74 seconds
Started Jul 26 05:40:54 PM PDT 24
Finished Jul 26 05:40:55 PM PDT 24
Peak memory 195264 kb
Host smart-96f2fb8a-6428-4475-af28-c7c131d341cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628205352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.628205352
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2413094906
Short name T20
Test name
Test status
Simulation time 10838579331 ps
CPU time 111.97 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:42:42 PM PDT 24
Peak memory 198516 kb
Host smart-1833a7cf-0065-440f-b921-47170da1b433
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413094906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2413094906
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1174050249
Short name T484
Test name
Test status
Simulation time 18677758 ps
CPU time 0.63 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 195108 kb
Host smart-fa443288-240f-454d-a565-2de1bcd8e46c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174050249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1174050249
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.890379698
Short name T572
Test name
Test status
Simulation time 26921598 ps
CPU time 0.83 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:40:45 PM PDT 24
Peak memory 196636 kb
Host smart-9f45d390-5d4e-4e3c-8536-92aee44000ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890379698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.890379698
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3370096556
Short name T608
Test name
Test status
Simulation time 1427370719 ps
CPU time 12.44 seconds
Started Jul 26 05:40:44 PM PDT 24
Finished Jul 26 05:40:57 PM PDT 24
Peak memory 197396 kb
Host smart-7a954015-a576-46f0-b99a-a778464e0ab9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370096556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3370096556
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2087600117
Short name T403
Test name
Test status
Simulation time 116145478 ps
CPU time 0.85 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 196576 kb
Host smart-b781c92e-f7eb-4e0a-99a4-a2f4852128b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087600117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2087600117
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.675073949
Short name T503
Test name
Test status
Simulation time 37169499 ps
CPU time 0.99 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 196520 kb
Host smart-9e056e2d-a3ce-43d3-99e9-a12fc05c8761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675073949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.675073949
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3428890068
Short name T667
Test name
Test status
Simulation time 292021057 ps
CPU time 3.1 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:52 PM PDT 24
Peak memory 196984 kb
Host smart-351e520b-3955-4592-87bb-c0781a692847
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428890068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3428890068
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1090346114
Short name T358
Test name
Test status
Simulation time 155196955 ps
CPU time 2.69 seconds
Started Jul 26 05:40:46 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 196316 kb
Host smart-bcf597c5-74f9-49fc-9c98-f496ca2b6fa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090346114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1090346114
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.137537775
Short name T282
Test name
Test status
Simulation time 93659340 ps
CPU time 0.8 seconds
Started Jul 26 05:41:00 PM PDT 24
Finished Jul 26 05:41:01 PM PDT 24
Peak memory 195896 kb
Host smart-f8af0ae9-f0cc-40ce-96e3-d00b44115e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137537775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.137537775
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4255050398
Short name T526
Test name
Test status
Simulation time 33495426 ps
CPU time 0.81 seconds
Started Jul 26 05:40:44 PM PDT 24
Finished Jul 26 05:40:45 PM PDT 24
Peak memory 196044 kb
Host smart-3fce9abd-17c5-453d-9fd1-2293a238e6e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255050398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4255050398
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3039101668
Short name T348
Test name
Test status
Simulation time 137855295 ps
CPU time 3.3 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 198508 kb
Host smart-c00f7936-6582-4495-a424-495909e75995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039101668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3039101668
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3898393202
Short name T147
Test name
Test status
Simulation time 98821220 ps
CPU time 0.86 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 196304 kb
Host smart-34a726c0-c203-46dc-aa7e-6fbb2e026687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898393202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3898393202
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.279666879
Short name T67
Test name
Test status
Simulation time 233581458 ps
CPU time 1.12 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 196220 kb
Host smart-8ac008a5-f644-449c-87dc-33a84c611eea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279666879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.279666879
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1298360976
Short name T506
Test name
Test status
Simulation time 90596252328 ps
CPU time 122.11 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:42:51 PM PDT 24
Peak memory 198548 kb
Host smart-63abd778-41ac-4e41-ba01-3fb3d85a284b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298360976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1298360976
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3041810060
Short name T472
Test name
Test status
Simulation time 19285543 ps
CPU time 0.54 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 194396 kb
Host smart-4f11c020-a850-4ad8-b3c0-7b121121f843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041810060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3041810060
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1980489831
Short name T499
Test name
Test status
Simulation time 74391232 ps
CPU time 0.73 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 196400 kb
Host smart-b8d09dc3-f458-42c9-9f2a-02cf482382d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980489831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1980489831
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3113025455
Short name T231
Test name
Test status
Simulation time 231298434 ps
CPU time 12.43 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:41:01 PM PDT 24
Peak memory 196804 kb
Host smart-b751bd3c-403e-4a17-b2bb-56aed3d09f65
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113025455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3113025455
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1369303129
Short name T619
Test name
Test status
Simulation time 64174473 ps
CPU time 0.93 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 196304 kb
Host smart-fda7887a-2d65-4fe0-aaf3-3de2342bc744
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369303129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1369303129
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2273318023
Short name T266
Test name
Test status
Simulation time 141178469 ps
CPU time 0.77 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 195744 kb
Host smart-ec7cecb4-0ee6-4537-b529-233b5ca97d22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273318023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2273318023
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3503679942
Short name T669
Test name
Test status
Simulation time 251078528 ps
CPU time 1.74 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 198488 kb
Host smart-3b4f85c8-d4a2-40e8-9769-8ea2c6f78097
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503679942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3503679942
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3141003321
Short name T381
Test name
Test status
Simulation time 151364883 ps
CPU time 1.19 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 196800 kb
Host smart-c7c4fed1-4be1-41b9-ab4e-42244e103a4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141003321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3141003321
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1288345903
Short name T534
Test name
Test status
Simulation time 136626649 ps
CPU time 0.97 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 196232 kb
Host smart-3159c1d3-d8a2-4e82-9307-422cb4f4f37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288345903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1288345903
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.4048488358
Short name T154
Test name
Test status
Simulation time 124483950 ps
CPU time 0.9 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 197188 kb
Host smart-1bbed75c-925d-47d2-b2d9-32268d994a8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048488358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.4048488358
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2161396787
Short name T678
Test name
Test status
Simulation time 925226544 ps
CPU time 3.25 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:52 PM PDT 24
Peak memory 198504 kb
Host smart-8eb20757-5fb0-47a4-b8fe-65303a366c3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161396787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2161396787
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3129572910
Short name T632
Test name
Test status
Simulation time 68569744 ps
CPU time 1.06 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:47 PM PDT 24
Peak memory 196048 kb
Host smart-0660e987-9643-4649-bbb9-2937a1829a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129572910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3129572910
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2175243475
Short name T411
Test name
Test status
Simulation time 263724579 ps
CPU time 1.14 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 196732 kb
Host smart-6d201c0b-740d-4fca-b5cb-a485ca6d706f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175243475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2175243475
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.6046949
Short name T5
Test name
Test status
Simulation time 6686505456 ps
CPU time 71.31 seconds
Started Jul 26 05:40:46 PM PDT 24
Finished Jul 26 05:41:58 PM PDT 24
Peak memory 198584 kb
Host smart-210f1a52-688e-4087-8b74-13f6ff68845e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6046949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpi
o_stress_all.6046949
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1117991398
Short name T220
Test name
Test status
Simulation time 15458936 ps
CPU time 0.61 seconds
Started Jul 26 05:40:56 PM PDT 24
Finished Jul 26 05:40:56 PM PDT 24
Peak memory 195344 kb
Host smart-8f00d003-3df7-47b9-96b9-e5f03fbaec8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117991398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1117991398
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1204910283
Short name T139
Test name
Test status
Simulation time 23562022 ps
CPU time 0.77 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 195876 kb
Host smart-6215569e-bce0-4f07-abf1-5c841b3066a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204910283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1204910283
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.910875182
Short name T398
Test name
Test status
Simulation time 554125175 ps
CPU time 15.77 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:41:03 PM PDT 24
Peak memory 198536 kb
Host smart-c31dd16f-0102-4be6-855e-80706d30485c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910875182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.910875182
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2596458480
Short name T699
Test name
Test status
Simulation time 27270575 ps
CPU time 0.67 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 195672 kb
Host smart-ffa8baee-24dd-4e2e-97dd-8ba224ec700b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596458480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2596458480
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2318213444
Short name T131
Test name
Test status
Simulation time 35513893 ps
CPU time 1.03 seconds
Started Jul 26 05:40:51 PM PDT 24
Finished Jul 26 05:40:52 PM PDT 24
Peak memory 196288 kb
Host smart-4bf351ad-140f-44e9-8d00-d7e24bcdf443
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318213444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2318213444
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3889453415
Short name T213
Test name
Test status
Simulation time 104855975 ps
CPU time 2.16 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 198492 kb
Host smart-f8eedc0a-c14c-4509-b65d-2ba70b0162d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889453415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3889453415
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1686869540
Short name T366
Test name
Test status
Simulation time 147154032 ps
CPU time 2.96 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:53 PM PDT 24
Peak memory 198464 kb
Host smart-52b94bf4-a8ec-4074-a6f1-1e4912cb6603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686869540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1686869540
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3187224878
Short name T720
Test name
Test status
Simulation time 41729596 ps
CPU time 0.93 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:52 PM PDT 24
Peak memory 196540 kb
Host smart-c66b2940-545f-41ae-b0c2-4858965d7977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187224878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3187224878
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1088203948
Short name T541
Test name
Test status
Simulation time 27688894 ps
CPU time 1.09 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 196396 kb
Host smart-35ba1634-9aaa-4ecd-88ce-81c08df18d22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088203948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1088203948
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2890115466
Short name T587
Test name
Test status
Simulation time 952932054 ps
CPU time 2.37 seconds
Started Jul 26 05:40:52 PM PDT 24
Finished Jul 26 05:40:55 PM PDT 24
Peak memory 198328 kb
Host smart-30b99390-37f9-42d0-8630-4e95d2e348d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890115466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2890115466
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3440053840
Short name T132
Test name
Test status
Simulation time 150363100 ps
CPU time 0.92 seconds
Started Jul 26 05:40:51 PM PDT 24
Finished Jul 26 05:40:53 PM PDT 24
Peak memory 196532 kb
Host smart-2e6e1dcc-158b-4142-bade-c58e13cc0688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440053840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3440053840
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3021259405
Short name T432
Test name
Test status
Simulation time 49889707 ps
CPU time 1.1 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 196100 kb
Host smart-640c0356-0467-452a-8a02-153f22896bd9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021259405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3021259405
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.259220059
Short name T606
Test name
Test status
Simulation time 11675711353 ps
CPU time 72.35 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:42:00 PM PDT 24
Peak memory 198644 kb
Host smart-f3db4141-bf5b-4893-968c-8cf2e24cc2a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259220059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.259220059
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2217004778
Short name T72
Test name
Test status
Simulation time 21745645070 ps
CPU time 608.13 seconds
Started Jul 26 05:40:56 PM PDT 24
Finished Jul 26 05:51:04 PM PDT 24
Peak memory 198764 kb
Host smart-60577557-a780-4ccc-8cc4-ff999cebb82d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2217004778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2217004778
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2636194743
Short name T12
Test name
Test status
Simulation time 22162136 ps
CPU time 0.58 seconds
Started Jul 26 05:39:47 PM PDT 24
Finished Jul 26 05:39:48 PM PDT 24
Peak memory 195116 kb
Host smart-862af7f3-0e12-4693-981a-d0648b8ab31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636194743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2636194743
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3859565409
Short name T335
Test name
Test status
Simulation time 113639080 ps
CPU time 0.9 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 197052 kb
Host smart-60ac7f77-66db-46b5-88c1-b6696077420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859565409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3859565409
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3630032361
Short name T16
Test name
Test status
Simulation time 421168073 ps
CPU time 14.77 seconds
Started Jul 26 05:39:34 PM PDT 24
Finished Jul 26 05:39:49 PM PDT 24
Peak memory 197036 kb
Host smart-9ed2b668-b2df-466b-bad2-a9aba81ffa5d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630032361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3630032361
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1382011548
Short name T342
Test name
Test status
Simulation time 167483820 ps
CPU time 0.92 seconds
Started Jul 26 05:39:40 PM PDT 24
Finished Jul 26 05:39:41 PM PDT 24
Peak memory 197564 kb
Host smart-37150881-b209-4dfc-9939-f8bacffeb9e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382011548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1382011548
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2205254810
Short name T496
Test name
Test status
Simulation time 107296732 ps
CPU time 1.04 seconds
Started Jul 26 05:39:37 PM PDT 24
Finished Jul 26 05:39:38 PM PDT 24
Peak memory 197012 kb
Host smart-7961bd4f-799b-4918-b514-6751ff76c9c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205254810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2205254810
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1087483325
Short name T609
Test name
Test status
Simulation time 105685001 ps
CPU time 2.16 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:41 PM PDT 24
Peak memory 198580 kb
Host smart-4aeec228-801e-43ed-8257-2204b02799c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087483325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1087483325
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3208341874
Short name T290
Test name
Test status
Simulation time 92979825 ps
CPU time 2.22 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:45 PM PDT 24
Peak memory 198488 kb
Host smart-0a7e3ae3-4e53-43af-8c5d-919692597944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208341874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3208341874
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.994197229
Short name T540
Test name
Test status
Simulation time 32161573 ps
CPU time 1.09 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 196332 kb
Host smart-9816f5d5-2e19-4207-84c9-43b769f8b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994197229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.994197229
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.890632830
Short name T170
Test name
Test status
Simulation time 181282767 ps
CPU time 1.17 seconds
Started Jul 26 05:39:36 PM PDT 24
Finished Jul 26 05:39:38 PM PDT 24
Peak memory 197220 kb
Host smart-1e611398-c98f-4586-b4a8-88467e74828d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890632830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.890632830
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1036284932
Short name T512
Test name
Test status
Simulation time 593113843 ps
CPU time 3.6 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:42 PM PDT 24
Peak memory 197676 kb
Host smart-c7e57a3e-4ad0-4624-b7a3-f0c49fa3ebbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036284932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1036284932
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2533702021
Short name T47
Test name
Test status
Simulation time 55720910 ps
CPU time 0.89 seconds
Started Jul 26 05:39:53 PM PDT 24
Finished Jul 26 05:39:54 PM PDT 24
Peak memory 214472 kb
Host smart-8087ad55-f310-439e-b6f8-38603b435992
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533702021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2533702021
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2639430603
Short name T408
Test name
Test status
Simulation time 60764848 ps
CPU time 1.24 seconds
Started Jul 26 05:39:37 PM PDT 24
Finished Jul 26 05:39:39 PM PDT 24
Peak memory 196944 kb
Host smart-e21f6e6f-6a17-423c-802e-985faddf9ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639430603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2639430603
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1868063146
Short name T493
Test name
Test status
Simulation time 51721726 ps
CPU time 0.81 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 195612 kb
Host smart-35bab67a-b88f-49b7-8b10-5d26688b512d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868063146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1868063146
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1739784093
Short name T9
Test name
Test status
Simulation time 34142239037 ps
CPU time 194.38 seconds
Started Jul 26 05:39:48 PM PDT 24
Finished Jul 26 05:43:02 PM PDT 24
Peak memory 198572 kb
Host smart-02c1994b-a9f6-4c3b-b465-26ced97d697c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739784093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1739784093
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2716658172
Short name T468
Test name
Test status
Simulation time 15507592 ps
CPU time 0.65 seconds
Started Jul 26 05:40:44 PM PDT 24
Finished Jul 26 05:40:45 PM PDT 24
Peak memory 194420 kb
Host smart-97aae0e4-2c29-4b55-bf52-bcd4c9510ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716658172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2716658172
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1451676925
Short name T61
Test name
Test status
Simulation time 65343347 ps
CPU time 0.99 seconds
Started Jul 26 05:40:53 PM PDT 24
Finished Jul 26 05:40:54 PM PDT 24
Peak memory 196404 kb
Host smart-c29f54ac-c3dd-40a2-86d3-b02b4c5a0be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451676925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1451676925
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2892136898
Short name T35
Test name
Test status
Simulation time 347835719 ps
CPU time 16.67 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:41:06 PM PDT 24
Peak memory 196004 kb
Host smart-60bdaa35-039e-4c0e-9e47-1ad733c0d874
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892136898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2892136898
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1294390360
Short name T407
Test name
Test status
Simulation time 164489322 ps
CPU time 1.03 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 197088 kb
Host smart-d7b55eed-62de-42f7-bff5-637eb6d5ef84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294390360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1294390360
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3472576354
Short name T454
Test name
Test status
Simulation time 197220355 ps
CPU time 1.04 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 197268 kb
Host smart-08b4c9af-423c-4979-9807-af0925635241
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472576354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3472576354
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3643012998
Short name T600
Test name
Test status
Simulation time 92071123 ps
CPU time 3.58 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:40:53 PM PDT 24
Peak memory 198412 kb
Host smart-b4c537a1-5b6b-4ad5-b581-f11894e6f272
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643012998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3643012998
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.4133677246
Short name T444
Test name
Test status
Simulation time 126813814 ps
CPU time 3.74 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:40:53 PM PDT 24
Peak memory 198504 kb
Host smart-b9577851-94ef-4101-b3c2-9dd2480921df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133677246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.4133677246
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.718694814
Short name T639
Test name
Test status
Simulation time 37327070 ps
CPU time 1.02 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 197052 kb
Host smart-9fe2670b-7d84-42ba-9975-19c84b9f0ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718694814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.718694814
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.323195873
Short name T228
Test name
Test status
Simulation time 52514154 ps
CPU time 1.01 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:40:44 PM PDT 24
Peak memory 196524 kb
Host smart-821a7f36-a07d-4b67-afbb-e587a7477028
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323195873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.323195873
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2670673669
Short name T689
Test name
Test status
Simulation time 268197151 ps
CPU time 1.42 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 198384 kb
Host smart-fc05bce4-9f54-4f9e-ab71-15f99956fae7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670673669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2670673669
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.162671915
Short name T577
Test name
Test status
Simulation time 337225329 ps
CPU time 1.26 seconds
Started Jul 26 05:40:50 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 196220 kb
Host smart-85bc65b5-32e7-42c8-bbae-fee11c8ea28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162671915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.162671915
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2560321347
Short name T292
Test name
Test status
Simulation time 239509610 ps
CPU time 1.07 seconds
Started Jul 26 05:40:53 PM PDT 24
Finished Jul 26 05:40:54 PM PDT 24
Peak memory 196800 kb
Host smart-994a7d08-d192-4124-9c99-d688ad397fd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560321347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2560321347
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2191478718
Short name T239
Test name
Test status
Simulation time 13186941925 ps
CPU time 47.98 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:41:33 PM PDT 24
Peak memory 198508 kb
Host smart-f9406be0-4c71-4a77-94ce-8603658e91b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191478718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2191478718
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1284174062
Short name T648
Test name
Test status
Simulation time 14990086317 ps
CPU time 253.59 seconds
Started Jul 26 05:40:46 PM PDT 24
Finished Jul 26 05:45:00 PM PDT 24
Peak memory 198752 kb
Host smart-05ed867c-4718-4247-a28f-20810225b308
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1284174062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1284174062
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.330331394
Short name T511
Test name
Test status
Simulation time 42225778 ps
CPU time 0.61 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:47 PM PDT 24
Peak memory 194436 kb
Host smart-8421f6cb-4046-4375-a63f-fee42421a6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330331394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.330331394
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2066313649
Short name T373
Test name
Test status
Simulation time 183358930 ps
CPU time 0.74 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 196544 kb
Host smart-36e49c75-e125-4486-8de5-f805e079b7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066313649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2066313649
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3970837651
Short name T450
Test name
Test status
Simulation time 920492203 ps
CPU time 5.51 seconds
Started Jul 26 05:40:44 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 196792 kb
Host smart-89cb6f15-8d61-437d-ae62-a920c5833d6f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970837651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3970837651
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1504950725
Short name T627
Test name
Test status
Simulation time 620645323 ps
CPU time 0.71 seconds
Started Jul 26 05:40:49 PM PDT 24
Finished Jul 26 05:40:50 PM PDT 24
Peak memory 195108 kb
Host smart-fc7d3fbd-3742-4873-a45f-2f1af211085b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504950725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1504950725
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.34731279
Short name T516
Test name
Test status
Simulation time 218085060 ps
CPU time 1.27 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 195924 kb
Host smart-cc41e3ff-0ad9-4d48-aaf5-1e6a644a2380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34731279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.34731279
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1495164951
Short name T353
Test name
Test status
Simulation time 325820839 ps
CPU time 3.41 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 198696 kb
Host smart-1e8ddab6-379a-4a99-ae8b-88db0444c68a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495164951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1495164951
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3319986573
Short name T340
Test name
Test status
Simulation time 43466123 ps
CPU time 1.05 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 196064 kb
Host smart-0397ce43-f3cc-4f6f-842d-a30e7450e7e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319986573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3319986573
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.104216621
Short name T642
Test name
Test status
Simulation time 224809436 ps
CPU time 1.28 seconds
Started Jul 26 05:40:45 PM PDT 24
Finished Jul 26 05:40:46 PM PDT 24
Peak memory 197512 kb
Host smart-5e27aa26-261d-4a94-93c3-cdd0b8bdb904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104216621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.104216621
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2120568067
Short name T344
Test name
Test status
Simulation time 103183151 ps
CPU time 1.15 seconds
Started Jul 26 05:40:46 PM PDT 24
Finished Jul 26 05:40:48 PM PDT 24
Peak memory 196476 kb
Host smart-417322cd-c33b-49cb-9384-85d24a86a60f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120568067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2120568067
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.684321771
Short name T364
Test name
Test status
Simulation time 2426321072 ps
CPU time 2.04 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:40:51 PM PDT 24
Peak memory 198540 kb
Host smart-21eddff6-862c-4b94-89cc-bc4ec01a0b9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684321771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.684321771
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.749221246
Short name T68
Test name
Test status
Simulation time 459654587 ps
CPU time 1.53 seconds
Started Jul 26 05:40:44 PM PDT 24
Finished Jul 26 05:40:45 PM PDT 24
Peak memory 198496 kb
Host smart-ad96c3d0-e7e6-47ec-9a28-dbe70e7cb5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749221246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.749221246
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2690416503
Short name T583
Test name
Test status
Simulation time 161320606 ps
CPU time 1.36 seconds
Started Jul 26 05:40:43 PM PDT 24
Finished Jul 26 05:40:45 PM PDT 24
Peak memory 197088 kb
Host smart-a4f4baf4-2ddb-42d5-8168-5ff27e0c102b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690416503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2690416503
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2960828009
Short name T78
Test name
Test status
Simulation time 12152386160 ps
CPU time 157.63 seconds
Started Jul 26 05:40:47 PM PDT 24
Finished Jul 26 05:43:24 PM PDT 24
Peak memory 198564 kb
Host smart-b36296c2-2f32-4be2-8b06-1083c49d9ddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960828009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2960828009
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3953273241
Short name T185
Test name
Test status
Simulation time 14560214 ps
CPU time 0.6 seconds
Started Jul 26 05:41:03 PM PDT 24
Finished Jul 26 05:41:04 PM PDT 24
Peak memory 195116 kb
Host smart-4d808845-56d9-4a38-9741-26ca9a656732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953273241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3953273241
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3921927907
Short name T286
Test name
Test status
Simulation time 24641783 ps
CPU time 0.71 seconds
Started Jul 26 05:40:56 PM PDT 24
Finished Jul 26 05:40:57 PM PDT 24
Peak memory 195408 kb
Host smart-29098247-aa93-43d1-8773-539acfde66ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921927907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3921927907
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3208988142
Short name T665
Test name
Test status
Simulation time 2390430774 ps
CPU time 10.48 seconds
Started Jul 26 05:40:52 PM PDT 24
Finished Jul 26 05:41:03 PM PDT 24
Peak memory 197152 kb
Host smart-3a96ed98-737f-4ec8-813c-6f475b29abe9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208988142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3208988142
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.4023775910
Short name T298
Test name
Test status
Simulation time 417125107 ps
CPU time 0.91 seconds
Started Jul 26 05:40:54 PM PDT 24
Finished Jul 26 05:40:55 PM PDT 24
Peak memory 197416 kb
Host smart-98a1f2ad-54df-48fb-a096-3705e34c8745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023775910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4023775910
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.4154918791
Short name T507
Test name
Test status
Simulation time 16450034 ps
CPU time 0.7 seconds
Started Jul 26 05:41:03 PM PDT 24
Finished Jul 26 05:41:04 PM PDT 24
Peak memory 194804 kb
Host smart-319d8644-1fbb-446b-aec9-20c7b5fa9c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154918791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.4154918791
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1104639530
Short name T152
Test name
Test status
Simulation time 100148338 ps
CPU time 3.76 seconds
Started Jul 26 05:41:01 PM PDT 24
Finished Jul 26 05:41:05 PM PDT 24
Peak memory 198500 kb
Host smart-bd531d11-6afa-4335-820b-928511ef4e23
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104639530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1104639530
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2354982898
Short name T319
Test name
Test status
Simulation time 557307003 ps
CPU time 2.95 seconds
Started Jul 26 05:41:01 PM PDT 24
Finished Jul 26 05:41:04 PM PDT 24
Peak memory 197816 kb
Host smart-a1babc4d-1354-471b-85f7-599e7c05fc0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354982898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2354982898
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3272889850
Short name T467
Test name
Test status
Simulation time 21616608 ps
CPU time 0.86 seconds
Started Jul 26 05:40:53 PM PDT 24
Finished Jul 26 05:40:54 PM PDT 24
Peak memory 197872 kb
Host smart-f3a01422-39b8-4b01-b633-ae677941a527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272889850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3272889850
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2945525604
Short name T313
Test name
Test status
Simulation time 89460871 ps
CPU time 0.98 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:06 PM PDT 24
Peak memory 196400 kb
Host smart-f3c291d5-7a74-4483-97f2-e1ef8ff61c1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945525604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2945525604
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3736147592
Short name T191
Test name
Test status
Simulation time 270759192 ps
CPU time 4.65 seconds
Started Jul 26 05:41:03 PM PDT 24
Finished Jul 26 05:41:07 PM PDT 24
Peak memory 198400 kb
Host smart-ca5829f5-7075-405d-a923-975bb0431da0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736147592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3736147592
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2428785590
Short name T581
Test name
Test status
Simulation time 130476168 ps
CPU time 0.84 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:49 PM PDT 24
Peak memory 196816 kb
Host smart-a5854846-2d53-4767-9f99-86bc7867380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428785590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2428785590
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3205075251
Short name T205
Test name
Test status
Simulation time 308066743 ps
CPU time 0.85 seconds
Started Jul 26 05:40:48 PM PDT 24
Finished Jul 26 05:40:54 PM PDT 24
Peak memory 195608 kb
Host smart-48305456-c6c8-4033-9ce5-359a438afcee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205075251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3205075251
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1190450163
Short name T429
Test name
Test status
Simulation time 16569749200 ps
CPU time 117.04 seconds
Started Jul 26 05:40:56 PM PDT 24
Finished Jul 26 05:42:53 PM PDT 24
Peak memory 198652 kb
Host smart-ed16f2bd-7b0b-4629-a0dd-51734e786d47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190450163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1190450163
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.466918674
Short name T580
Test name
Test status
Simulation time 114479334 ps
CPU time 0.57 seconds
Started Jul 26 05:41:04 PM PDT 24
Finished Jul 26 05:41:05 PM PDT 24
Peak memory 195124 kb
Host smart-da12a48e-b215-4eb1-838b-73cd3e336008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466918674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.466918674
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3289581486
Short name T441
Test name
Test status
Simulation time 611932621 ps
CPU time 0.96 seconds
Started Jul 26 05:40:54 PM PDT 24
Finished Jul 26 05:40:55 PM PDT 24
Peak memory 196228 kb
Host smart-a8e0783b-fe6c-484b-8f5d-590b1557763a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289581486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3289581486
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2127182812
Short name T372
Test name
Test status
Simulation time 326511311 ps
CPU time 8.04 seconds
Started Jul 26 05:41:06 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 197416 kb
Host smart-0d3ee7be-c471-45e0-be41-12e6b98083c0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127182812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2127182812
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.913758751
Short name T323
Test name
Test status
Simulation time 508092109 ps
CPU time 0.92 seconds
Started Jul 26 05:40:57 PM PDT 24
Finished Jul 26 05:40:58 PM PDT 24
Peak memory 196496 kb
Host smart-3fc52367-ed98-4de9-956a-c953081d853d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913758751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.913758751
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1302167870
Short name T438
Test name
Test status
Simulation time 47569178 ps
CPU time 0.68 seconds
Started Jul 26 05:41:03 PM PDT 24
Finished Jul 26 05:41:04 PM PDT 24
Peak memory 195624 kb
Host smart-7eab1e1a-0914-4789-a384-7d1eb8b60367
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302167870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1302167870
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1165648133
Short name T646
Test name
Test status
Simulation time 87452446 ps
CPU time 1.21 seconds
Started Jul 26 05:40:59 PM PDT 24
Finished Jul 26 05:41:00 PM PDT 24
Peak memory 198548 kb
Host smart-aeed4389-6521-407c-8d72-d45e3a8944f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165648133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1165648133
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4233827068
Short name T542
Test name
Test status
Simulation time 317669973 ps
CPU time 3.45 seconds
Started Jul 26 05:41:06 PM PDT 24
Finished Jul 26 05:41:09 PM PDT 24
Peak memory 197388 kb
Host smart-e40bcecf-f1ed-4d57-a23d-5df6635f2c01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233827068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4233827068
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3064658207
Short name T329
Test name
Test status
Simulation time 50156399 ps
CPU time 0.87 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 05:41:08 PM PDT 24
Peak memory 197148 kb
Host smart-8570f451-7e18-4380-9f6a-c63686d441de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064658207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3064658207
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3036153058
Short name T592
Test name
Test status
Simulation time 69787798 ps
CPU time 0.89 seconds
Started Jul 26 05:40:56 PM PDT 24
Finished Jul 26 05:40:57 PM PDT 24
Peak memory 197056 kb
Host smart-2c863113-17c2-4c5b-ab4b-84a91bdc182e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036153058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3036153058
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.4280410307
Short name T289
Test name
Test status
Simulation time 119260479 ps
CPU time 1.25 seconds
Started Jul 26 05:40:58 PM PDT 24
Finished Jul 26 05:41:00 PM PDT 24
Peak memory 198436 kb
Host smart-78215d0c-9c6f-4f77-aea6-805772e33f22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280410307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.4280410307
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2988321395
Short name T368
Test name
Test status
Simulation time 45492683 ps
CPU time 0.96 seconds
Started Jul 26 05:40:58 PM PDT 24
Finished Jul 26 05:40:59 PM PDT 24
Peak memory 196648 kb
Host smart-d3c47cd5-9e4e-46c1-851e-58b7a448e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988321395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2988321395
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3812557255
Short name T543
Test name
Test status
Simulation time 203511190 ps
CPU time 0.99 seconds
Started Jul 26 05:41:06 PM PDT 24
Finished Jul 26 05:41:08 PM PDT 24
Peak memory 196140 kb
Host smart-91a79107-c9aa-48f9-98b1-dac6008be2bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812557255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3812557255
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.88643317
Short name T167
Test name
Test status
Simulation time 2031545875 ps
CPU time 52.61 seconds
Started Jul 26 05:40:57 PM PDT 24
Finished Jul 26 05:41:50 PM PDT 24
Peak memory 192192 kb
Host smart-ec29b60f-5c8f-4a6b-80b6-48dd1ed08230
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88643317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gp
io_stress_all.88643317
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3035818464
Short name T559
Test name
Test status
Simulation time 32403569 ps
CPU time 0.54 seconds
Started Jul 26 05:41:06 PM PDT 24
Finished Jul 26 05:41:06 PM PDT 24
Peak memory 194396 kb
Host smart-258e5dec-7da6-429c-a910-381044cbf317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035818464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3035818464
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2941821075
Short name T352
Test name
Test status
Simulation time 114492434 ps
CPU time 0.9 seconds
Started Jul 26 05:40:59 PM PDT 24
Finished Jul 26 05:41:00 PM PDT 24
Peak memory 196996 kb
Host smart-5b6ef86b-3ad4-4cf7-b30d-141f5e8d7fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941821075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2941821075
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3888370802
Short name T150
Test name
Test status
Simulation time 9868850646 ps
CPU time 26.52 seconds
Started Jul 26 05:41:03 PM PDT 24
Finished Jul 26 05:41:30 PM PDT 24
Peak memory 197504 kb
Host smart-6e187a13-a264-4949-92ee-9a6ddc9b48a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888370802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3888370802
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2849322708
Short name T515
Test name
Test status
Simulation time 55068272 ps
CPU time 0.92 seconds
Started Jul 26 05:41:03 PM PDT 24
Finished Jul 26 05:41:04 PM PDT 24
Peak memory 196372 kb
Host smart-a9f03070-86ce-4d36-b30e-4449372088b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849322708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2849322708
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.899192665
Short name T500
Test name
Test status
Simulation time 178042394 ps
CPU time 1.38 seconds
Started Jul 26 05:41:00 PM PDT 24
Finished Jul 26 05:41:01 PM PDT 24
Peak memory 197496 kb
Host smart-8a71b5e5-d6da-4ad3-a4f5-a8aef16bb4fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899192665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.899192665
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2193194954
Short name T257
Test name
Test status
Simulation time 41189434 ps
CPU time 1.67 seconds
Started Jul 26 05:40:58 PM PDT 24
Finished Jul 26 05:41:00 PM PDT 24
Peak memory 197284 kb
Host smart-26c5802b-d1b8-4f7b-b33c-3c7cceaa049b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193194954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2193194954
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2801951753
Short name T616
Test name
Test status
Simulation time 64572531 ps
CPU time 2.23 seconds
Started Jul 26 05:41:03 PM PDT 24
Finished Jul 26 05:41:05 PM PDT 24
Peak memory 197472 kb
Host smart-5274e1be-d5ac-4252-bd28-089cfd7489d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801951753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2801951753
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3838524808
Short name T442
Test name
Test status
Simulation time 46754877 ps
CPU time 0.78 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:06 PM PDT 24
Peak memory 196596 kb
Host smart-7663b43b-e63b-4715-a7b4-9e7e79493d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838524808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3838524808
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2853728810
Short name T508
Test name
Test status
Simulation time 14438823 ps
CPU time 0.71 seconds
Started Jul 26 05:40:58 PM PDT 24
Finished Jul 26 05:40:59 PM PDT 24
Peak memory 194724 kb
Host smart-1815d8ac-d752-46f3-926a-d0d3c9243f7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853728810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2853728810
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1328645155
Short name T320
Test name
Test status
Simulation time 228592083 ps
CPU time 3.67 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:09 PM PDT 24
Peak memory 198384 kb
Host smart-d6eff7c6-6a8e-4fc7-81b5-29b68e89e7a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328645155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1328645155
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3782060408
Short name T354
Test name
Test status
Simulation time 22751174 ps
CPU time 0.77 seconds
Started Jul 26 05:41:06 PM PDT 24
Finished Jul 26 05:41:07 PM PDT 24
Peak memory 195728 kb
Host smart-8e51cc07-ca00-4e52-9e19-2cc9ef549dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782060408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3782060408
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3284251683
Short name T690
Test name
Test status
Simulation time 184948896 ps
CPU time 1.38 seconds
Started Jul 26 05:41:02 PM PDT 24
Finished Jul 26 05:41:04 PM PDT 24
Peak memory 196128 kb
Host smart-83654d27-91ea-48bd-abb1-c85ff38224d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284251683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3284251683
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3745451534
Short name T660
Test name
Test status
Simulation time 20227348738 ps
CPU time 71.85 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:42:17 PM PDT 24
Peak memory 198612 kb
Host smart-250be845-77b8-48f7-b19c-acf5b12ba6ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745451534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3745451534
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.595473295
Short name T390
Test name
Test status
Simulation time 248871271351 ps
CPU time 896.43 seconds
Started Jul 26 05:41:02 PM PDT 24
Finished Jul 26 05:55:58 PM PDT 24
Peak memory 206884 kb
Host smart-c89f21ed-b549-4602-a993-3b2a9cc7ea59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=595473295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.595473295
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.817691871
Short name T49
Test name
Test status
Simulation time 12444138 ps
CPU time 0.56 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 05:41:07 PM PDT 24
Peak memory 195140 kb
Host smart-1e2c3b29-89ec-4717-806f-2e9774242866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817691871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.817691871
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3062721103
Short name T337
Test name
Test status
Simulation time 29088362 ps
CPU time 0.69 seconds
Started Jul 26 05:41:14 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 195708 kb
Host smart-adc20359-7f37-47ca-a0dd-ebe3432a6837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062721103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3062721103
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1869239651
Short name T256
Test name
Test status
Simulation time 1738139432 ps
CPU time 20.26 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 05:41:28 PM PDT 24
Peak memory 197312 kb
Host smart-901020b8-0e2c-442c-99a3-1f4eaf0c8861
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869239651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1869239651
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2220860524
Short name T219
Test name
Test status
Simulation time 61929170 ps
CPU time 0.69 seconds
Started Jul 26 05:40:58 PM PDT 24
Finished Jul 26 05:40:59 PM PDT 24
Peak memory 195004 kb
Host smart-effb23df-acc6-4c48-909c-1b05a72ff692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220860524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2220860524
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.659097856
Short name T478
Test name
Test status
Simulation time 58765760 ps
CPU time 0.81 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:06 PM PDT 24
Peak memory 196016 kb
Host smart-ed71a272-73a7-472c-9bf9-3eca57e774e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659097856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.659097856
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2639953262
Short name T410
Test name
Test status
Simulation time 547140788 ps
CPU time 2.79 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:08 PM PDT 24
Peak memory 198636 kb
Host smart-e9e8ee67-b5ec-4106-a9e9-62eee9fd30fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639953262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2639953262
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.372801375
Short name T218
Test name
Test status
Simulation time 339501746 ps
CPU time 2.64 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 05:41:10 PM PDT 24
Peak memory 197696 kb
Host smart-e00d22b5-00fc-40df-b443-b6c89d3e2854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372801375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
372801375
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1471384483
Short name T24
Test name
Test status
Simulation time 63593440 ps
CPU time 1.13 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 05:41:09 PM PDT 24
Peak memory 196472 kb
Host smart-7414ad8a-4def-4bd6-bedf-ef2cf0218482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471384483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1471384483
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1482575715
Short name T708
Test name
Test status
Simulation time 77719426 ps
CPU time 0.94 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 05:41:08 PM PDT 24
Peak memory 196360 kb
Host smart-43c20e8a-fe6d-435f-bff3-6e66c195c602
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482575715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1482575715
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3357457144
Short name T301
Test name
Test status
Simulation time 168554593 ps
CPU time 1.99 seconds
Started Jul 26 05:41:08 PM PDT 24
Finished Jul 26 05:41:10 PM PDT 24
Peak memory 198432 kb
Host smart-6f925600-0831-4f30-aba7-9575fc42d3a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357457144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3357457144
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.553748065
Short name T724
Test name
Test status
Simulation time 65255157 ps
CPU time 1.24 seconds
Started Jul 26 05:41:01 PM PDT 24
Finished Jul 26 05:41:03 PM PDT 24
Peak memory 196228 kb
Host smart-e3dabbb7-47fd-4a7a-8f01-3cc488b4847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553748065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.553748065
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3702007690
Short name T247
Test name
Test status
Simulation time 120538072 ps
CPU time 1 seconds
Started Jul 26 05:41:00 PM PDT 24
Finished Jul 26 05:41:01 PM PDT 24
Peak memory 196196 kb
Host smart-7abfe46e-94ff-4f15-b829-3678847fc392
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702007690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3702007690
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.228436097
Short name T413
Test name
Test status
Simulation time 2353556665 ps
CPU time 61.94 seconds
Started Jul 26 05:41:17 PM PDT 24
Finished Jul 26 05:42:19 PM PDT 24
Peak memory 198696 kb
Host smart-78560f8d-05fd-4781-8bd1-bc2dfd2590cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228436097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.228436097
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.726660435
Short name T71
Test name
Test status
Simulation time 349825204376 ps
CPU time 1430.24 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 06:05:12 PM PDT 24
Peak memory 198744 kb
Host smart-800c46be-130a-4242-800b-aba13a9e7914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=726660435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.726660435
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.4275598612
Short name T284
Test name
Test status
Simulation time 31556410 ps
CPU time 0.6 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:14 PM PDT 24
Peak memory 194368 kb
Host smart-ee1b740b-464a-4261-ac1a-e7fef690d940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275598612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.4275598612
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1294864381
Short name T160
Test name
Test status
Simulation time 135855202 ps
CPU time 0.87 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:14 PM PDT 24
Peak memory 195852 kb
Host smart-71694fc2-6e05-4f90-b5e4-628067a38bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294864381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1294864381
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1021309310
Short name T705
Test name
Test status
Simulation time 1487059103 ps
CPU time 17.87 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:31 PM PDT 24
Peak memory 197232 kb
Host smart-66a32c29-9d0f-40e4-83b4-3f5e476d06e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021309310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1021309310
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3172925363
Short name T637
Test name
Test status
Simulation time 255744043 ps
CPU time 0.9 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 197140 kb
Host smart-4f3b8484-0ec0-4423-9feb-4b52dca97c63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172925363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3172925363
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2604499905
Short name T551
Test name
Test status
Simulation time 81452964 ps
CPU time 0.69 seconds
Started Jul 26 05:41:09 PM PDT 24
Finished Jul 26 05:41:10 PM PDT 24
Peak memory 194644 kb
Host smart-717d8f72-39eb-491c-a823-98a3f31dd8c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604499905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2604499905
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2639850522
Short name T207
Test name
Test status
Simulation time 66963064 ps
CPU time 1.35 seconds
Started Jul 26 05:41:10 PM PDT 24
Finished Jul 26 05:41:12 PM PDT 24
Peak memory 198500 kb
Host smart-b70f0f73-ca1e-4779-9032-1ea4de194cea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639850522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2639850522
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2599072755
Short name T27
Test name
Test status
Simulation time 179351227 ps
CPU time 1.59 seconds
Started Jul 26 05:41:09 PM PDT 24
Finished Jul 26 05:41:10 PM PDT 24
Peak memory 196444 kb
Host smart-18dd7f7f-7560-4f32-8f22-a1bd3c8beb5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599072755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2599072755
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.4151302957
Short name T370
Test name
Test status
Simulation time 56993591 ps
CPU time 0.7 seconds
Started Jul 26 05:41:12 PM PDT 24
Finished Jul 26 05:41:13 PM PDT 24
Peak memory 194744 kb
Host smart-37c55ba0-ed4e-476b-8a85-4418f3d701ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151302957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.4151302957
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3092706875
Short name T269
Test name
Test status
Simulation time 135368101 ps
CPU time 0.95 seconds
Started Jul 26 05:41:14 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 196580 kb
Host smart-5b0b1af2-c009-4a0e-b3da-f4931da662b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092706875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3092706875
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4122175394
Short name T461
Test name
Test status
Simulation time 45322294 ps
CPU time 2.12 seconds
Started Jul 26 05:41:12 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 198424 kb
Host smart-ae8c97b5-993b-491e-b649-7c1370c361af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122175394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4122175394
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2595168048
Short name T564
Test name
Test status
Simulation time 142911700 ps
CPU time 1.51 seconds
Started Jul 26 05:41:15 PM PDT 24
Finished Jul 26 05:41:17 PM PDT 24
Peak memory 198512 kb
Host smart-ef3cf2c0-63b8-44ce-b3a2-900ccebcd4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595168048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2595168048
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1555519730
Short name T533
Test name
Test status
Simulation time 85831928 ps
CPU time 0.83 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 05:41:08 PM PDT 24
Peak memory 197336 kb
Host smart-8a335a4c-7cd8-41d5-a18b-3c6fcec30a0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555519730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1555519730
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.24741124
Short name T574
Test name
Test status
Simulation time 9488650156 ps
CPU time 129.57 seconds
Started Jul 26 05:41:06 PM PDT 24
Finished Jul 26 05:43:16 PM PDT 24
Peak memory 198640 kb
Host smart-b9282f50-1d52-469e-ae3c-679f08c5cadc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24741124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gp
io_stress_all.24741124
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.658297388
Short name T288
Test name
Test status
Simulation time 186414627730 ps
CPU time 996.95 seconds
Started Jul 26 05:41:24 PM PDT 24
Finished Jul 26 05:58:01 PM PDT 24
Peak memory 198792 kb
Host smart-10977d75-1694-49f0-8622-93122505a76c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=658297388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.658297388
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1077022299
Short name T212
Test name
Test status
Simulation time 36660457 ps
CPU time 0.55 seconds
Started Jul 26 05:41:17 PM PDT 24
Finished Jul 26 05:41:18 PM PDT 24
Peak memory 194316 kb
Host smart-5cdbf176-5e81-4c7f-8968-da1b98a47357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077022299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1077022299
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.459184321
Short name T141
Test name
Test status
Simulation time 39466421 ps
CPU time 0.91 seconds
Started Jul 26 05:41:06 PM PDT 24
Finished Jul 26 05:41:07 PM PDT 24
Peak memory 197076 kb
Host smart-a3dd6c0e-8ef6-434e-9bfc-98ab1ed28d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459184321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.459184321
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.988614152
Short name T144
Test name
Test status
Simulation time 936175940 ps
CPU time 27.92 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:41 PM PDT 24
Peak memory 197136 kb
Host smart-06a7623b-626b-4661-974d-dd397a50b298
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988614152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.988614152
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.785383522
Short name T249
Test name
Test status
Simulation time 259310598 ps
CPU time 0.99 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 198092 kb
Host smart-6717c86c-e62c-4c47-92f0-4f06c78e56dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785383522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.785383522
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.815313012
Short name T217
Test name
Test status
Simulation time 50197572 ps
CPU time 0.8 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 05:41:08 PM PDT 24
Peak memory 196744 kb
Host smart-d17f6ef6-4595-4e0b-bebc-846136a7e348
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815313012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.815313012
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1055775369
Short name T388
Test name
Test status
Simulation time 56152280 ps
CPU time 2.53 seconds
Started Jul 26 05:41:04 PM PDT 24
Finished Jul 26 05:41:07 PM PDT 24
Peak memory 198516 kb
Host smart-179c6f72-2bab-4f49-a66c-c6491dd89a4b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055775369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1055775369
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1091221950
Short name T234
Test name
Test status
Simulation time 290254696 ps
CPU time 1.68 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:06 PM PDT 24
Peak memory 197236 kb
Host smart-5f064ed6-add8-464a-a4cc-37446958df20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091221950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1091221950
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2978591996
Short name T460
Test name
Test status
Simulation time 102424086 ps
CPU time 0.82 seconds
Started Jul 26 05:41:06 PM PDT 24
Finished Jul 26 05:41:08 PM PDT 24
Peak memory 197004 kb
Host smart-4e4c7b9b-8956-4687-bc27-baccd66f2199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978591996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2978591996
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2380110189
Short name T125
Test name
Test status
Simulation time 107828154 ps
CPU time 1 seconds
Started Jul 26 05:41:18 PM PDT 24
Finished Jul 26 05:41:19 PM PDT 24
Peak memory 196444 kb
Host smart-eb7df7db-9e29-4407-bb5b-d4a8dffb9ce5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380110189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2380110189
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3640662873
Short name T302
Test name
Test status
Simulation time 119803764 ps
CPU time 1.18 seconds
Started Jul 26 05:41:04 PM PDT 24
Finished Jul 26 05:41:06 PM PDT 24
Peak memory 198508 kb
Host smart-a7f90771-94b3-4fc8-8210-e6c636679ee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640662873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3640662873
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1032748479
Short name T321
Test name
Test status
Simulation time 64949478 ps
CPU time 0.94 seconds
Started Jul 26 05:41:14 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 196004 kb
Host smart-75d749c4-55b2-44c0-87a7-08bc9c0fc343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032748479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1032748479
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3073601006
Short name T297
Test name
Test status
Simulation time 49184185 ps
CPU time 1.07 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:06 PM PDT 24
Peak memory 197092 kb
Host smart-25467a75-7107-40bb-87ed-1c20d67b5311
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073601006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3073601006
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1387968296
Short name T414
Test name
Test status
Simulation time 16097570725 ps
CPU time 118.25 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:43:12 PM PDT 24
Peak memory 198588 kb
Host smart-fc838529-a354-4e15-aa08-682e4d8af059
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387968296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1387968296
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.153900637
Short name T70
Test name
Test status
Simulation time 92568984206 ps
CPU time 2100.1 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 06:16:08 PM PDT 24
Peak memory 198680 kb
Host smart-3a3ca023-f088-4f58-adb0-682588ab41b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=153900637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.153900637
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2113795038
Short name T198
Test name
Test status
Simulation time 13848044 ps
CPU time 0.56 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:13 PM PDT 24
Peak memory 195028 kb
Host smart-c6c3c0b1-eb9b-4e03-b97b-b0e17242051d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113795038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2113795038
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.404284137
Short name T66
Test name
Test status
Simulation time 192604865 ps
CPU time 0.91 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 196744 kb
Host smart-b86426b6-9fad-4c02-8305-4a50c993d198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404284137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.404284137
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3888644233
Short name T29
Test name
Test status
Simulation time 106494351 ps
CPU time 5.51 seconds
Started Jul 26 05:41:09 PM PDT 24
Finished Jul 26 05:41:14 PM PDT 24
Peak memory 197272 kb
Host smart-741c6c6d-196f-4f17-b64d-ac13ddbbe03e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888644233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3888644233
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1258349256
Short name T428
Test name
Test status
Simulation time 95814202 ps
CPU time 0.83 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:23 PM PDT 24
Peak memory 197092 kb
Host smart-4c1c04b0-c2c2-4c11-8c3f-4b40ac21075a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258349256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1258349256
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1533854210
Short name T426
Test name
Test status
Simulation time 571231883 ps
CPU time 1.14 seconds
Started Jul 26 05:41:14 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 196512 kb
Host smart-8f311674-aa62-44e5-b08b-bd7664af40a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533854210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1533854210
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1996187522
Short name T171
Test name
Test status
Simulation time 25356451 ps
CPU time 1.08 seconds
Started Jul 26 05:41:10 PM PDT 24
Finished Jul 26 05:41:11 PM PDT 24
Peak memory 197520 kb
Host smart-87cb5b4c-b06f-4a48-a1a1-74e86fc5e716
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996187522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1996187522
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2397198318
Short name T539
Test name
Test status
Simulation time 364584460 ps
CPU time 1.93 seconds
Started Jul 26 05:41:21 PM PDT 24
Finished Jul 26 05:41:24 PM PDT 24
Peak memory 196384 kb
Host smart-5438d839-908a-46cf-98fa-03d009db938c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397198318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2397198318
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3954111495
Short name T567
Test name
Test status
Simulation time 159859048 ps
CPU time 1.03 seconds
Started Jul 26 05:41:06 PM PDT 24
Finished Jul 26 05:41:07 PM PDT 24
Peak memory 196528 kb
Host smart-e0a750a3-6265-4bba-b102-e9b075433e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954111495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3954111495
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1877409199
Short name T380
Test name
Test status
Simulation time 305377181 ps
CPU time 1.18 seconds
Started Jul 26 05:41:22 PM PDT 24
Finished Jul 26 05:41:24 PM PDT 24
Peak memory 197760 kb
Host smart-3a142654-8cd6-466b-9e53-94cd704875bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877409199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1877409199
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.503494239
Short name T203
Test name
Test status
Simulation time 86251720 ps
CPU time 3.59 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:09 PM PDT 24
Peak memory 198316 kb
Host smart-80a56b03-b75c-440f-8c5c-27656e3a053d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503494239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.503494239
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2219336060
Short name T176
Test name
Test status
Simulation time 72212377 ps
CPU time 1.12 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:06 PM PDT 24
Peak memory 196360 kb
Host smart-c50fe31c-f2f8-4907-9327-d83d52762aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219336060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2219336060
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3849581792
Short name T514
Test name
Test status
Simulation time 184983616 ps
CPU time 1.05 seconds
Started Jul 26 05:41:07 PM PDT 24
Finished Jul 26 05:41:08 PM PDT 24
Peak memory 196176 kb
Host smart-de7a0bb1-75af-4123-b2e9-20ad5bd2733e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849581792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3849581792
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.206717082
Short name T532
Test name
Test status
Simulation time 18435218449 ps
CPU time 56.04 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:42:09 PM PDT 24
Peak memory 198588 kb
Host smart-fcd22fb5-fba0-4f5c-b534-a2d363972dbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206717082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.206717082
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3028118048
Short name T75
Test name
Test status
Simulation time 130729040554 ps
CPU time 830.76 seconds
Started Jul 26 05:41:09 PM PDT 24
Finished Jul 26 05:55:00 PM PDT 24
Peak memory 198676 kb
Host smart-c355f2d1-e82a-4e42-9cf3-8b6532055bff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3028118048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3028118048
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1346645546
Short name T168
Test name
Test status
Simulation time 49489535 ps
CPU time 0.58 seconds
Started Jul 26 05:41:12 PM PDT 24
Finished Jul 26 05:41:13 PM PDT 24
Peak memory 194572 kb
Host smart-7175d727-ffc8-4516-893d-5dccbfa2c1fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346645546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1346645546
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2971346907
Short name T485
Test name
Test status
Simulation time 46326514 ps
CPU time 0.91 seconds
Started Jul 26 05:41:20 PM PDT 24
Finished Jul 26 05:41:21 PM PDT 24
Peak memory 197004 kb
Host smart-cbf35b27-4dea-45e7-8407-54ac8fc7e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971346907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2971346907
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3470560613
Short name T549
Test name
Test status
Simulation time 281606031 ps
CPU time 13.99 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:27 PM PDT 24
Peak memory 198464 kb
Host smart-d75b1808-2b1e-491d-833d-5c35cc2ce5e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470560613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3470560613
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1575974112
Short name T658
Test name
Test status
Simulation time 109878294 ps
CPU time 0.66 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:14 PM PDT 24
Peak memory 194924 kb
Host smart-535358a3-5450-47bb-aada-8eddbe962f14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575974112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1575974112
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1822844817
Short name T425
Test name
Test status
Simulation time 96076638 ps
CPU time 0.85 seconds
Started Jul 26 05:41:14 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 197168 kb
Host smart-475c4b0f-81bc-42b3-a7d5-deb8797f349b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822844817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1822844817
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.4138192613
Short name T272
Test name
Test status
Simulation time 107741939 ps
CPU time 2.17 seconds
Started Jul 26 05:41:12 PM PDT 24
Finished Jul 26 05:41:14 PM PDT 24
Peak memory 198536 kb
Host smart-daf97d1c-c761-41c4-8036-3079efcd9074
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138192613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.4138192613
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2995559070
Short name T187
Test name
Test status
Simulation time 33200203 ps
CPU time 1.17 seconds
Started Jul 26 05:41:05 PM PDT 24
Finished Jul 26 05:41:07 PM PDT 24
Peak memory 197332 kb
Host smart-061e6be5-b3da-4324-832e-10c848bd1216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995559070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2995559070
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2489002405
Short name T700
Test name
Test status
Simulation time 45794738 ps
CPU time 1.05 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 196520 kb
Host smart-85a1e1eb-9197-4ea1-a9cc-395ed4f18771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489002405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2489002405
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1829356197
Short name T501
Test name
Test status
Simulation time 364850595 ps
CPU time 1.12 seconds
Started Jul 26 05:41:08 PM PDT 24
Finished Jul 26 05:41:09 PM PDT 24
Peak memory 196632 kb
Host smart-b57803f9-c5f7-496d-a9c1-a0631cd9a2e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829356197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1829356197
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1653929803
Short name T722
Test name
Test status
Simulation time 182196239 ps
CPU time 1.89 seconds
Started Jul 26 05:41:13 PM PDT 24
Finished Jul 26 05:41:15 PM PDT 24
Peak memory 198376 kb
Host smart-67b00104-689c-4fb9-9cbb-5608a082b481
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653929803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1653929803
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3581452012
Short name T64
Test name
Test status
Simulation time 85359815 ps
CPU time 1.29 seconds
Started Jul 26 05:41:09 PM PDT 24
Finished Jul 26 05:41:10 PM PDT 24
Peak memory 197304 kb
Host smart-342de264-90e7-46f6-86cf-f45014911cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581452012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3581452012
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.999183254
Short name T11
Test name
Test status
Simulation time 67814861 ps
CPU time 1.18 seconds
Started Jul 26 05:41:17 PM PDT 24
Finished Jul 26 05:41:18 PM PDT 24
Peak memory 196016 kb
Host smart-d56f08ff-84d3-4605-845c-b64b88ec1ed2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999183254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.999183254
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2268503058
Short name T716
Test name
Test status
Simulation time 5203126484 ps
CPU time 75.68 seconds
Started Jul 26 05:41:09 PM PDT 24
Finished Jul 26 05:42:25 PM PDT 24
Peak memory 198540 kb
Host smart-4ae9818f-2b6d-40fc-babc-0e44ebba920f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268503058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2268503058
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3547378385
Short name T446
Test name
Test status
Simulation time 13767057 ps
CPU time 0.58 seconds
Started Jul 26 05:39:47 PM PDT 24
Finished Jul 26 05:39:48 PM PDT 24
Peak memory 194400 kb
Host smart-41e88564-687d-4740-b1b7-154c7e1344ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547378385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3547378385
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2724095763
Short name T377
Test name
Test status
Simulation time 66155926 ps
CPU time 0.79 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:39 PM PDT 24
Peak memory 196316 kb
Host smart-c1882621-af81-4c94-8fcc-d1350c84ef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724095763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2724095763
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2573111467
Short name T617
Test name
Test status
Simulation time 722372601 ps
CPU time 9.74 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:39:51 PM PDT 24
Peak memory 195992 kb
Host smart-13d6cc32-3ea7-49b2-b4a5-af4f795818e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573111467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2573111467
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1178046777
Short name T662
Test name
Test status
Simulation time 48470172 ps
CPU time 0.8 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:39:45 PM PDT 24
Peak memory 196232 kb
Host smart-00c1b18d-92d3-4bce-a699-9fb16fb32424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178046777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1178046777
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1088374877
Short name T188
Test name
Test status
Simulation time 62361551 ps
CPU time 0.73 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:46 PM PDT 24
Peak memory 194744 kb
Host smart-36a5b4cc-c6a9-463b-bfeb-209340976c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088374877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1088374877
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4253040023
Short name T536
Test name
Test status
Simulation time 385824494 ps
CPU time 2.95 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:46 PM PDT 24
Peak memory 198464 kb
Host smart-a21dc684-474a-453d-85e6-f58f8cda1620
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253040023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4253040023
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3862159648
Short name T666
Test name
Test status
Simulation time 178218646 ps
CPU time 1.51 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 196464 kb
Host smart-5d7ea29b-3c50-4746-b55d-84728dcb7c77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862159648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3862159648
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1197844347
Short name T307
Test name
Test status
Simulation time 43131059 ps
CPU time 0.92 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:39:42 PM PDT 24
Peak memory 196516 kb
Host smart-8ddfdcc3-dec9-4eff-a9f3-2ea70f5865cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197844347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1197844347
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2352796161
Short name T668
Test name
Test status
Simulation time 49574207 ps
CPU time 1.11 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:39:42 PM PDT 24
Peak memory 196536 kb
Host smart-ed373754-d2fb-4a69-8a84-3457b398e3a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352796161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2352796161
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3585299746
Short name T712
Test name
Test status
Simulation time 299443029 ps
CPU time 2.72 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:41 PM PDT 24
Peak memory 197440 kb
Host smart-ece0f77f-0016-421b-85f7-a31ac70c5a70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585299746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3585299746
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2660370904
Short name T550
Test name
Test status
Simulation time 148134688 ps
CPU time 1.15 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 196064 kb
Host smart-f276efa9-aea5-469c-b4d1-692853431bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660370904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2660370904
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3625488101
Short name T223
Test name
Test status
Simulation time 166253885 ps
CPU time 1.34 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 196708 kb
Host smart-e8d95a0f-4019-41ed-8213-fa2ca10a85da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625488101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3625488101
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1202405917
Short name T294
Test name
Test status
Simulation time 76954045150 ps
CPU time 193.3 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:42:58 PM PDT 24
Peak memory 198612 kb
Host smart-d3c126f0-e401-4ede-8187-0c23e595c568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202405917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1202405917
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3871061568
Short name T598
Test name
Test status
Simulation time 28103808 ps
CPU time 0.57 seconds
Started Jul 26 05:39:49 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 194644 kb
Host smart-ec74e2ce-0dcc-4702-8821-def20be5a576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871061568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3871061568
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.598656502
Short name T330
Test name
Test status
Simulation time 97461309 ps
CPU time 0.73 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 195540 kb
Host smart-5563fa5f-23a1-4c8a-bf8c-1adeff9fc924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598656502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.598656502
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1713925666
Short name T528
Test name
Test status
Simulation time 216695988 ps
CPU time 7.76 seconds
Started Jul 26 05:39:47 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 198476 kb
Host smart-d50ed916-60ac-47b8-91ac-844904c80767
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713925666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1713925666
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3202249787
Short name T471
Test name
Test status
Simulation time 43114841 ps
CPU time 0.81 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:39:45 PM PDT 24
Peak memory 197124 kb
Host smart-831782cb-caf2-4ef3-a6eb-d14bc04e235f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202249787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3202249787
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3062016520
Short name T90
Test name
Test status
Simulation time 481299817 ps
CPU time 0.95 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:39:45 PM PDT 24
Peak memory 197668 kb
Host smart-3a9ad27d-a83e-4d76-871a-57939aa4c63d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062016520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3062016520
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3528589941
Short name T430
Test name
Test status
Simulation time 310117165 ps
CPU time 3.15 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:39:48 PM PDT 24
Peak memory 198552 kb
Host smart-3f8f133d-df90-475e-83bc-5bbf37abdc1d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528589941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3528589941
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.905062783
Short name T262
Test name
Test status
Simulation time 1425175768 ps
CPU time 3.34 seconds
Started Jul 26 05:39:42 PM PDT 24
Finished Jul 26 05:39:45 PM PDT 24
Peak memory 198436 kb
Host smart-93e65ab7-963f-418c-af1b-b33fcac0e5f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905062783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.905062783
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3202153827
Short name T317
Test name
Test status
Simulation time 45404056 ps
CPU time 1.01 seconds
Started Jul 26 05:39:37 PM PDT 24
Finished Jul 26 05:39:38 PM PDT 24
Peak memory 197104 kb
Host smart-f23779c0-9356-42c6-8bb7-28be030b8db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202153827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3202153827
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2663751354
Short name T401
Test name
Test status
Simulation time 40851094 ps
CPU time 0.69 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 195512 kb
Host smart-1a056158-5a29-488e-830e-3659e88c47c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663751354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2663751354
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3678148696
Short name T545
Test name
Test status
Simulation time 40337564 ps
CPU time 0.99 seconds
Started Jul 26 05:39:47 PM PDT 24
Finished Jul 26 05:39:48 PM PDT 24
Peak memory 197040 kb
Host smart-71e61fc6-6f0b-49e4-944b-4bb923999e4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678148696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3678148696
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3870376159
Short name T60
Test name
Test status
Simulation time 221932071 ps
CPU time 1.13 seconds
Started Jul 26 05:39:42 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 196280 kb
Host smart-d748e6fd-1b94-41ca-85d1-215cb69bc5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870376159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3870376159
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2514492330
Short name T633
Test name
Test status
Simulation time 148617135 ps
CPU time 1.27 seconds
Started Jul 26 05:39:36 PM PDT 24
Finished Jul 26 05:39:38 PM PDT 24
Peak memory 196900 kb
Host smart-d91df285-4e22-4a90-ae38-5f14fe61355b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514492330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2514492330
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.4207489137
Short name T253
Test name
Test status
Simulation time 17567641450 ps
CPU time 74.6 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:40:53 PM PDT 24
Peak memory 198648 kb
Host smart-19d5ae68-faca-4c1e-b852-608b99bae2e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207489137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.4207489137
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.889611736
Short name T656
Test name
Test status
Simulation time 33230131362 ps
CPU time 784.16 seconds
Started Jul 26 05:39:49 PM PDT 24
Finished Jul 26 05:52:54 PM PDT 24
Peak memory 198744 kb
Host smart-7dfd6999-bb04-452f-af3b-6f8290857e91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=889611736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.889611736
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2642279302
Short name T259
Test name
Test status
Simulation time 18172636 ps
CPU time 0.59 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:39 PM PDT 24
Peak memory 194404 kb
Host smart-807d8071-c6c8-41c8-b5b9-dfb35085fba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642279302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2642279302
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2045791798
Short name T531
Test name
Test status
Simulation time 120559384 ps
CPU time 0.8 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:46 PM PDT 24
Peak memory 195804 kb
Host smart-45093c91-2066-433d-a2fa-75364de048f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045791798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2045791798
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2935360171
Short name T325
Test name
Test status
Simulation time 493568157 ps
CPU time 13.06 seconds
Started Jul 26 05:39:37 PM PDT 24
Finished Jul 26 05:39:50 PM PDT 24
Peak memory 196048 kb
Host smart-3b401e47-1e29-4292-9fd0-2dd53e97f63b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935360171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2935360171
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1777349607
Short name T88
Test name
Test status
Simulation time 47906953 ps
CPU time 0.78 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 196340 kb
Host smart-b90d5e02-b40a-4cde-ba81-d962326e4a16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777349607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1777349607
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1927807624
Short name T33
Test name
Test status
Simulation time 201315233 ps
CPU time 1.34 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:46 PM PDT 24
Peak memory 197424 kb
Host smart-5dac2d6b-d83d-4088-9c67-25b60c930095
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927807624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1927807624
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3042867763
Short name T692
Test name
Test status
Simulation time 483414624 ps
CPU time 2.64 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:42 PM PDT 24
Peak memory 198520 kb
Host smart-cfca234c-9684-4471-a917-80354434316d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042867763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3042867763
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4289703776
Short name T310
Test name
Test status
Simulation time 400676467 ps
CPU time 3.18 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:55 PM PDT 24
Peak memory 198596 kb
Host smart-201a88a0-cf3e-4c30-b829-9eed20bd3891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289703776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
4289703776
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3750566275
Short name T415
Test name
Test status
Simulation time 49560753 ps
CPU time 0.98 seconds
Started Jul 26 05:39:49 PM PDT 24
Finished Jul 26 05:39:56 PM PDT 24
Peak memory 196416 kb
Host smart-2a62a39f-c901-407e-86dd-d4ef9f47e72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750566275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3750566275
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3061063549
Short name T570
Test name
Test status
Simulation time 29738452 ps
CPU time 0.82 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:46 PM PDT 24
Peak memory 196032 kb
Host smart-36f8b926-3705-42af-93c4-f7b4ef607278
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061063549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3061063549
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.592399892
Short name T654
Test name
Test status
Simulation time 1459325362 ps
CPU time 4.87 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 198704 kb
Host smart-0b03f548-b678-44bd-aab1-feba30849847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592399892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.592399892
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3227003869
Short name T640
Test name
Test status
Simulation time 94210969 ps
CPU time 0.85 seconds
Started Jul 26 05:39:51 PM PDT 24
Finished Jul 26 05:39:52 PM PDT 24
Peak memory 196868 kb
Host smart-1551e782-c113-461d-a031-e357c53e9d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227003869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3227003869
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.372176979
Short name T309
Test name
Test status
Simulation time 144255290 ps
CPU time 1.4 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:39 PM PDT 24
Peak memory 198464 kb
Host smart-909cc5ae-4a96-4509-ae2f-97c0384eba97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372176979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.372176979
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1313781632
Short name T547
Test name
Test status
Simulation time 121585412302 ps
CPU time 201.16 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:43:00 PM PDT 24
Peak memory 198576 kb
Host smart-d233ad35-7c74-4756-8fab-de97078c775d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313781632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1313781632
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.65911673
Short name T280
Test name
Test status
Simulation time 146351771672 ps
CPU time 949.77 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:55:29 PM PDT 24
Peak memory 198712 kb
Host smart-876910cf-b926-4518-98ce-a1141185cbbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=65911673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.65911673
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2478231118
Short name T582
Test name
Test status
Simulation time 41597211 ps
CPU time 0.62 seconds
Started Jul 26 05:39:37 PM PDT 24
Finished Jul 26 05:39:38 PM PDT 24
Peak memory 195336 kb
Host smart-8c85ad78-3d86-49f6-9e1d-23363fac1a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478231118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2478231118
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4146893844
Short name T87
Test name
Test status
Simulation time 45547647 ps
CPU time 0.94 seconds
Started Jul 26 05:39:46 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 196960 kb
Host smart-a087fe81-4e3c-4847-8745-b5f37c2702f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146893844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4146893844
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1295477820
Short name T363
Test name
Test status
Simulation time 902322001 ps
CPU time 8.25 seconds
Started Jul 26 05:39:37 PM PDT 24
Finished Jul 26 05:39:45 PM PDT 24
Peak memory 198744 kb
Host smart-b9cbfad3-d16d-4e91-95d4-70b6becf5f8b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295477820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1295477820
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1835320614
Short name T318
Test name
Test status
Simulation time 73853252 ps
CPU time 0.99 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:39:42 PM PDT 24
Peak memory 197128 kb
Host smart-6b2777f1-7a3e-46fa-ba20-ba291de1aa84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835320614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1835320614
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.656563454
Short name T457
Test name
Test status
Simulation time 29744160 ps
CPU time 0.93 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:39:42 PM PDT 24
Peak memory 197284 kb
Host smart-9ead4507-4cdf-4d99-b41b-5cce1729d7a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656563454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.656563454
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.996104062
Short name T607
Test name
Test status
Simulation time 284109456 ps
CPU time 3.18 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:49 PM PDT 24
Peak memory 198688 kb
Host smart-8cd9c243-0b8c-46ac-8ff1-c05dc542e551
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996104062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.996104062
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2232921818
Short name T245
Test name
Test status
Simulation time 134255782 ps
CPU time 1.02 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 196020 kb
Host smart-8f683481-2a07-44f6-bf93-da3fdc8017b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232921818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2232921818
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3203972495
Short name T557
Test name
Test status
Simulation time 76268971 ps
CPU time 1.18 seconds
Started Jul 26 05:39:42 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 197364 kb
Host smart-a141baa4-944e-4b22-8be8-306d1545c868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203972495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3203972495
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.440407625
Short name T497
Test name
Test status
Simulation time 52401854 ps
CPU time 0.99 seconds
Started Jul 26 05:39:40 PM PDT 24
Finished Jul 26 05:39:41 PM PDT 24
Peak memory 196508 kb
Host smart-54eadc86-ce08-41ad-b586-dbc413055d8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440407625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.440407625
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1212736579
Short name T200
Test name
Test status
Simulation time 98340195 ps
CPU time 2.31 seconds
Started Jul 26 05:39:41 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 198396 kb
Host smart-861b6a02-2f12-4fde-9462-00650f04fe04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212736579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1212736579
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3469355261
Short name T586
Test name
Test status
Simulation time 79765253 ps
CPU time 1.18 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:39:39 PM PDT 24
Peak memory 197400 kb
Host smart-0ceb90a0-8cf3-4fef-8b0f-ed7e230b0ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469355261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3469355261
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2560281225
Short name T166
Test name
Test status
Simulation time 93842925 ps
CPU time 1.33 seconds
Started Jul 26 05:39:37 PM PDT 24
Finished Jul 26 05:39:38 PM PDT 24
Peak memory 197360 kb
Host smart-5c6c8035-5da1-426c-90a2-d72d38c8c626
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560281225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2560281225
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2449262601
Short name T300
Test name
Test status
Simulation time 25489927409 ps
CPU time 81.06 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:41:04 PM PDT 24
Peak memory 198600 kb
Host smart-6dbcef2f-4bbc-4dcf-9623-d90765d3b814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449262601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2449262601
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.344658818
Short name T41
Test name
Test status
Simulation time 30986528217 ps
CPU time 639.77 seconds
Started Jul 26 05:39:38 PM PDT 24
Finished Jul 26 05:50:18 PM PDT 24
Peak memory 198764 kb
Host smart-1cb6ae98-aa73-4e81-a049-4242036b85ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=344658818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.344658818
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2435290829
Short name T556
Test name
Test status
Simulation time 30515024 ps
CPU time 0.56 seconds
Started Jul 26 05:39:42 PM PDT 24
Finished Jul 26 05:39:43 PM PDT 24
Peak memory 194352 kb
Host smart-9e798b08-43da-45dc-90c8-6401d8b9792f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435290829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2435290829
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1152125986
Short name T241
Test name
Test status
Simulation time 33664921 ps
CPU time 0.78 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 196360 kb
Host smart-416659e3-01e6-41a6-8ed5-91314944fe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152125986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1152125986
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1298883791
Short name T455
Test name
Test status
Simulation time 447961229 ps
CPU time 6.22 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:39:51 PM PDT 24
Peak memory 197472 kb
Host smart-a89a85c1-8aa8-42ff-99af-4d314143d592
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298883791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1298883791
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3414302908
Short name T431
Test name
Test status
Simulation time 138139016 ps
CPU time 0.95 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 197340 kb
Host smart-511016c3-e3fb-4946-8295-412210860b82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414302908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3414302908
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.315010830
Short name T275
Test name
Test status
Simulation time 234169764 ps
CPU time 1.06 seconds
Started Jul 26 05:39:45 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 196584 kb
Host smart-43812926-9493-4d1b-b142-42650dd545c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315010830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.315010830
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3239630817
Short name T605
Test name
Test status
Simulation time 262274308 ps
CPU time 2.64 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:39:47 PM PDT 24
Peak memory 198668 kb
Host smart-dbd707ac-76ec-481a-8678-ab3ab31bf9d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239630817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3239630817
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1816346882
Short name T163
Test name
Test status
Simulation time 439080232 ps
CPU time 2.26 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:39:46 PM PDT 24
Peak memory 197648 kb
Host smart-92aff9ad-180a-4c60-8d09-25a02289d69a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816346882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1816346882
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.4086987917
Short name T238
Test name
Test status
Simulation time 157447707 ps
CPU time 1.03 seconds
Started Jul 26 05:39:44 PM PDT 24
Finished Jul 26 05:39:45 PM PDT 24
Peak memory 196996 kb
Host smart-ac98d4ae-518b-49d7-b20e-950c8880e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086987917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.4086987917
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1417439909
Short name T693
Test name
Test status
Simulation time 72849219 ps
CPU time 1.02 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 196492 kb
Host smart-039c0676-582a-45f2-a9c6-4bc9fbe595b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417439909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1417439909
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.4205121380
Short name T719
Test name
Test status
Simulation time 71375169 ps
CPU time 1.15 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 198460 kb
Host smart-3335c9fa-d841-462f-9cc1-6e070c1bb117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205121380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.4205121380
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1475688005
Short name T216
Test name
Test status
Simulation time 143541959 ps
CPU time 1.01 seconds
Started Jul 26 05:39:42 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 196240 kb
Host smart-1bd02b32-62d8-4084-8dcc-1ac54f04cbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475688005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1475688005
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.76116555
Short name T285
Test name
Test status
Simulation time 138310672 ps
CPU time 1.07 seconds
Started Jul 26 05:39:43 PM PDT 24
Finished Jul 26 05:39:44 PM PDT 24
Peak memory 196280 kb
Host smart-b07b5397-301e-45bb-a4cc-58023e6af109
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76116555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.76116555
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.1133608242
Short name T328
Test name
Test status
Simulation time 722378969356 ps
CPU time 3340.39 seconds
Started Jul 26 05:39:42 PM PDT 24
Finished Jul 26 06:35:23 PM PDT 24
Peak memory 198680 kb
Host smart-22b4747a-04c0-4432-be07-2f57537f03bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1133608242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.1133608242
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4076476056
Short name T896
Test name
Test status
Simulation time 154604785 ps
CPU time 0.91 seconds
Started Jul 26 05:39:04 PM PDT 24
Finished Jul 26 05:39:05 PM PDT 24
Peak memory 197340 kb
Host smart-cfc2ac83-63f8-43e3-b123-d71da831f4dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4076476056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.4076476056
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1547192272
Short name T892
Test name
Test status
Simulation time 33340805 ps
CPU time 0.83 seconds
Started Jul 26 05:39:02 PM PDT 24
Finished Jul 26 05:39:03 PM PDT 24
Peak memory 191580 kb
Host smart-5f109079-3bbb-48b3-9738-1809846591ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547192272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1547192272
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3754596185
Short name T931
Test name
Test status
Simulation time 339238107 ps
CPU time 1.36 seconds
Started Jul 26 05:39:02 PM PDT 24
Finished Jul 26 05:39:03 PM PDT 24
Peak memory 191724 kb
Host smart-4523e0d4-8b08-470a-82cc-de9fa1e4f505
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3754596185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3754596185
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1117475142
Short name T874
Test name
Test status
Simulation time 63031384 ps
CPU time 1.11 seconds
Started Jul 26 05:39:04 PM PDT 24
Finished Jul 26 05:39:05 PM PDT 24
Peak memory 196752 kb
Host smart-11a69272-0dc9-4840-801a-265d8b6fbe3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117475142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1117475142
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3242119317
Short name T902
Test name
Test status
Simulation time 144633866 ps
CPU time 1.35 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:02 PM PDT 24
Peak memory 198364 kb
Host smart-8758db13-5b6d-4cd8-baca-e19914d5e339
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3242119317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3242119317
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2142898174
Short name T921
Test name
Test status
Simulation time 63017240 ps
CPU time 1.12 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 196708 kb
Host smart-94472738-5b83-4c3e-bb7a-49d6ce922585
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142898174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2142898174
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1547554335
Short name T927
Test name
Test status
Simulation time 96637484 ps
CPU time 0.76 seconds
Started Jul 26 05:39:21 PM PDT 24
Finished Jul 26 05:39:22 PM PDT 24
Peak memory 191580 kb
Host smart-58911f75-156c-4fa8-9d91-49f2df20b1e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1547554335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1547554335
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2451883208
Short name T907
Test name
Test status
Simulation time 76384458 ps
CPU time 1.38 seconds
Started Jul 26 05:39:11 PM PDT 24
Finished Jul 26 05:39:12 PM PDT 24
Peak memory 191748 kb
Host smart-92a80c2f-d22f-4b19-b457-40b46f7833e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451883208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2451883208
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3811922309
Short name T876
Test name
Test status
Simulation time 100234537 ps
CPU time 1.75 seconds
Started Jul 26 05:39:19 PM PDT 24
Finished Jul 26 05:39:20 PM PDT 24
Peak memory 191816 kb
Host smart-2fb85604-7671-4173-8897-d6903f903c92
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3811922309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3811922309
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3631125486
Short name T916
Test name
Test status
Simulation time 64633850 ps
CPU time 1.29 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 191748 kb
Host smart-2f13992a-2f90-4fd5-9b07-de4ce381f2b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631125486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3631125486
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2822908559
Short name T906
Test name
Test status
Simulation time 234298000 ps
CPU time 1.41 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 198364 kb
Host smart-e289d661-05c4-480b-b81b-626c30d6ffd6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2822908559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2822908559
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4071153155
Short name T917
Test name
Test status
Simulation time 73661273 ps
CPU time 1.16 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 191812 kb
Host smart-3657066c-b54d-4829-bef9-df3ad9a93e58
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071153155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4071153155
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2626994534
Short name T860
Test name
Test status
Simulation time 278257362 ps
CPU time 1.22 seconds
Started Jul 26 05:39:20 PM PDT 24
Finished Jul 26 05:39:21 PM PDT 24
Peak memory 191760 kb
Host smart-d2737a68-52ac-4e89-91fb-a831191bca65
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2626994534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2626994534
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98946103
Short name T899
Test name
Test status
Simulation time 224509272 ps
CPU time 1.3 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 191664 kb
Host smart-e221e2ec-d821-42ec-a8a2-38b4c2115e85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98946103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.98946103
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1384646155
Short name T941
Test name
Test status
Simulation time 77020118 ps
CPU time 1.49 seconds
Started Jul 26 05:39:10 PM PDT 24
Finished Jul 26 05:39:12 PM PDT 24
Peak memory 191796 kb
Host smart-910f943b-095d-4b88-9019-b629df3e2f52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1384646155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1384646155
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1278807947
Short name T867
Test name
Test status
Simulation time 218733470 ps
CPU time 1.31 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 191752 kb
Host smart-a1bbdb7a-10af-4d4f-91ed-b6a6966779f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278807947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1278807947
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3067363838
Short name T937
Test name
Test status
Simulation time 40784683 ps
CPU time 1.17 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 197548 kb
Host smart-1e61b7e1-e268-4d78-a2ad-40ee8cb8d04a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3067363838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3067363838
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2931483659
Short name T897
Test name
Test status
Simulation time 29556903 ps
CPU time 0.89 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 197328 kb
Host smart-99b17adf-4bf4-4321-a601-8371c6606469
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931483659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2931483659
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4194973282
Short name T913
Test name
Test status
Simulation time 67247864 ps
CPU time 0.86 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 191444 kb
Host smart-ec3ccb9b-5913-41db-8172-16014ed8174d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4194973282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.4194973282
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224288630
Short name T859
Test name
Test status
Simulation time 98938483 ps
CPU time 1.42 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 191772 kb
Host smart-a87f4020-aa58-4331-9224-71c3b6e69c56
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224288630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4224288630
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2065070680
Short name T935
Test name
Test status
Simulation time 51083267 ps
CPU time 1 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191596 kb
Host smart-6fe11f0a-8cfc-4d33-bc4b-ea3575c39fac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2065070680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2065070680
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1114778590
Short name T934
Test name
Test status
Simulation time 53609667 ps
CPU time 1.35 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191724 kb
Host smart-ef9dfdf9-2632-496f-9e06-cdbf6f7e411d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114778590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1114778590
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3786215141
Short name T888
Test name
Test status
Simulation time 106533640 ps
CPU time 0.9 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191600 kb
Host smart-32ac74d4-4635-4fb8-a823-e67c8169fba4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3786215141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3786215141
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1316425053
Short name T940
Test name
Test status
Simulation time 144707071 ps
CPU time 0.99 seconds
Started Jul 26 05:39:10 PM PDT 24
Finished Jul 26 05:39:12 PM PDT 24
Peak memory 191588 kb
Host smart-266ebc1d-41f4-4001-bb19-6dd295128f61
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316425053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1316425053
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.319924645
Short name T909
Test name
Test status
Simulation time 60154564 ps
CPU time 1.05 seconds
Started Jul 26 05:39:04 PM PDT 24
Finished Jul 26 05:39:05 PM PDT 24
Peak memory 191544 kb
Host smart-95d994ac-f906-49a8-9226-8ea5311783f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=319924645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.319924645
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.529245175
Short name T923
Test name
Test status
Simulation time 38923695 ps
CPU time 0.97 seconds
Started Jul 26 05:38:58 PM PDT 24
Finished Jul 26 05:38:59 PM PDT 24
Peak memory 191616 kb
Host smart-10e4d8e1-6d3d-403e-bfb5-145b58e01a97
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529245175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.529245175
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3434149604
Short name T854
Test name
Test status
Simulation time 49179649 ps
CPU time 1.09 seconds
Started Jul 26 05:39:19 PM PDT 24
Finished Jul 26 05:39:20 PM PDT 24
Peak memory 191776 kb
Host smart-97ffa6f3-bc39-4655-9547-41e05106a6b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3434149604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3434149604
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1999925415
Short name T903
Test name
Test status
Simulation time 153802707 ps
CPU time 1.37 seconds
Started Jul 26 05:39:19 PM PDT 24
Finished Jul 26 05:39:20 PM PDT 24
Peak memory 198164 kb
Host smart-7377af48-241c-415b-bd1d-a3417054f07a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999925415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1999925415
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2701704242
Short name T864
Test name
Test status
Simulation time 210988480 ps
CPU time 1.33 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 198188 kb
Host smart-36f1c46d-83af-42d4-a125-04b9c163e06b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2701704242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2701704242
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.752391585
Short name T883
Test name
Test status
Simulation time 130810195 ps
CPU time 1.14 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 191804 kb
Host smart-22360e0f-54c9-4f66-aad7-18978274bf1b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752391585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.752391585
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3647953817
Short name T922
Test name
Test status
Simulation time 74683277 ps
CPU time 1.13 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:15 PM PDT 24
Peak memory 191816 kb
Host smart-6edffe0b-5edb-4c0f-a518-4745d579cb9a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3647953817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3647953817
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749685906
Short name T900
Test name
Test status
Simulation time 192475011 ps
CPU time 1.19 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191792 kb
Host smart-808b9df8-0b78-4ffe-a064-d68779d94ec2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749685906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3749685906
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1868567887
Short name T898
Test name
Test status
Simulation time 585956511 ps
CPU time 1.23 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 191804 kb
Host smart-dda801cf-6c74-4a57-abb5-94577851bc27
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1868567887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1868567887
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.547399939
Short name T882
Test name
Test status
Simulation time 245587440 ps
CPU time 1.47 seconds
Started Jul 26 05:39:19 PM PDT 24
Finished Jul 26 05:39:20 PM PDT 24
Peak memory 198200 kb
Host smart-5627243c-ed68-43e5-a690-ff77b3f78607
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547399939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.547399939
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2030708756
Short name T863
Test name
Test status
Simulation time 160669139 ps
CPU time 1.25 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 198116 kb
Host smart-4003a3e1-7f35-4cf7-b6bd-2cf99a57b334
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2030708756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2030708756
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1931768669
Short name T914
Test name
Test status
Simulation time 78787769 ps
CPU time 1.26 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 198228 kb
Host smart-51cddc56-9f1d-4079-bfa4-038ab342b3da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931768669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1931768669
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4238469353
Short name T858
Test name
Test status
Simulation time 107242068 ps
CPU time 0.95 seconds
Started Jul 26 05:39:21 PM PDT 24
Finished Jul 26 05:39:22 PM PDT 24
Peak memory 191580 kb
Host smart-e6390d67-e681-4489-868b-0b5c20fe0b32
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4238469353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.4238469353
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1846299363
Short name T869
Test name
Test status
Simulation time 146515372 ps
CPU time 1.22 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191768 kb
Host smart-655d390a-e368-43ee-ae9f-e6a09f769181
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846299363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1846299363
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3632045814
Short name T933
Test name
Test status
Simulation time 90256147 ps
CPU time 1.19 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 191828 kb
Host smart-3e3427fe-7f2d-4c4c-9f74-af97de0b1f36
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3632045814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3632045814
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.914746500
Short name T885
Test name
Test status
Simulation time 49662012 ps
CPU time 1.07 seconds
Started Jul 26 05:39:11 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 197536 kb
Host smart-01a9eda4-6fad-41c6-bb0b-3dcbf681d3a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914746500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.914746500
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4138933625
Short name T945
Test name
Test status
Simulation time 184336168 ps
CPU time 1.27 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 198140 kb
Host smart-ee8e548c-9e81-478e-8ad7-cec241bfe580
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4138933625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4138933625
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3738477724
Short name T943
Test name
Test status
Simulation time 194116220 ps
CPU time 1.35 seconds
Started Jul 26 05:39:20 PM PDT 24
Finished Jul 26 05:39:22 PM PDT 24
Peak memory 198184 kb
Host smart-34ae6c51-f58b-4e4d-b19f-64db0b1ccbd9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738477724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3738477724
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.926601165
Short name T853
Test name
Test status
Simulation time 76506035 ps
CPU time 1.46 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 197728 kb
Host smart-1d470874-a23c-41d4-8efb-2bd9eb8533c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=926601165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.926601165
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2116813190
Short name T862
Test name
Test status
Simulation time 77083192 ps
CPU time 1.12 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 198124 kb
Host smart-bba23603-e826-4063-9f29-eb52e56b81b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116813190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2116813190
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1834400288
Short name T893
Test name
Test status
Simulation time 36407390 ps
CPU time 1.15 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191804 kb
Host smart-3c1c27ff-eb6d-467b-9b08-79cb65b726c1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1834400288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1834400288
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.855945881
Short name T889
Test name
Test status
Simulation time 237190951 ps
CPU time 1.22 seconds
Started Jul 26 05:39:11 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191792 kb
Host smart-c912b5e2-50ad-42f8-a2d8-5b46da09b3ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855945881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.855945881
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2838624130
Short name T904
Test name
Test status
Simulation time 66631898 ps
CPU time 1.2 seconds
Started Jul 26 05:39:01 PM PDT 24
Finished Jul 26 05:39:02 PM PDT 24
Peak memory 198272 kb
Host smart-73b33d81-5ee7-41b2-9bc5-93156fac0080
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2838624130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2838624130
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2376266020
Short name T938
Test name
Test status
Simulation time 620420398 ps
CPU time 1.3 seconds
Started Jul 26 05:39:01 PM PDT 24
Finished Jul 26 05:39:03 PM PDT 24
Peak memory 198148 kb
Host smart-61932f7d-addb-4c85-9d4d-e437913087e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376266020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2376266020
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3845294921
Short name T901
Test name
Test status
Simulation time 207923624 ps
CPU time 1.04 seconds
Started Jul 26 05:39:11 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191728 kb
Host smart-9d51fe08-3210-46ff-9e8b-ec6f0e4925b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3845294921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3845294921
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.559735980
Short name T919
Test name
Test status
Simulation time 35032393 ps
CPU time 1.04 seconds
Started Jul 26 05:39:10 PM PDT 24
Finished Jul 26 05:39:11 PM PDT 24
Peak memory 191784 kb
Host smart-c9e4a78c-6fb4-4082-bf20-6dec8e026a10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559735980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.559735980
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3052453472
Short name T850
Test name
Test status
Simulation time 237922400 ps
CPU time 1.16 seconds
Started Jul 26 05:39:11 PM PDT 24
Finished Jul 26 05:39:12 PM PDT 24
Peak memory 191804 kb
Host smart-62c601a6-a3ac-4d09-a049-dc85b57fcdb6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3052453472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3052453472
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1389706484
Short name T910
Test name
Test status
Simulation time 54166165 ps
CPU time 1.48 seconds
Started Jul 26 05:39:11 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191812 kb
Host smart-9efde12b-d18e-4368-898c-a9db9ef3d385
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389706484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1389706484
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2325534872
Short name T925
Test name
Test status
Simulation time 39632357 ps
CPU time 1.14 seconds
Started Jul 26 05:39:19 PM PDT 24
Finished Jul 26 05:39:20 PM PDT 24
Peak memory 191776 kb
Host smart-69c26c81-dcd6-4530-a1a8-4b7b4c157b52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2325534872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2325534872
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1400831276
Short name T890
Test name
Test status
Simulation time 81360323 ps
CPU time 1.2 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191772 kb
Host smart-5e62f4c9-088f-4f02-ad78-3220a048b95d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400831276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1400831276
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2530589321
Short name T871
Test name
Test status
Simulation time 231590782 ps
CPU time 1.02 seconds
Started Jul 26 05:39:21 PM PDT 24
Finished Jul 26 05:39:22 PM PDT 24
Peak memory 191760 kb
Host smart-bc21080d-bc7e-4751-8525-7e98092c201b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2530589321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2530589321
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1013190333
Short name T857
Test name
Test status
Simulation time 34993014 ps
CPU time 0.97 seconds
Started Jul 26 05:39:12 PM PDT 24
Finished Jul 26 05:39:13 PM PDT 24
Peak memory 191612 kb
Host smart-a0db7bab-7820-485c-8daa-ef5ca60eb518
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013190333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1013190333
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2060078387
Short name T928
Test name
Test status
Simulation time 43995324 ps
CPU time 1.29 seconds
Started Jul 26 05:39:13 PM PDT 24
Finished Jul 26 05:39:14 PM PDT 24
Peak memory 198224 kb
Host smart-9600d17f-189a-4b5a-aaf6-da7e6c3c3b79
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2060078387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2060078387
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2168562443
Short name T932
Test name
Test status
Simulation time 113869249 ps
CPU time 1.18 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:26 PM PDT 24
Peak memory 198392 kb
Host smart-d839f7e2-7561-46c9-8c54-fc7294863be6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168562443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2168562443
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2787442721
Short name T926
Test name
Test status
Simulation time 72637229 ps
CPU time 1.23 seconds
Started Jul 26 05:39:22 PM PDT 24
Finished Jul 26 05:39:23 PM PDT 24
Peak memory 198188 kb
Host smart-3c2cfc75-a230-4bf7-804a-aa9ca03fa9c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2787442721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2787442721
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1840030988
Short name T875
Test name
Test status
Simulation time 151772022 ps
CPU time 1.32 seconds
Started Jul 26 05:39:28 PM PDT 24
Finished Jul 26 05:39:30 PM PDT 24
Peak memory 198096 kb
Host smart-b846e23d-4a0e-4090-94f0-1d7a12edaa27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840030988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1840030988
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.602507508
Short name T866
Test name
Test status
Simulation time 29029357 ps
CPU time 0.89 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:24 PM PDT 24
Peak memory 191596 kb
Host smart-2370c038-5ab3-48fa-919a-9896ef8ecc9a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=602507508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.602507508
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1207566407
Short name T872
Test name
Test status
Simulation time 73786576 ps
CPU time 1.32 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 197992 kb
Host smart-e3165756-66a2-4ab4-9a8f-ba8e423bed0b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207566407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1207566407
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3214241441
Short name T918
Test name
Test status
Simulation time 26911623 ps
CPU time 0.88 seconds
Started Jul 26 05:39:29 PM PDT 24
Finished Jul 26 05:39:30 PM PDT 24
Peak memory 191544 kb
Host smart-f7eb2f76-5c0b-44a5-8372-52ae1c924b18
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3214241441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3214241441
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2864299344
Short name T930
Test name
Test status
Simulation time 55292160 ps
CPU time 1.07 seconds
Started Jul 26 05:39:29 PM PDT 24
Finished Jul 26 05:39:30 PM PDT 24
Peak memory 197236 kb
Host smart-21e8d14e-ed36-43fd-813a-3a4c9caa4cea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864299344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2864299344
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3033265149
Short name T905
Test name
Test status
Simulation time 49073583 ps
CPU time 1.37 seconds
Started Jul 26 05:39:29 PM PDT 24
Finished Jul 26 05:39:30 PM PDT 24
Peak memory 198152 kb
Host smart-5d717862-ea97-46d4-9c20-f3de404f449f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3033265149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3033265149
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3270099650
Short name T886
Test name
Test status
Simulation time 62011869 ps
CPU time 1.22 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 198204 kb
Host smart-72575da6-a7d7-4edf-9cc1-ee57511ca0c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270099650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3270099650
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.471828419
Short name T879
Test name
Test status
Simulation time 42719225 ps
CPU time 1.14 seconds
Started Jul 26 05:39:24 PM PDT 24
Finished Jul 26 05:39:25 PM PDT 24
Peak memory 191728 kb
Host smart-d38020a3-dcf3-475a-89a3-56e304ddb9e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=471828419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.471828419
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2910692319
Short name T884
Test name
Test status
Simulation time 50717317 ps
CPU time 1.25 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:24 PM PDT 24
Peak memory 191812 kb
Host smart-6db7d4fe-259d-40c8-a3b3-71eda5c13701
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910692319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2910692319
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1512904843
Short name T908
Test name
Test status
Simulation time 236562201 ps
CPU time 1.7 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:02 PM PDT 24
Peak memory 191784 kb
Host smart-5089d911-16e1-45a7-82aa-e553724443cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1512904843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1512904843
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3633320369
Short name T912
Test name
Test status
Simulation time 40496009 ps
CPU time 1.13 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:02 PM PDT 24
Peak memory 196804 kb
Host smart-2beb6ca5-c052-44d5-9a87-fd60373d91b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633320369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3633320369
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2936745480
Short name T852
Test name
Test status
Simulation time 580831510 ps
CPU time 1 seconds
Started Jul 26 05:39:30 PM PDT 24
Finished Jul 26 05:39:31 PM PDT 24
Peak memory 191756 kb
Host smart-98fcdfcb-784b-4fe7-91c0-b4aa03cae087
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2936745480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2936745480
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3544289124
Short name T924
Test name
Test status
Simulation time 318489824 ps
CPU time 1.39 seconds
Started Jul 26 05:39:28 PM PDT 24
Finished Jul 26 05:39:29 PM PDT 24
Peak memory 191836 kb
Host smart-bfcceba8-8910-4c25-a0b0-5b8304d0785f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544289124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3544289124
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.67325518
Short name T946
Test name
Test status
Simulation time 40762752 ps
CPU time 0.85 seconds
Started Jul 26 05:39:24 PM PDT 24
Finished Jul 26 05:39:25 PM PDT 24
Peak memory 191580 kb
Host smart-b7d8509e-e482-48f7-baa5-99dba08a0a7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=67325518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.67325518
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2600083221
Short name T947
Test name
Test status
Simulation time 99812243 ps
CPU time 0.74 seconds
Started Jul 26 05:39:28 PM PDT 24
Finished Jul 26 05:39:29 PM PDT 24
Peak memory 191488 kb
Host smart-349a0a4e-a012-4411-8a8c-1f8651257700
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600083221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2600083221
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1383477044
Short name T880
Test name
Test status
Simulation time 253385306 ps
CPU time 1.12 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:25 PM PDT 24
Peak memory 191700 kb
Host smart-ecd89597-a0fa-4b23-ae31-fd56d7fda5c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1383477044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1383477044
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3977747491
Short name T891
Test name
Test status
Simulation time 304135421 ps
CPU time 1.3 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:25 PM PDT 24
Peak memory 191796 kb
Host smart-8be2f17e-e4c9-4d96-9116-2ad9b15df1da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977747491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3977747491
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.161987626
Short name T870
Test name
Test status
Simulation time 160529981 ps
CPU time 0.98 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 191824 kb
Host smart-2e97bc33-b706-4fbe-b706-1de78460dd67
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=161987626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.161987626
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2970099577
Short name T878
Test name
Test status
Simulation time 50496717 ps
CPU time 1 seconds
Started Jul 26 05:39:24 PM PDT 24
Finished Jul 26 05:39:25 PM PDT 24
Peak memory 191812 kb
Host smart-b18f6885-bf2b-48b1-95ea-161aa00b3d14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970099577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2970099577
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3297147802
Short name T856
Test name
Test status
Simulation time 316323633 ps
CPU time 1.26 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 191784 kb
Host smart-3a7fac46-5386-4cb6-87c2-8533a7c2160f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3297147802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3297147802
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.943620164
Short name T849
Test name
Test status
Simulation time 65364416 ps
CPU time 1.28 seconds
Started Jul 26 05:39:25 PM PDT 24
Finished Jul 26 05:39:27 PM PDT 24
Peak memory 198152 kb
Host smart-62f884ae-32a5-40b3-8226-c7f60d39fdab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943620164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.943620164
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1114264076
Short name T881
Test name
Test status
Simulation time 115598661 ps
CPU time 0.93 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:25 PM PDT 24
Peak memory 191824 kb
Host smart-4780c5c6-5d3a-4e24-a0d0-bbf6935d77db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1114264076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1114264076
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1581388568
Short name T944
Test name
Test status
Simulation time 132273243 ps
CPU time 1.36 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 191724 kb
Host smart-c87dbbdd-a915-45a8-99ac-f49bb4098d27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581388568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1581388568
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2822702499
Short name T868
Test name
Test status
Simulation time 139106825 ps
CPU time 1.14 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:29 PM PDT 24
Peak memory 191728 kb
Host smart-d89f1e2f-2579-4bf8-b25a-5d6ca4cf8126
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2822702499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2822702499
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2981454428
Short name T920
Test name
Test status
Simulation time 42592711 ps
CPU time 0.9 seconds
Started Jul 26 05:39:27 PM PDT 24
Finished Jul 26 05:39:29 PM PDT 24
Peak memory 191436 kb
Host smart-3f4b4251-a0f0-4b13-a53d-f27119c1abf3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981454428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2981454428
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1392936386
Short name T915
Test name
Test status
Simulation time 79833459 ps
CPU time 1.37 seconds
Started Jul 26 05:39:26 PM PDT 24
Finished Jul 26 05:39:28 PM PDT 24
Peak memory 191812 kb
Host smart-ba4cea75-5a54-4684-a7a1-61fbbe35d67d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1392936386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1392936386
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.78029080
Short name T855
Test name
Test status
Simulation time 252471793 ps
CPU time 1.32 seconds
Started Jul 26 05:39:28 PM PDT 24
Finished Jul 26 05:39:30 PM PDT 24
Peak memory 198060 kb
Host smart-461d31fb-7d66-4a48-92b9-2373e2c859b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78029080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.78029080
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.300498491
Short name T877
Test name
Test status
Simulation time 249180852 ps
CPU time 0.95 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:25 PM PDT 24
Peak memory 191788 kb
Host smart-6a99d0c1-bc6c-42a7-b428-848061ef91cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=300498491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.300498491
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.939781433
Short name T936
Test name
Test status
Simulation time 39970715 ps
CPU time 1.12 seconds
Started Jul 26 05:39:39 PM PDT 24
Finished Jul 26 05:39:40 PM PDT 24
Peak memory 191792 kb
Host smart-9efd52e0-3111-48f2-9ec8-89ff09edf9ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939781433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.939781433
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.717244215
Short name T895
Test name
Test status
Simulation time 59414072 ps
CPU time 1.12 seconds
Started Jul 26 05:39:24 PM PDT 24
Finished Jul 26 05:39:25 PM PDT 24
Peak memory 191800 kb
Host smart-78c4362b-cc25-4d07-a728-3005adde2bad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=717244215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.717244215
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2806459425
Short name T942
Test name
Test status
Simulation time 338182862 ps
CPU time 1.38 seconds
Started Jul 26 05:39:23 PM PDT 24
Finished Jul 26 05:39:24 PM PDT 24
Peak memory 191780 kb
Host smart-e4e866d9-6a6f-4c13-8602-41c10ed8a7b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806459425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2806459425
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2161881136
Short name T873
Test name
Test status
Simulation time 32739366 ps
CPU time 0.96 seconds
Started Jul 26 05:38:59 PM PDT 24
Finished Jul 26 05:39:00 PM PDT 24
Peak memory 191668 kb
Host smart-7bbd82c5-343f-49ca-9a87-79e62712120f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2161881136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2161881136
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4204449303
Short name T911
Test name
Test status
Simulation time 156479884 ps
CPU time 0.9 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 191612 kb
Host smart-60306fa7-a5bf-47e8-aa7c-91c756951272
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204449303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4204449303
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2307783035
Short name T887
Test name
Test status
Simulation time 173002682 ps
CPU time 1.11 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 197632 kb
Host smart-d27f4aba-0127-4188-a6ee-cbcc4b04f413
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2307783035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2307783035
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4135942186
Short name T851
Test name
Test status
Simulation time 37275186 ps
CPU time 0.87 seconds
Started Jul 26 05:39:03 PM PDT 24
Finished Jul 26 05:39:04 PM PDT 24
Peak memory 191436 kb
Host smart-e2c579ca-61ca-4952-95aa-f201d2836784
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135942186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4135942186
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.158138429
Short name T865
Test name
Test status
Simulation time 42572614 ps
CPU time 1.11 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 197400 kb
Host smart-b14f9fac-c396-4878-a3f5-6ea926ab3bf0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=158138429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.158138429
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3749289317
Short name T861
Test name
Test status
Simulation time 39759084 ps
CPU time 1.11 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 191784 kb
Host smart-6d3581a8-3d2a-4976-b741-bbaceefe45ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749289317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3749289317
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1256061424
Short name T939
Test name
Test status
Simulation time 286909507 ps
CPU time 1.47 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:02 PM PDT 24
Peak memory 198140 kb
Host smart-93e98b83-2f8d-47c2-a2bc-cbff91128f4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1256061424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1256061424
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2098221030
Short name T948
Test name
Test status
Simulation time 112042949 ps
CPU time 1.28 seconds
Started Jul 26 05:39:02 PM PDT 24
Finished Jul 26 05:39:04 PM PDT 24
Peak memory 191760 kb
Host smart-ddb010b8-770d-4051-90b9-72064c3da27a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098221030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2098221030
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3172627224
Short name T929
Test name
Test status
Simulation time 36231879 ps
CPU time 0.98 seconds
Started Jul 26 05:39:03 PM PDT 24
Finished Jul 26 05:39:04 PM PDT 24
Peak memory 191588 kb
Host smart-d7d34e43-6e2a-4ea4-877f-8e025f6ddda2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3172627224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3172627224
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3437538000
Short name T894
Test name
Test status
Simulation time 91801092 ps
CPU time 0.88 seconds
Started Jul 26 05:39:00 PM PDT 24
Finished Jul 26 05:39:01 PM PDT 24
Peak memory 196228 kb
Host smart-679c8b06-a8da-429f-8733-b900ec6460b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437538000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3437538000
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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