Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4259152	1			T1	3854		T11	1		T12	1
all_pins[1]	4259152	1			T1	3854		T11	1		T12	1
all_pins[2]	4259152	1			T1	3854		T11	1		T12	1
all_pins[3]	4259152	1			T1	3854		T11	1		T12	1
all_pins[4]	4259152	1			T1	3854		T11	1		T12	1
all_pins[5]	4259152	1			T1	3854		T11	1		T12	1
all_pins[6]	4259152	1			T1	3854		T11	1		T12	1
all_pins[7]	4259152	1			T1	3854		T11	1		T12	1
all_pins[8]	4259152	1			T1	3854		T11	1		T12	1
all_pins[9]	4259152	1			T1	3854		T11	1		T12	1
all_pins[10]	4259152	1			T1	3854		T11	1		T12	1
all_pins[11]	4259152	1			T1	3854		T11	1		T12	1
all_pins[12]	4259152	1			T1	3854		T11	1		T12	1
all_pins[13]	4259152	1			T1	3854		T11	1		T12	1
all_pins[14]	4259152	1			T1	3854		T11	1		T12	1
all_pins[15]	4259152	1			T1	3854		T11	1		T12	1
all_pins[16]	4259152	1			T1	3854		T11	1		T12	1
all_pins[17]	4259152	1			T1	3854		T11	1		T12	1
all_pins[18]	4259152	1			T1	3854		T11	1		T12	1
all_pins[19]	4259152	1			T1	3854		T11	1		T12	1
all_pins[20]	4259152	1			T1	3854		T11	1		T12	1
all_pins[21]	4259152	1			T1	3854		T11	1		T12	1
all_pins[22]	4259152	1			T1	3854		T11	1		T12	1
all_pins[23]	4259152	1			T1	3854		T11	1		T12	1
all_pins[24]	4259152	1			T1	3854		T11	1		T12	1
all_pins[25]	4259152	1			T1	3854		T11	1		T12	1
all_pins[26]	4259152	1			T1	3854		T11	1		T12	1
all_pins[27]	4259152	1			T1	3854		T11	1		T12	1
all_pins[28]	4259152	1			T1	3854		T11	1		T12	1
all_pins[29]	4259152	1			T1	3854		T11	1		T12	1
all_pins[30]	4259152	1			T1	3854		T11	1		T12	1
all_pins[31]	4259152	1			T1	3854		T11	1		T12	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	84632418	1			T1	76082		T11	32		T12	32
values[0x1]	51660446	1			T1	47246		T13	730		T14	388952
transitions[0x0=>0x1]	30933881	1			T1	28175		T13	371		T14	234525
transitions[0x1=>0x0]	30933720	1			T1	28175		T13	370		T14	234525

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2646517	1			T1	2423		T11	1		T12	1
all_pins[0]	values[0x1]	1612635	1			T1	1431		T13	19		T14	12191
all_pins[0]	transitions[0x0=>0x1]	998980	1			T1	925		T13	7		T14	7410
all_pins[0]	transitions[0x1=>0x0]	1000544	1			T1	946		T13	12		T14	7299
all_pins[1]	values[0x0]	2642380	1			T1	2298		T11	1		T12	1
all_pins[1]	values[0x1]	1616772	1			T1	1556		T13	25		T14	12200
all_pins[1]	transitions[0x0=>0x1]	967960	1			T1	924		T13	16		T14	7192
all_pins[1]	transitions[0x1=>0x0]	963823	1			T1	799		T13	10		T14	7183
all_pins[2]	values[0x0]	2648244	1			T1	2393		T11	1		T12	1
all_pins[2]	values[0x1]	1610908	1			T1	1461		T13	24		T14	12583
all_pins[2]	transitions[0x0=>0x1]	959082	1			T1	829		T13	10		T14	7447
all_pins[2]	transitions[0x1=>0x0]	964946	1			T1	924		T13	11		T14	7064
all_pins[3]	values[0x0]	2644527	1			T1	2495		T11	1		T12	1
all_pins[3]	values[0x1]	1614625	1			T1	1359		T13	22		T14	12322
all_pins[3]	transitions[0x0=>0x1]	966222	1			T1	842		T13	11		T14	7251
all_pins[3]	transitions[0x1=>0x0]	962505	1			T1	944		T13	13		T14	7512
all_pins[4]	values[0x0]	2643637	1			T1	2216		T11	1		T12	1
all_pins[4]	values[0x1]	1615515	1			T1	1638		T13	22		T14	12527
all_pins[4]	transitions[0x0=>0x1]	967232	1			T1	993		T13	11		T14	7430
all_pins[4]	transitions[0x1=>0x0]	966342	1			T1	714		T13	11		T14	7225
all_pins[5]	values[0x0]	2645258	1			T1	2490		T11	1		T12	1
all_pins[5]	values[0x1]	1613894	1			T1	1364		T13	18		T14	12424
all_pins[5]	transitions[0x0=>0x1]	964188	1			T1	837		T13	10		T14	7381
all_pins[5]	transitions[0x1=>0x0]	965809	1			T1	1111		T13	14		T14	7484
all_pins[6]	values[0x0]	2640739	1			T1	2491		T11	1		T12	1
all_pins[6]	values[0x1]	1618413	1			T1	1363		T13	17		T14	12310
all_pins[6]	transitions[0x0=>0x1]	968308	1			T1	884		T13	10		T14	7201
all_pins[6]	transitions[0x1=>0x0]	963789	1			T1	885		T13	11		T14	7315
all_pins[7]	values[0x0]	2644249	1			T1	2287		T11	1		T12	1
all_pins[7]	values[0x1]	1614903	1			T1	1567		T13	27		T14	11596
all_pins[7]	transitions[0x0=>0x1]	964156	1			T1	1017		T13	15		T14	7043
all_pins[7]	transitions[0x1=>0x0]	967666	1			T1	813		T13	5		T14	7757
all_pins[8]	values[0x0]	2649388	1			T1	2364		T11	1		T12	1
all_pins[8]	values[0x1]	1609764	1			T1	1490		T13	16		T14	12038
all_pins[8]	transitions[0x0=>0x1]	962655	1			T1	895		T13	7		T14	7523
all_pins[8]	transitions[0x1=>0x0]	967794	1			T1	972		T13	18		T14	7081
all_pins[9]	values[0x0]	2649082	1			T1	2466		T11	1		T12	1
all_pins[9]	values[0x1]	1610070	1			T1	1388		T13	20		T14	11972
all_pins[9]	transitions[0x0=>0x1]	963364	1			T1	795		T13	10		T14	7199
all_pins[9]	transitions[0x1=>0x0]	963058	1			T1	897		T13	6		T14	7265
all_pins[10]	values[0x0]	2642406	1			T1	2352		T11	1		T12	1
all_pins[10]	values[0x1]	1616746	1			T1	1502		T13	19		T14	12107
all_pins[10]	transitions[0x0=>0x1]	969057	1			T1	938		T13	9		T14	7306
all_pins[10]	transitions[0x1=>0x0]	962381	1			T1	824		T13	10		T14	7171
all_pins[11]	values[0x0]	2643263	1			T1	2253		T11	1		T12	1
all_pins[11]	values[0x1]	1615889	1			T1	1601		T13	25		T14	11313
all_pins[11]	transitions[0x0=>0x1]	966252	1			T1	946		T13	14		T14	6690
all_pins[11]	transitions[0x1=>0x0]	967109	1			T1	847		T13	8		T14	7484
all_pins[12]	values[0x0]	2647334	1			T1	2571		T11	1		T12	1
all_pins[12]	values[0x1]	1611818	1			T1	1283		T13	19		T14	11629
all_pins[12]	transitions[0x0=>0x1]	964001	1			T1	721		T13	12		T14	7357
all_pins[12]	transitions[0x1=>0x0]	968072	1			T1	1039		T13	18		T14	7041
all_pins[13]	values[0x0]	2644855	1			T1	2434		T11	1		T12	1
all_pins[13]	values[0x1]	1614297	1			T1	1420		T13	26		T14	11744
all_pins[13]	transitions[0x0=>0x1]	968486	1			T1	885		T13	17		T14	7315
all_pins[13]	transitions[0x1=>0x0]	966007	1			T1	748		T13	10		T14	7200
all_pins[14]	values[0x0]	2648195	1			T1	2457		T11	1		T12	1
all_pins[14]	values[0x1]	1610957	1			T1	1397		T13	22		T14	12251
all_pins[14]	transitions[0x0=>0x1]	963311	1			T1	765		T13	10		T14	7512
all_pins[14]	transitions[0x1=>0x0]	966651	1			T1	788		T13	14		T14	7005
all_pins[15]	values[0x0]	2644019	1			T1	2332		T11	1		T12	1
all_pins[15]	values[0x1]	1615133	1			T1	1522		T13	19		T14	12177
all_pins[15]	transitions[0x0=>0x1]	968145	1			T1	863		T13	9		T14	7374
all_pins[15]	transitions[0x1=>0x0]	963969	1			T1	738		T13	12		T14	7448
all_pins[16]	values[0x0]	2655697	1			T1	2360		T11	1		T12	1
all_pins[16]	values[0x1]	1603455	1			T1	1494		T13	34		T14	12288
all_pins[16]	transitions[0x0=>0x1]	956477	1			T1	855		T13	20		T14	7540
all_pins[16]	transitions[0x1=>0x0]	968155	1			T1	883		T13	5		T14	7429
all_pins[17]	values[0x0]	2645402	1			T1	2303		T11	1		T12	1
all_pins[17]	values[0x1]	1613750	1			T1	1551		T13	16		T14	12160
all_pins[17]	transitions[0x0=>0x1]	968405	1			T1	927		T13	5		T14	7291
all_pins[17]	transitions[0x1=>0x0]	958110	1			T1	870		T13	23		T14	7419
all_pins[18]	values[0x0]	2648512	1			T1	2366		T11	1		T12	1
all_pins[18]	values[0x1]	1610640	1			T1	1488		T13	25		T14	12308
all_pins[18]	transitions[0x0=>0x1]	964222	1			T1	892		T13	19		T14	7287
all_pins[18]	transitions[0x1=>0x0]	967332	1			T1	955		T13	10		T14	7139
all_pins[19]	values[0x0]	2645159	1			T1	2413		T11	1		T12	1
all_pins[19]	values[0x1]	1613993	1			T1	1441		T13	21		T14	12403
all_pins[19]	transitions[0x0=>0x1]	967308	1			T1	924		T13	11		T14	7540
all_pins[19]	transitions[0x1=>0x0]	963955	1			T1	971		T13	15		T14	7445
all_pins[20]	values[0x0]	2640328	1			T1	2351		T11	1		T12	1
all_pins[20]	values[0x1]	1618824	1			T1	1503		T13	35		T14	12394
all_pins[20]	transitions[0x0=>0x1]	969384	1			T1	931		T13	16		T14	7449
all_pins[20]	transitions[0x1=>0x0]	964553	1			T1	869		T13	2		T14	7458
all_pins[21]	values[0x0]	2646278	1			T1	2391		T11	1		T12	1
all_pins[21]	values[0x1]	1612874	1			T1	1463		T13	24		T14	12292
all_pins[21]	transitions[0x0=>0x1]	963104	1			T1	842		T13	8		T14	7290
all_pins[21]	transitions[0x1=>0x0]	969054	1			T1	882		T13	19		T14	7392
all_pins[22]	values[0x0]	2642733	1			T1	2297		T11	1		T12	1
all_pins[22]	values[0x1]	1616419	1			T1	1557		T13	22		T14	12067
all_pins[22]	transitions[0x0=>0x1]	970216	1			T1	983		T13	9		T14	7084
all_pins[22]	transitions[0x1=>0x0]	966671	1			T1	889		T13	11		T14	7309
all_pins[23]	values[0x0]	2641122	1			T1	2477		T11	1		T12	1
all_pins[23]	values[0x1]	1618030	1			T1	1377		T13	18		T14	12392
all_pins[23]	transitions[0x0=>0x1]	967935	1			T1	752		T13	8		T14	7610
all_pins[23]	transitions[0x1=>0x0]	966324	1			T1	932		T13	12		T14	7285
all_pins[24]	values[0x0]	2640988	1			T1	2341		T11	1		T12	1
all_pins[24]	values[0x1]	1618164	1			T1	1513		T13	19		T14	12515
all_pins[24]	transitions[0x0=>0x1]	967031	1			T1	918		T13	10		T14	7384
all_pins[24]	transitions[0x1=>0x0]	966897	1			T1	782		T13	9		T14	7261
all_pins[25]	values[0x0]	2646246	1			T1	2437		T11	1		T12	1
all_pins[25]	values[0x1]	1612906	1			T1	1417		T13	21		T14	11855
all_pins[25]	transitions[0x0=>0x1]	963816	1			T1	802		T13	13		T14	7045
all_pins[25]	transitions[0x1=>0x0]	969074	1			T1	898		T13	11		T14	7705
all_pins[26]	values[0x0]	2641956	1			T1	2422		T11	1		T12	1
all_pins[26]	values[0x1]	1617196	1			T1	1432		T13	23		T14	11720
all_pins[26]	transitions[0x0=>0x1]	967383	1			T1	839		T13	11		T14	7094
all_pins[26]	transitions[0x1=>0x0]	963093	1			T1	824		T13	9		T14	7229
all_pins[27]	values[0x0]	2639095	1			T1	2336		T11	1		T12	1
all_pins[27]	values[0x1]	1620057	1			T1	1518		T13	19		T14	12204
all_pins[27]	transitions[0x0=>0x1]	966346	1			T1	911		T13	9		T14	7594
all_pins[27]	transitions[0x1=>0x0]	963485	1			T1	825		T13	13		T14	7110
all_pins[28]	values[0x0]	2644171	1			T1	2211		T11	1		T12	1
all_pins[28]	values[0x1]	1614981	1			T1	1643		T13	27		T14	12671
all_pins[28]	transitions[0x0=>0x1]	963547	1			T1	1019		T13	20		T14	7653
all_pins[28]	transitions[0x1=>0x0]	968623	1			T1	894		T13	12		T14	7186
all_pins[29]	values[0x0]	2641935	1			T1	2308		T11	1		T12	1
all_pins[29]	values[0x1]	1617217	1			T1	1546		T13	28		T14	12216
all_pins[29]	transitions[0x0=>0x1]	967464	1			T1	878		T13	12		T14	7398
all_pins[29]	transitions[0x1=>0x0]	965228	1			T1	975		T13	11		T14	7853
all_pins[30]	values[0x0]	2643911	1			T1	2345		T11	1		T12	1
all_pins[30]	values[0x1]	1615241	1			T1	1509		T13	33		T14	12003
all_pins[30]	transitions[0x0=>0x1]	967129	1			T1	810		T13	14		T14	7413
all_pins[30]	transitions[0x1=>0x0]	969105	1			T1	847		T13	9		T14	7626
all_pins[31]	values[0x0]	2644792	1			T1	2402		T11	1		T12	1
all_pins[31]	values[0x1]	1614360	1			T1	1452		T13	25		T14	12080
all_pins[31]	transitions[0x0=>0x1]	962715	1			T1	833		T13	8		T14	7222
all_pins[31]	transitions[0x1=>0x0]	963596	1			T1	890		T13	16		T14	7145