Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[1]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[2]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[3]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[4]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[5]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[6]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[7]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[8]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[9]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[10]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[11]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[12]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[13]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[14]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[15]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[16]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[17]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[18]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[19]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[20]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[21]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[22]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[23]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[24]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[25]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[26]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[27]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[28]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[29]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[30]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[31]	13874113	1			T1	15284		T11	661		T12	323

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265485869

1

T1

302551

T11

16561

T12

7164

auto[1]

178485747

1

T1

186537

T11

4591

T12

3172

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

356219559

1

T1

404279

T11

16592

T12

6899

auto[1]

87752057

1

T1

84809

T11

4560

T12

3437

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

330762386

1

T1

382248

T11

10974

T12

6770

auto[1]

113209230

1

T1

106840

T11

10178

T12

3566

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5164311	1			T1	6177		T11	164		T12	103
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3789039	1			T1	4396		T11	14		T12	47
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1377366	1			T1	1266		T11	84		T12	54
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1754565	1			T1	1958		T11	266		T12	61
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	418113	1			T1	169		T11	52		T14	1398
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1370719	1			T1	1318		T11	81		T12	58
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5164050	1			T1	6260		T11	315		T12	152
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3800443	1			T1	4318		T11	55		T12	50
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1382771	1			T1	1198		T11	57		T12	13
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1743904	1			T1	2070		T11	175		T12	76
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	416774	1			T1	127		T11	21		T14	1358
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1366171	1			T1	1311		T11	38		T12	32
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5167800	1			T1	6321		T11	202		T12	112
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3797485	1			T1	4364		T11	42		T12	42
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1378675	1			T1	1308		T11	61		T12	41
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1751390	1			T1	1935		T11	272		T12	72
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	416435	1			T1	118		T11	33		T14	1337
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1362328	1			T1	1238		T11	51		T12	56
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5172245	1			T1	6115		T11	220		T12	114
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3787728	1			T1	4421		T11	21		T12	47
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1378054	1			T1	1305		T11	52		T12	54
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1753494	1			T1	2052		T11	240		T12	54
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	419124	1			T1	170		T11	50		T14	1384
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1363468	1			T1	1221		T11	78		T12	54
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5172188	1			T1	6239		T11	219		T12	112
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3785007	1			T1	4323		T11	49		T12	42
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1381183	1			T1	1190		T11	59		T12	66
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1748311	1			T1	2039		T11	263		T12	49
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	419832	1			T1	185		T11	24		T14	1343
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1367592	1			T1	1308		T11	47		T12	54
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5145821	1			T1	6161		T11	250		T12	109
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3811783	1			T1	4386		T11	38		T12	45
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1377120	1			T1	1274		T11	65		T12	66
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1749579	1			T1	2007		T11	213		T12	48
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	418383	1			T1	135		T11	32		T14	1279
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1371427	1			T1	1321		T11	63		T12	55
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5163732	1			T1	6321		T11	189		T12	108
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3795244	1			T1	4452		T11	31		T12	46
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1382531	1			T1	1376		T11	61		T12	54
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1743935	1			T1	1798		T11	254		T12	72
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	419692	1			T1	113		T11	36		T14	1331
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1368979	1			T1	1224		T11	90		T12	43
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5167846	1			T1	6278		T11	265		T12	104
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3793539	1			T1	4363		T11	36		T12	50
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1378708	1			T1	1431		T11	59		T12	61
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1747630	1			T1	1787		T11	191		T12	60
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	419539	1			T1	129		T11	26		T14	1223
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1366851	1			T1	1296		T11	84		T12	48
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5172007	1			T1	6104		T11	182		T12	124
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3786729	1			T1	4346		T11	32		T12	48
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1380368	1			T1	1280		T11	53		T12	64
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1749887	1			T1	1880		T11	236		T12	46
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	419069	1			T1	177		T11	49		T14	1410
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1366053	1			T1	1497		T11	109		T12	41
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5163964	1			T1	6230		T11	295		T12	117
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3790943	1			T1	4326		T11	58		T12	41
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1380962	1			T1	1375		T11	65		T12	45
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1749389	1			T1	1826		T11	167		T12	52
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	418280	1			T1	121		T11	17		T14	1337
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1370575	1			T1	1406		T11	59		T12	68
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5165106	1			T1	6199		T11	244		T12	116
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3786656	1			T1	4370		T11	34		T12	38
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1377668	1			T1	1406		T11	104		T12	53
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1754918	1			T1	1880		T11	164		T12	52
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	418512	1			T1	123		T11	33		T14	1262
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1371253	1			T1	1306		T11	82		T12	64
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5161618	1			T1	6044		T11	249		T12	109
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3793769	1			T1	4375		T11	51		T12	41
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1377075	1			T1	1374		T11	68		T12	57
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1751613	1			T1	1885		T11	206		T12	48
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	421031	1			T1	144		T11	20		T14	1393
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1369007	1			T1	1462		T11	67		T12	68
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5161220	1			T1	6327		T11	279		T12	113
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3792845	1			T1	4343		T11	37		T12	53
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1381877	1			T1	1323		T11	92		T12	57
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1748334	1			T1	1809		T11	159		T12	36
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	420277	1			T1	145		T11	26		T14	1233
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1369560	1			T1	1337		T11	68		T12	64
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5167250	1			T1	6141		T11	218		T12	122
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3794499	1			T1	4380		T11	35		T12	48
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1376669	1			T1	1290		T11	57		T12	62
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1752414	1			T1	1819		T11	232		T12	45
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	417577	1			T1	139		T11	31		T14	1380
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1365704	1			T1	1515		T11	88		T12	46
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5167179	1			T1	6083		T11	199		T12	98
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3787938	1			T1	4368		T11	34		T12	46
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1377185	1			T1	1405		T11	78		T12	40
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1754251	1			T1	1951		T11	236		T12	70
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	419586	1			T1	124		T11	39		T14	1335
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1367974	1			T1	1353		T11	75		T12	69
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5154722	1			T1	6163		T11	235		T12	109
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3796212	1			T1	4471		T11	28		T12	41
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1379747	1			T1	1384		T11	35		T12	70
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1755762	1			T1	1735		T11	190		T12	53
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	420266	1			T1	112		T11	39		T14	1404
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1367404	1			T1	1419		T11	134		T12	50
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5157967	1			T1	6230		T11	268		T12	100
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3799917	1			T1	4397		T11	50		T12	51
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1372979	1			T1	1330		T11	71		T12	48
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1756084	1			T1	1924		T11	163		T12	80
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	422174	1			T1	145		T11	27		T14	1344
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1364992	1			T1	1258		T11	82		T12	44
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5172114	1			T1	6271		T11	207		T12	106
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3789815	1			T1	4381		T11	44		T12	43
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1371950	1			T1	1427		T11	82		T12	50
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1752714	1			T1	1812		T11	234		T12	66
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	421505	1			T1	121		T11	36		T14	1361
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1366015	1			T1	1272		T11	58		T12	58
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5164016	1			T1	6296		T11	222		T12	123
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3799950	1			T1	4378		T11	37		T12	45
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1377230	1			T1	1356		T11	47		T12	47
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1751603	1			T1	1806		T11	257		T12	38
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	416674	1			T1	143		T11	37		T14	1452
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1364640	1			T1	1305		T11	61		T12	70
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5165511	1			T1	6426		T11	224		T12	127
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3798818	1			T1	4301		T11	30		T12	39
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1373257	1			T1	1409		T11	100		T12	45
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1758026	1			T1	1687		T11	193		T12	76
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	418816	1			T1	126		T11	36		T14	1332
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1359685	1			T1	1335		T11	78		T12	36
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5167168	1			T1	6128		T11	277		T12	121
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3794931	1			T1	4441		T11	53		T12	41
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1373405	1			T1	1384		T11	113		T12	54
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1755160	1			T1	1864		T11	140		T12	61
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	419613	1			T1	154		T11	18		T14	1401
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1363836	1			T1	1313		T11	60		T12	46
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5171867	1			T1	6469		T11	262		T12	132
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3790076	1			T1	4261		T11	46		T12	41
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1372374	1			T1	1416		T11	77		T12	74
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1756657	1			T1	1724		T11	204		T12	26
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	419063	1			T1	123		T11	19		T14	1193
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1364076	1			T1	1291		T11	53		T12	50
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5167881	1			T1	6352		T11	188		T12	109
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3788493	1			T1	4436		T11	25		T12	45
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1373740	1			T1	1331		T11	46		T12	58
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1755579	1			T1	1752		T11	286		T12	81
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	420636	1			T1	106		T11	46		T14	1387
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1367784	1			T1	1307		T11	70		T12	30
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5168635	1			T1	6146		T11	194		T12	109
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3799644	1			T1	4404		T11	26		T12	39
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1379843	1			T1	1242		T11	45		T12	56
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1748465	1			T1	1935		T11	280		T12	59
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	417743	1			T1	176		T11	36		T14	1246
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1359783	1			T1	1381		T11	80		T12	60
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5177631	1			T1	6334		T11	285		T12	75
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3782448	1			T1	4387		T11	25		T12	59
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1376757	1			T1	1385		T11	49		T12	53
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1756018	1			T1	1757		T11	198		T12	72
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	420180	1			T1	120		T11	44		T14	1297
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1361079	1			T1	1301		T11	60		T12	64
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5167480	1			T1	6290		T11	237		T12	96
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3790577	1			T1	4426		T11	42		T12	51
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1369477	1			T1	1321		T11	88		T12	48
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1759444	1			T1	1825		T11	192		T12	56
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	422793	1			T1	116		T11	33		T14	1409
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1364342	1			T1	1306		T11	69		T12	72
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5169026	1			T1	6343		T11	175		T12	101
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3790526	1			T1	4300		T11	30		T12	49
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1376806	1			T1	1285		T11	63		T12	54
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1754707	1			T1	1985		T11	264		T12	37
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	419307	1			T1	155		T11	48		T14	1417
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1363741	1			T1	1216		T11	81		T12	82
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5169644	1			T1	6193		T11	213		T12	140
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3794137	1			T1	4295		T11	40		T12	40
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1373769	1			T1	1235		T11	78		T12	52
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1757079	1			T1	2093		T11	192		T12	50
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	419276	1			T1	159		T11	36		T14	1287
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1360208	1			T1	1309		T11	102		T12	41
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5168214	1			T1	6295		T11	244		T12	101
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3792532	1			T1	4400		T11	42		T12	46
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1371817	1			T1	1371		T11	70		T12	44
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1753409	1			T1	1847		T11	208		T12	64
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	421331	1			T1	157		T11	30		T14	1298
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1366810	1			T1	1214		T11	67		T12	68
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5171896	1			T1	6360		T11	297		T12	94
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3794062	1			T1	4338		T11	51		T12	40
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1367634	1			T1	1151		T11	96		T12	61
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1754807	1			T1	2001		T11	160		T12	60
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	419751	1			T1	130		T11	17		T14	1282
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1365963	1			T1	1304		T11	40		T12	68
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5172348	1			T1	6421		T11	246		T12	125
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3787315	1			T1	4229		T11	25		T12	49
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1373542	1			T1	1427		T11	94		T12	57
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1757077	1			T1	1791		T11	174		T12	64
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	420224	1			T1	123		T11	45		T14	1347
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1363607	1			T1	1293		T11	77		T12	28
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5190133	1			T1	6287		T11	275		T12	122
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3779322	1			T1	4415		T11	37		T12	48
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1374835	1			T1	1198		T11	68		T12	58
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1749700	1			T1	1860		T11	176		T12	61
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	417066	1			T1	105		T11	34		T14	1306
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1363057	1			T1	1419		T11	71		T12	34

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal