Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[1]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[2]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[3]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[4]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[5]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[6]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[7]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[8]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[9]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[10]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[11]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[12]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[13]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[14]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[15]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[16]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[17]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[18]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[19]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[20]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[21]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[22]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[23]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[24]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[25]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[26]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[27]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[28]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[29]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[30]	13874113	1			T1	15284		T11	661		T12	323
bins_for_gpio_bits[31]	13874113	1			T1	15284		T11	661		T12	323

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265485869

1

T1

302551

T11

16561

T12

7164

auto[1]

178485747

1

T1

186537

T11

4591

T12

3172

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265477199

1

T1

302506

T11

16561

T12

7159

auto[1]

178494417

1

T1

186582

T11

4591

T12

3177

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8049944	1			T1	9124		T11	497		T12	203
bins_for_gpio_bits[0]	auto[0]	auto[1]	246037	1			T1	275		T11	17		T12	15
bins_for_gpio_bits[0]	auto[1]	auto[0]	246298	1			T1	277		T11	17		T12	15
bins_for_gpio_bits[0]	auto[1]	auto[1]	5331834	1			T1	5608		T11	130		T12	90
bins_for_gpio_bits[1]	auto[0]	auto[0]	8044788	1			T1	9227		T11	539		T12	233
bins_for_gpio_bits[1]	auto[0]	auto[1]	245658	1			T1	298		T11	8		T12	8
bins_for_gpio_bits[1]	auto[1]	auto[0]	245937	1			T1	301		T11	8		T12	8
bins_for_gpio_bits[1]	auto[1]	auto[1]	5337730	1			T1	5458		T11	106		T12	74
bins_for_gpio_bits[2]	auto[0]	auto[0]	8052287	1			T1	9282		T11	521		T12	214
bins_for_gpio_bits[2]	auto[0]	auto[1]	245329	1			T1	281		T11	14		T12	11
bins_for_gpio_bits[2]	auto[1]	auto[0]	245578	1			T1	282		T11	14		T12	11
bins_for_gpio_bits[2]	auto[1]	auto[1]	5330919	1			T1	5439		T11	112		T12	87
bins_for_gpio_bits[3]	auto[0]	auto[0]	8058429	1			T1	9184		T11	498		T12	207
bins_for_gpio_bits[3]	auto[0]	auto[1]	245082	1			T1	287		T11	14		T12	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	245364	1			T1	288		T11	14		T12	15
bins_for_gpio_bits[3]	auto[1]	auto[1]	5325238	1			T1	5525		T11	135		T12	86
bins_for_gpio_bits[4]	auto[0]	auto[0]	8055911	1			T1	9182		T11	532		T12	213
bins_for_gpio_bits[4]	auto[0]	auto[1]	245508	1			T1	284		T11	9		T12	14
bins_for_gpio_bits[4]	auto[1]	auto[0]	245771	1			T1	286		T11	9		T12	14
bins_for_gpio_bits[4]	auto[1]	auto[1]	5326923	1			T1	5532		T11	111		T12	82
bins_for_gpio_bits[5]	auto[0]	auto[0]	8026544	1			T1	9163		T11	516		T12	209
bins_for_gpio_bits[5]	auto[0]	auto[1]	245709	1			T1	277		T11	12		T12	13
bins_for_gpio_bits[5]	auto[1]	auto[0]	245976	1			T1	279		T11	12		T12	14
bins_for_gpio_bits[5]	auto[1]	auto[1]	5355884	1			T1	5565		T11	121		T12	87
bins_for_gpio_bits[6]	auto[0]	auto[0]	8044082	1			T1	9214		T11	487		T12	219
bins_for_gpio_bits[6]	auto[0]	auto[1]	245846	1			T1	279		T11	17		T12	14
bins_for_gpio_bits[6]	auto[1]	auto[0]	246116	1			T1	281		T11	17		T12	15
bins_for_gpio_bits[6]	auto[1]	auto[1]	5338069	1			T1	5510		T11	140		T12	75
bins_for_gpio_bits[7]	auto[0]	auto[0]	8048552	1			T1	9211		T11	500		T12	210
bins_for_gpio_bits[7]	auto[0]	auto[1]	245350	1			T1	285		T11	15		T12	15
bins_for_gpio_bits[7]	auto[1]	auto[0]	245632	1			T1	285		T11	15		T12	15
bins_for_gpio_bits[7]	auto[1]	auto[1]	5334579	1			T1	5503		T11	131		T12	83
bins_for_gpio_bits[8]	auto[0]	auto[0]	8056687	1			T1	8970		T11	455		T12	221
bins_for_gpio_bits[8]	auto[0]	auto[1]	245328	1			T1	292		T11	16		T12	12
bins_for_gpio_bits[8]	auto[1]	auto[0]	245575	1			T1	294		T11	16		T12	13
bins_for_gpio_bits[8]	auto[1]	auto[1]	5326523	1			T1	5728		T11	174		T12	77
bins_for_gpio_bits[9]	auto[0]	auto[0]	8048829	1			T1	9132		T11	516		T12	200
bins_for_gpio_bits[9]	auto[0]	auto[1]	245190	1			T1	297		T11	11		T12	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	245486	1			T1	299		T11	11		T12	14
bins_for_gpio_bits[9]	auto[1]	auto[1]	5334608	1			T1	5556		T11	123		T12	95
bins_for_gpio_bits[10]	auto[0]	auto[0]	8052054	1			T1	9196		T11	494		T12	209
bins_for_gpio_bits[10]	auto[0]	auto[1]	245367	1			T1	288		T11	18		T12	12
bins_for_gpio_bits[10]	auto[1]	auto[0]	245638	1			T1	289		T11	18		T12	12
bins_for_gpio_bits[10]	auto[1]	auto[1]	5331054	1			T1	5511		T11	131		T12	90
bins_for_gpio_bits[11]	auto[0]	auto[0]	8044457	1			T1	9002		T11	511		T12	198
bins_for_gpio_bits[11]	auto[0]	auto[1]	245558	1			T1	300		T11	12		T12	16
bins_for_gpio_bits[11]	auto[1]	auto[0]	245849	1			T1	301		T11	12		T12	16
bins_for_gpio_bits[11]	auto[1]	auto[1]	5338249	1			T1	5681		T11	126		T12	93
bins_for_gpio_bits[12]	auto[0]	auto[0]	8044850	1			T1	9156		T11	519		T12	193
bins_for_gpio_bits[12]	auto[0]	auto[1]	246307	1			T1	302		T11	11		T12	13
bins_for_gpio_bits[12]	auto[1]	auto[0]	246581	1			T1	303		T11	11		T12	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	5336375	1			T1	5523		T11	120		T12	104
bins_for_gpio_bits[13]	auto[0]	auto[0]	8050399	1			T1	8942		T11	492		T12	216
bins_for_gpio_bits[13]	auto[0]	auto[1]	245694	1			T1	307		T11	15		T12	13
bins_for_gpio_bits[13]	auto[1]	auto[0]	245934	1			T1	308		T11	15		T12	13
bins_for_gpio_bits[13]	auto[1]	auto[1]	5332086	1			T1	5727		T11	139		T12	81
bins_for_gpio_bits[14]	auto[0]	auto[0]	8052579	1			T1	9131		T11	501		T12	192
bins_for_gpio_bits[14]	auto[0]	auto[1]	245717	1			T1	305		T11	12		T12	15
bins_for_gpio_bits[14]	auto[1]	auto[0]	246036	1			T1	308		T11	12		T12	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	5329781	1			T1	5540		T11	136		T12	100
bins_for_gpio_bits[15]	auto[0]	auto[0]	8044143	1			T1	8982		T11	440		T12	216
bins_for_gpio_bits[15]	auto[0]	auto[1]	245852	1			T1	298		T11	20		T12	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	246088	1			T1	300		T11	20		T12	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	5338030	1			T1	5704		T11	181		T12	75
bins_for_gpio_bits[16]	auto[0]	auto[0]	8040788	1			T1	9194		T11	488		T12	214
bins_for_gpio_bits[16]	auto[0]	auto[1]	245930	1			T1	288		T11	14		T12	14
bins_for_gpio_bits[16]	auto[1]	auto[0]	246242	1			T1	290		T11	14		T12	14
bins_for_gpio_bits[16]	auto[1]	auto[1]	5341153	1			T1	5512		T11	145		T12	81
bins_for_gpio_bits[17]	auto[0]	auto[0]	8051037	1			T1	9232		T11	509		T12	205
bins_for_gpio_bits[17]	auto[0]	auto[1]	245483	1			T1	276		T11	14		T12	17
bins_for_gpio_bits[17]	auto[1]	auto[0]	245741	1			T1	278		T11	14		T12	17
bins_for_gpio_bits[17]	auto[1]	auto[1]	5331852	1			T1	5498		T11	124		T12	84
bins_for_gpio_bits[18]	auto[0]	auto[0]	8046887	1			T1	9163		T11	513		T12	192
bins_for_gpio_bits[18]	auto[0]	auto[1]	245686	1			T1	294		T11	13		T12	16
bins_for_gpio_bits[18]	auto[1]	auto[0]	245962	1			T1	295		T11	13		T12	16
bins_for_gpio_bits[18]	auto[1]	auto[1]	5335578	1			T1	5532		T11	122		T12	99
bins_for_gpio_bits[19]	auto[0]	auto[0]	8051750	1			T1	9234		T11	502		T12	237
bins_for_gpio_bits[19]	auto[0]	auto[1]	244785	1			T1	288		T11	15		T12	11
bins_for_gpio_bits[19]	auto[1]	auto[0]	245044	1			T1	288		T11	15		T12	11
bins_for_gpio_bits[19]	auto[1]	auto[1]	5332534	1			T1	5474		T11	129		T12	64
bins_for_gpio_bits[20]	auto[0]	auto[0]	8049959	1			T1	9088		T11	517		T12	224
bins_for_gpio_bits[20]	auto[0]	auto[1]	245554	1			T1	286		T11	13		T12	12
bins_for_gpio_bits[20]	auto[1]	auto[0]	245774	1			T1	288		T11	13		T12	12
bins_for_gpio_bits[20]	auto[1]	auto[1]	5332826	1			T1	5622		T11	118		T12	75
bins_for_gpio_bits[21]	auto[0]	auto[0]	8054860	1			T1	9322		T11	533		T12	221
bins_for_gpio_bits[21]	auto[0]	auto[1]	245733	1			T1	287		T11	10		T12	11
bins_for_gpio_bits[21]	auto[1]	auto[0]	246038	1			T1	287		T11	10		T12	11
bins_for_gpio_bits[21]	auto[1]	auto[1]	5327482	1			T1	5388		T11	108		T12	80
bins_for_gpio_bits[22]	auto[0]	auto[0]	8050609	1			T1	9147		T11	508		T12	240
bins_for_gpio_bits[22]	auto[0]	auto[1]	246334	1			T1	287		T11	12		T12	8
bins_for_gpio_bits[22]	auto[1]	auto[0]	246591	1			T1	288		T11	12		T12	8
bins_for_gpio_bits[22]	auto[1]	auto[1]	5330579	1			T1	5562		T11	129		T12	67
bins_for_gpio_bits[23]	auto[0]	auto[0]	8050854	1			T1	9030		T11	504		T12	211
bins_for_gpio_bits[23]	auto[0]	auto[1]	245824	1			T1	293		T11	15		T12	13
bins_for_gpio_bits[23]	auto[1]	auto[0]	246089	1			T1	293		T11	15		T12	13
bins_for_gpio_bits[23]	auto[1]	auto[1]	5331346	1			T1	5668		T11	127		T12	86
bins_for_gpio_bits[24]	auto[0]	auto[0]	8064442	1			T1	9192		T11	520		T12	184
bins_for_gpio_bits[24]	auto[0]	auto[1]	245694	1			T1	282		T11	12		T12	16
bins_for_gpio_bits[24]	auto[1]	auto[0]	245964	1			T1	284		T11	12		T12	16
bins_for_gpio_bits[24]	auto[1]	auto[1]	5318013	1			T1	5526		T11	117		T12	107
bins_for_gpio_bits[25]	auto[0]	auto[0]	8050131	1			T1	9126		T11	503		T12	182
bins_for_gpio_bits[25]	auto[0]	auto[1]	246023	1			T1	309		T11	14		T12	18
bins_for_gpio_bits[25]	auto[1]	auto[0]	246270	1			T1	310		T11	14		T12	18
bins_for_gpio_bits[25]	auto[1]	auto[1]	5331689	1			T1	5539		T11	130		T12	105
bins_for_gpio_bits[26]	auto[0]	auto[0]	8054050	1			T1	9328		T11	486		T12	180
bins_for_gpio_bits[26]	auto[0]	auto[1]	246203	1			T1	283		T11	16		T12	12
bins_for_gpio_bits[26]	auto[1]	auto[0]	246489	1			T1	285		T11	16		T12	12
bins_for_gpio_bits[26]	auto[1]	auto[1]	5327371	1			T1	5388		T11	143		T12	119
bins_for_gpio_bits[27]	auto[0]	auto[0]	8054598	1			T1	9223		T11	463		T12	228
bins_for_gpio_bits[27]	auto[0]	auto[1]	245625	1			T1	298		T11	20		T12	13
bins_for_gpio_bits[27]	auto[1]	auto[0]	245894	1			T1	298		T11	20		T12	14
bins_for_gpio_bits[27]	auto[1]	auto[1]	5327996	1			T1	5465		T11	158		T12	68
bins_for_gpio_bits[28]	auto[0]	auto[0]	8046662	1			T1	9239		T11	507		T12	192
bins_for_gpio_bits[28]	auto[0]	auto[1]	246500	1			T1	273		T11	15		T12	17
bins_for_gpio_bits[28]	auto[1]	auto[0]	246778	1			T1	274		T11	15		T12	17
bins_for_gpio_bits[28]	auto[1]	auto[1]	5334173	1			T1	5498		T11	124		T12	97
bins_for_gpio_bits[29]	auto[0]	auto[0]	8048247	1			T1	9237		T11	542		T12	198
bins_for_gpio_bits[29]	auto[0]	auto[1]	245769	1			T1	273		T11	11		T12	17
bins_for_gpio_bits[29]	auto[1]	auto[0]	246090	1			T1	275		T11	11		T12	17
bins_for_gpio_bits[29]	auto[1]	auto[1]	5334007	1			T1	5499		T11	97		T12	91
bins_for_gpio_bits[30]	auto[0]	auto[0]	8056546	1			T1	9363		T11	498		T12	238
bins_for_gpio_bits[30]	auto[0]	auto[1]	246157	1			T1	274		T11	16		T12	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	246421	1			T1	276		T11	16		T12	8
bins_for_gpio_bits[30]	auto[1]	auto[1]	5324989	1			T1	5371		T11	131		T12	69
bins_for_gpio_bits[31]	auto[0]	auto[0]	8069224	1			T1	9056		T11	507		T12	232
bins_for_gpio_bits[31]	auto[0]	auto[1]	245188	1			T1	288		T11	12		T12	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	245444	1			T1	289		T11	12		T12	9
bins_for_gpio_bits[31]	auto[1]	auto[1]	5314257	1			T1	5651		T11	130		T12	73