Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8118074 |
1 |
|
|
T1 |
9112 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6000601 |
1 |
|
|
T1 |
6011 |
|
T14 |
45578 |
|
T17 |
71 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13350854 |
1 |
|
|
T1 |
13928 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
767821 |
1 |
|
|
T1 |
1195 |
|
T14 |
5796 |
|
T17 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8134477 |
1 |
|
|
T1 |
7750 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5984198 |
1 |
|
|
T1 |
7373 |
|
T14 |
46554 |
|
T17 |
73 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2605001 |
1 |
|
|
T1 |
3340 |
|
T14 |
20414 |
|
T17 |
22 |
| auto[1] |
auto[0] |
auto[1] |
383010 |
1 |
|
|
T1 |
633 |
|
T14 |
2937 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2611376 |
1 |
|
|
T1 |
2838 |
|
T14 |
20344 |
|
T17 |
44 |
| auto[1] |
auto[1] |
auto[1] |
384811 |
1 |
|
|
T1 |
562 |
|
T14 |
2859 |
|
T17 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8098920 |
1 |
|
|
T1 |
9398 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6019755 |
1 |
|
|
T1 |
5725 |
|
T14 |
45689 |
|
T17 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13347843 |
1 |
|
|
T1 |
14042 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
770832 |
1 |
|
|
T1 |
1081 |
|
T14 |
5446 |
|
T17 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8121981 |
1 |
|
|
T1 |
8482 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5996694 |
1 |
|
|
T1 |
6641 |
|
T14 |
44492 |
|
T17 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2592018 |
1 |
|
|
T1 |
2995 |
|
T14 |
19514 |
|
T17 |
50 |
| auto[1] |
auto[0] |
auto[1] |
381450 |
1 |
|
|
T1 |
572 |
|
T14 |
2748 |
|
T17 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2633844 |
1 |
|
|
T1 |
2565 |
|
T14 |
19532 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[1] |
389382 |
1 |
|
|
T1 |
509 |
|
T14 |
2698 |
|
T18 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8120376 |
1 |
|
|
T1 |
8742 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5998299 |
1 |
|
|
T1 |
6381 |
|
T14 |
46132 |
|
T17 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13347213 |
1 |
|
|
T1 |
14125 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
771462 |
1 |
|
|
T1 |
998 |
|
T14 |
5394 |
|
T17 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8115168 |
1 |
|
|
T1 |
8736 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6003507 |
1 |
|
|
T1 |
6387 |
|
T14 |
44958 |
|
T17 |
78 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2618346 |
1 |
|
|
T1 |
2752 |
|
T14 |
19504 |
|
T17 |
31 |
| auto[1] |
auto[0] |
auto[1] |
386944 |
1 |
|
|
T1 |
505 |
|
T14 |
2652 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2613699 |
1 |
|
|
T1 |
2637 |
|
T14 |
20060 |
|
T17 |
42 |
| auto[1] |
auto[1] |
auto[1] |
384518 |
1 |
|
|
T1 |
493 |
|
T14 |
2742 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8094458 |
1 |
|
|
T1 |
8325 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6024217 |
1 |
|
|
T1 |
6798 |
|
T14 |
42280 |
|
T17 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13348893 |
1 |
|
|
T1 |
14015 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
769782 |
1 |
|
|
T1 |
1108 |
|
T14 |
5600 |
|
T17 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8120336 |
1 |
|
|
T1 |
8038 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5998339 |
1 |
|
|
T1 |
7085 |
|
T14 |
45453 |
|
T17 |
69 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2596068 |
1 |
|
|
T1 |
3109 |
|
T14 |
21560 |
|
T17 |
28 |
| auto[1] |
auto[0] |
auto[1] |
380819 |
1 |
|
|
T1 |
590 |
|
T14 |
3055 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2632489 |
1 |
|
|
T1 |
2868 |
|
T14 |
18293 |
|
T17 |
35 |
| auto[1] |
auto[1] |
auto[1] |
388963 |
1 |
|
|
T1 |
518 |
|
T14 |
2545 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8191118 |
1 |
|
|
T1 |
8909 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5927557 |
1 |
|
|
T1 |
6214 |
|
T14 |
44131 |
|
T17 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13341010 |
1 |
|
|
T1 |
13990 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
777665 |
1 |
|
|
T1 |
1133 |
|
T14 |
5769 |
|
T17 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8087169 |
1 |
|
|
T1 |
8071 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6031506 |
1 |
|
|
T1 |
7052 |
|
T14 |
46274 |
|
T17 |
82 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2648970 |
1 |
|
|
T1 |
2881 |
|
T14 |
20191 |
|
T17 |
43 |
| auto[1] |
auto[0] |
auto[1] |
392468 |
1 |
|
|
T1 |
581 |
|
T14 |
2857 |
|
T17 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2604871 |
1 |
|
|
T1 |
3038 |
|
T14 |
20314 |
|
T17 |
33 |
| auto[1] |
auto[1] |
auto[1] |
385197 |
1 |
|
|
T1 |
552 |
|
T14 |
2912 |
|
T17 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8129769 |
1 |
|
|
T1 |
8992 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5988906 |
1 |
|
|
T1 |
6131 |
|
T14 |
44575 |
|
T17 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13343811 |
1 |
|
|
T1 |
13909 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
774864 |
1 |
|
|
T1 |
1214 |
|
T14 |
5307 |
|
T17 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8093763 |
1 |
|
|
T1 |
7818 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6024912 |
1 |
|
|
T1 |
7305 |
|
T14 |
43415 |
|
T17 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2637799 |
1 |
|
|
T1 |
3446 |
|
T14 |
19368 |
|
T17 |
26 |
| auto[1] |
auto[0] |
auto[1] |
389479 |
1 |
|
|
T1 |
681 |
|
T14 |
2696 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2612249 |
1 |
|
|
T1 |
2645 |
|
T14 |
18740 |
|
T17 |
13 |
| auto[1] |
auto[1] |
auto[1] |
385385 |
1 |
|
|
T1 |
533 |
|
T14 |
2611 |
|
T17 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8140319 |
1 |
|
|
T1 |
8850 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5978356 |
1 |
|
|
T1 |
6273 |
|
T14 |
46034 |
|
T17 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13349305 |
1 |
|
|
T1 |
14137 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
769370 |
1 |
|
|
T1 |
986 |
|
T14 |
5399 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8135727 |
1 |
|
|
T1 |
9189 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5982948 |
1 |
|
|
T1 |
5934 |
|
T14 |
44355 |
|
T17 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2611366 |
1 |
|
|
T1 |
2541 |
|
T14 |
20584 |
|
T17 |
12 |
| auto[1] |
auto[0] |
auto[1] |
385416 |
1 |
|
|
T1 |
529 |
|
T14 |
2861 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2602212 |
1 |
|
|
T1 |
2407 |
|
T14 |
18372 |
|
T18 |
32 |
| auto[1] |
auto[1] |
auto[1] |
383954 |
1 |
|
|
T1 |
457 |
|
T14 |
2538 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8124745 |
1 |
|
|
T1 |
7261 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5993930 |
1 |
|
|
T1 |
7862 |
|
T14 |
45748 |
|
T17 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13349335 |
1 |
|
|
T1 |
14190 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
769340 |
1 |
|
|
T1 |
933 |
|
T14 |
5768 |
|
T17 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8132805 |
1 |
|
|
T1 |
9201 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5985870 |
1 |
|
|
T1 |
5922 |
|
T14 |
46351 |
|
T17 |
78 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2609080 |
1 |
|
|
T1 |
2437 |
|
T14 |
20801 |
|
T17 |
45 |
| auto[1] |
auto[0] |
auto[1] |
384716 |
1 |
|
|
T1 |
480 |
|
T14 |
2950 |
|
T17 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2607450 |
1 |
|
|
T1 |
2552 |
|
T14 |
19782 |
|
T17 |
27 |
| auto[1] |
auto[1] |
auto[1] |
384624 |
1 |
|
|
T1 |
453 |
|
T14 |
2818 |
|
T17 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8162628 |
1 |
|
|
T1 |
9041 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5956047 |
1 |
|
|
T1 |
6082 |
|
T14 |
45366 |
|
T17 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13344483 |
1 |
|
|
T1 |
13849 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
774192 |
1 |
|
|
T1 |
1274 |
|
T14 |
5591 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8101593 |
1 |
|
|
T1 |
7304 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6017082 |
1 |
|
|
T1 |
7819 |
|
T14 |
45459 |
|
T17 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2648219 |
1 |
|
|
T1 |
3963 |
|
T14 |
20128 |
|
T17 |
4 |
| auto[1] |
auto[0] |
auto[1] |
392005 |
1 |
|
|
T1 |
772 |
|
T14 |
2906 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2594671 |
1 |
|
|
T1 |
2582 |
|
T14 |
19740 |
|
T18 |
70 |
| auto[1] |
auto[1] |
auto[1] |
382187 |
1 |
|
|
T1 |
502 |
|
T14 |
2685 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8114713 |
1 |
|
|
T1 |
7766 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6003962 |
1 |
|
|
T1 |
7357 |
|
T14 |
46384 |
|
T17 |
80 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13350942 |
1 |
|
|
T1 |
14085 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
767733 |
1 |
|
|
T1 |
1038 |
|
T14 |
5758 |
|
T17 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8140658 |
1 |
|
|
T1 |
8516 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5978017 |
1 |
|
|
T1 |
6607 |
|
T14 |
45617 |
|
T17 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2609938 |
1 |
|
|
T1 |
2498 |
|
T14 |
19470 |
|
T17 |
14 |
| auto[1] |
auto[0] |
auto[1] |
385258 |
1 |
|
|
T1 |
450 |
|
T14 |
2809 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2600346 |
1 |
|
|
T1 |
3071 |
|
T14 |
20389 |
|
T17 |
26 |
| auto[1] |
auto[1] |
auto[1] |
382475 |
1 |
|
|
T1 |
588 |
|
T14 |
2949 |
|
T17 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8132950 |
1 |
|
|
T1 |
8644 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5985725 |
1 |
|
|
T1 |
6479 |
|
T14 |
45522 |
|
T17 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13342850 |
1 |
|
|
T1 |
13989 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
775825 |
1 |
|
|
T1 |
1134 |
|
T14 |
5314 |
|
T17 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8094626 |
1 |
|
|
T1 |
8143 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6024049 |
1 |
|
|
T1 |
6980 |
|
T14 |
43565 |
|
T17 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2632006 |
1 |
|
|
T1 |
2656 |
|
T14 |
18887 |
|
T17 |
26 |
| auto[1] |
auto[0] |
auto[1] |
389965 |
1 |
|
|
T1 |
510 |
|
T14 |
2558 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2616218 |
1 |
|
|
T1 |
3190 |
|
T14 |
19364 |
|
T17 |
16 |
| auto[1] |
auto[1] |
auto[1] |
385860 |
1 |
|
|
T1 |
624 |
|
T14 |
2756 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8123160 |
1 |
|
|
T1 |
8470 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5995515 |
1 |
|
|
T1 |
6653 |
|
T14 |
45263 |
|
T17 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13352965 |
1 |
|
|
T1 |
13890 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
765710 |
1 |
|
|
T1 |
1233 |
|
T14 |
5636 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8143647 |
1 |
|
|
T1 |
7469 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5975028 |
1 |
|
|
T1 |
7654 |
|
T14 |
45881 |
|
T17 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2603798 |
1 |
|
|
T1 |
3189 |
|
T14 |
20014 |
|
T17 |
27 |
| auto[1] |
auto[0] |
auto[1] |
383475 |
1 |
|
|
T1 |
613 |
|
T14 |
2847 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2605520 |
1 |
|
|
T1 |
3232 |
|
T14 |
20231 |
|
T17 |
5 |
| auto[1] |
auto[1] |
auto[1] |
382235 |
1 |
|
|
T1 |
620 |
|
T14 |
2789 |
|
T18 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8132014 |
1 |
|
|
T1 |
9002 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5986661 |
1 |
|
|
T1 |
6121 |
|
T14 |
47337 |
|
T17 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13348603 |
1 |
|
|
T1 |
14043 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
770072 |
1 |
|
|
T1 |
1080 |
|
T14 |
5347 |
|
T17 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8135565 |
1 |
|
|
T1 |
8257 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5983110 |
1 |
|
|
T1 |
6866 |
|
T14 |
43732 |
|
T17 |
91 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2612572 |
1 |
|
|
T1 |
3294 |
|
T14 |
18746 |
|
T17 |
54 |
| auto[1] |
auto[0] |
auto[1] |
385250 |
1 |
|
|
T1 |
583 |
|
T14 |
2571 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2600466 |
1 |
|
|
T1 |
2492 |
|
T14 |
19639 |
|
T17 |
32 |
| auto[1] |
auto[1] |
auto[1] |
384822 |
1 |
|
|
T1 |
497 |
|
T14 |
2776 |
|
T17 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8121124 |
1 |
|
|
T1 |
9386 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5997551 |
1 |
|
|
T1 |
5737 |
|
T14 |
44579 |
|
T17 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13346372 |
1 |
|
|
T1 |
13994 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
772303 |
1 |
|
|
T1 |
1129 |
|
T14 |
5732 |
|
T17 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8117674 |
1 |
|
|
T1 |
8076 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6001001 |
1 |
|
|
T1 |
7047 |
|
T14 |
45772 |
|
T17 |
60 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2607223 |
1 |
|
|
T1 |
3353 |
|
T14 |
20732 |
|
T17 |
31 |
| auto[1] |
auto[0] |
auto[1] |
385386 |
1 |
|
|
T1 |
602 |
|
T14 |
2950 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2621475 |
1 |
|
|
T1 |
2565 |
|
T14 |
19308 |
|
T17 |
26 |
| auto[1] |
auto[1] |
auto[1] |
386917 |
1 |
|
|
T1 |
527 |
|
T14 |
2782 |
|
T17 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8109530 |
1 |
|
|
T1 |
9093 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6009145 |
1 |
|
|
T1 |
6030 |
|
T14 |
44654 |
|
T17 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13351339 |
1 |
|
|
T1 |
13993 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
767336 |
1 |
|
|
T1 |
1130 |
|
T14 |
5387 |
|
T17 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8136152 |
1 |
|
|
T1 |
8191 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5982523 |
1 |
|
|
T1 |
6932 |
|
T14 |
44071 |
|
T17 |
62 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2595209 |
1 |
|
|
T1 |
3111 |
|
T14 |
19266 |
|
T17 |
43 |
| auto[1] |
auto[0] |
auto[1] |
381186 |
1 |
|
|
T1 |
571 |
|
T14 |
2679 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2619978 |
1 |
|
|
T1 |
2691 |
|
T14 |
19418 |
|
T17 |
15 |
| auto[1] |
auto[1] |
auto[1] |
386150 |
1 |
|
|
T1 |
559 |
|
T14 |
2708 |
|
T17 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8148355 |
1 |
|
|
T1 |
8975 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5970320 |
1 |
|
|
T1 |
6148 |
|
T14 |
46431 |
|
T17 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13345912 |
1 |
|
|
T1 |
14163 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
772763 |
1 |
|
|
T1 |
960 |
|
T14 |
6023 |
|
T17 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8109752 |
1 |
|
|
T1 |
9222 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6008923 |
1 |
|
|
T1 |
5901 |
|
T14 |
47732 |
|
T17 |
86 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2627236 |
1 |
|
|
T1 |
2768 |
|
T14 |
19994 |
|
T17 |
60 |
| auto[1] |
auto[0] |
auto[1] |
387337 |
1 |
|
|
T1 |
527 |
|
T14 |
2808 |
|
T17 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2608924 |
1 |
|
|
T1 |
2173 |
|
T14 |
21715 |
|
T17 |
18 |
| auto[1] |
auto[1] |
auto[1] |
385426 |
1 |
|
|
T1 |
433 |
|
T14 |
3215 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8113179 |
1 |
|
|
T1 |
9829 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6005496 |
1 |
|
|
T1 |
5294 |
|
T14 |
46948 |
|
T17 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13349029 |
1 |
|
|
T1 |
14095 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
769646 |
1 |
|
|
T1 |
1028 |
|
T14 |
5934 |
|
T17 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8127430 |
1 |
|
|
T1 |
8972 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5991245 |
1 |
|
|
T1 |
6151 |
|
T14 |
47491 |
|
T17 |
92 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2614290 |
1 |
|
|
T1 |
2944 |
|
T14 |
20509 |
|
T17 |
62 |
| auto[1] |
auto[0] |
auto[1] |
385374 |
1 |
|
|
T1 |
608 |
|
T14 |
2951 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2607309 |
1 |
|
|
T1 |
2179 |
|
T14 |
21048 |
|
T17 |
23 |
| auto[1] |
auto[1] |
auto[1] |
384272 |
1 |
|
|
T1 |
420 |
|
T14 |
2983 |
|
T17 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8138058 |
1 |
|
|
T1 |
7366 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5980617 |
1 |
|
|
T1 |
7757 |
|
T14 |
47324 |
|
T17 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13346029 |
1 |
|
|
T1 |
14157 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
772646 |
1 |
|
|
T1 |
966 |
|
T14 |
5733 |
|
T17 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8107069 |
1 |
|
|
T1 |
9156 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6011606 |
1 |
|
|
T1 |
5967 |
|
T14 |
45588 |
|
T17 |
78 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2639055 |
1 |
|
|
T1 |
2242 |
|
T14 |
18447 |
|
T17 |
38 |
| auto[1] |
auto[0] |
auto[1] |
389503 |
1 |
|
|
T1 |
441 |
|
T14 |
2581 |
|
T17 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2599905 |
1 |
|
|
T1 |
2759 |
|
T14 |
21408 |
|
T17 |
35 |
| auto[1] |
auto[1] |
auto[1] |
383143 |
1 |
|
|
T1 |
525 |
|
T14 |
3152 |
|
T17 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8118412 |
1 |
|
|
T1 |
8594 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6000263 |
1 |
|
|
T1 |
6529 |
|
T14 |
45249 |
|
T17 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13345489 |
1 |
|
|
T1 |
14144 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
773186 |
1 |
|
|
T1 |
979 |
|
T14 |
5862 |
|
T17 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8120647 |
1 |
|
|
T1 |
8982 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5998028 |
1 |
|
|
T1 |
6141 |
|
T14 |
46602 |
|
T17 |
88 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2607209 |
1 |
|
|
T1 |
2508 |
|
T14 |
20950 |
|
T17 |
59 |
| auto[1] |
auto[0] |
auto[1] |
386665 |
1 |
|
|
T1 |
460 |
|
T14 |
3028 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2617633 |
1 |
|
|
T1 |
2654 |
|
T14 |
19790 |
|
T17 |
25 |
| auto[1] |
auto[1] |
auto[1] |
386521 |
1 |
|
|
T1 |
519 |
|
T14 |
2834 |
|
T17 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8140165 |
1 |
|
|
T1 |
8799 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5978510 |
1 |
|
|
T1 |
6324 |
|
T14 |
44049 |
|
T17 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13342829 |
1 |
|
|
T1 |
14101 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
775846 |
1 |
|
|
T1 |
1022 |
|
T14 |
5539 |
|
T17 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8090784 |
1 |
|
|
T1 |
8577 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6027891 |
1 |
|
|
T1 |
6546 |
|
T14 |
45390 |
|
T17 |
67 |