Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8141724 |
1 |
|
|
T1 |
9542 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5976951 |
1 |
|
|
T1 |
5581 |
|
T14 |
45659 |
|
T17 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13355533 |
1 |
|
|
T1 |
14172 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
763142 |
1 |
|
|
T1 |
951 |
|
T14 |
5560 |
|
T18 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8166942 |
1 |
|
|
T1 |
8915 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5951733 |
1 |
|
|
T1 |
6208 |
|
T14 |
44830 |
|
T17 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2604438 |
1 |
|
|
T1 |
3375 |
|
T14 |
20115 |
|
T17 |
9 |
| auto[1] |
auto[0] |
auto[1] |
383201 |
1 |
|
|
T1 |
631 |
|
T14 |
2775 |
|
T18 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2584153 |
1 |
|
|
T1 |
1882 |
|
T14 |
19155 |
|
T18 |
80 |
| auto[1] |
auto[1] |
auto[1] |
379941 |
1 |
|
|
T1 |
320 |
|
T14 |
2785 |
|
T18 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |