Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8156297 |
1 |
|
|
T1 |
8842 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5962378 |
1 |
|
|
T1 |
6281 |
|
T14 |
45090 |
|
T17 |
57 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13352028 |
1 |
|
|
T1 |
14047 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
766647 |
1 |
|
|
T1 |
1076 |
|
T14 |
5326 |
|
T17 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8159120 |
1 |
|
|
T1 |
8306 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5959555 |
1 |
|
|
T1 |
6817 |
|
T14 |
43521 |
|
T17 |
106 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2600716 |
1 |
|
|
T1 |
3297 |
|
T14 |
18993 |
|
T17 |
48 |
| auto[1] |
auto[0] |
auto[1] |
384142 |
1 |
|
|
T1 |
625 |
|
T14 |
2724 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2592192 |
1 |
|
|
T1 |
2444 |
|
T14 |
19202 |
|
T17 |
54 |
| auto[1] |
auto[1] |
auto[1] |
382505 |
1 |
|
|
T1 |
451 |
|
T14 |
2602 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |