Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8107556 |
1 |
|
|
T1 |
8519 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6011119 |
1 |
|
|
T1 |
6604 |
|
T14 |
44580 |
|
T17 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13346816 |
1 |
|
|
T1 |
14273 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
771859 |
1 |
|
|
T1 |
850 |
|
T14 |
5420 |
|
T17 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8116812 |
1 |
|
|
T1 |
9818 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6001863 |
1 |
|
|
T1 |
5305 |
|
T14 |
43673 |
|
T17 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2599141 |
1 |
|
|
T1 |
2224 |
|
T14 |
20151 |
|
T17 |
8 |
| auto[1] |
auto[0] |
auto[1] |
382013 |
1 |
|
|
T1 |
433 |
|
T14 |
2860 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2630863 |
1 |
|
|
T1 |
2231 |
|
T14 |
18102 |
|
T17 |
10 |
| auto[1] |
auto[1] |
auto[1] |
389846 |
1 |
|
|
T1 |
417 |
|
T14 |
2560 |
|
T18 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |