Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8124032 |
1 |
|
|
T1 |
8320 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5994643 |
1 |
|
|
T1 |
6803 |
|
T14 |
44898 |
|
T17 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13350599 |
1 |
|
|
T1 |
14245 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
768076 |
1 |
|
|
T1 |
878 |
|
T14 |
5603 |
|
T17 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8138188 |
1 |
|
|
T1 |
9566 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5980487 |
1 |
|
|
T1 |
5557 |
|
T14 |
44933 |
|
T17 |
64 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2615255 |
1 |
|
|
T1 |
2645 |
|
T14 |
20259 |
|
T17 |
45 |
| auto[1] |
auto[0] |
auto[1] |
384430 |
1 |
|
|
T1 |
504 |
|
T14 |
2857 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2597156 |
1 |
|
|
T1 |
2034 |
|
T14 |
19071 |
|
T17 |
16 |
| auto[1] |
auto[1] |
auto[1] |
383646 |
1 |
|
|
T1 |
374 |
|
T14 |
2746 |
|
T17 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |