Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8118074 |
1 |
|
|
T1 |
9112 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6000601 |
1 |
|
|
T1 |
6011 |
|
T14 |
45578 |
|
T17 |
71 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11652489 |
1 |
|
|
T1 |
12220 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2466186 |
1 |
|
|
T1 |
2903 |
|
T14 |
17859 |
|
T17 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8138093 |
1 |
|
|
T1 |
8564 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5980582 |
1 |
|
|
T1 |
6559 |
|
T14 |
46877 |
|
T17 |
67 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1753511 |
1 |
|
|
T1 |
2138 |
|
T14 |
14725 |
|
T17 |
17 |
| auto[1] |
auto[0] |
auto[1] |
1228974 |
1 |
|
|
T1 |
1550 |
|
T14 |
9188 |
|
T17 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1760885 |
1 |
|
|
T1 |
1518 |
|
T14 |
14293 |
|
T17 |
17 |
| auto[1] |
auto[1] |
auto[1] |
1237212 |
1 |
|
|
T1 |
1353 |
|
T14 |
8671 |
|
T17 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |