Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8098920 |
1 |
|
|
T1 |
9398 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6019755 |
1 |
|
|
T1 |
5725 |
|
T14 |
45689 |
|
T17 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659195 |
1 |
|
|
T1 |
12090 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2459480 |
1 |
|
|
T1 |
3033 |
|
T14 |
16767 |
|
T17 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8141427 |
1 |
|
|
T1 |
8437 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5977248 |
1 |
|
|
T1 |
6686 |
|
T14 |
44222 |
|
T17 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1752121 |
1 |
|
|
T1 |
2011 |
|
T14 |
13031 |
|
T17 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1226915 |
1 |
|
|
T1 |
1523 |
|
T14 |
7857 |
|
T17 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1765647 |
1 |
|
|
T1 |
1642 |
|
T14 |
14424 |
|
T17 |
18 |
| auto[1] |
auto[1] |
auto[1] |
1232565 |
1 |
|
|
T1 |
1510 |
|
T14 |
8910 |
|
T17 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |