Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8120376 |
1 |
|
|
T1 |
8742 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5998299 |
1 |
|
|
T1 |
6381 |
|
T14 |
46132 |
|
T17 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659415 |
1 |
|
|
T1 |
12503 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2459260 |
1 |
|
|
T1 |
2620 |
|
T14 |
17672 |
|
T17 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8150924 |
1 |
|
|
T1 |
9201 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5967751 |
1 |
|
|
T1 |
5922 |
|
T14 |
45963 |
|
T17 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1752868 |
1 |
|
|
T1 |
1973 |
|
T14 |
14087 |
|
T17 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1228132 |
1 |
|
|
T1 |
1395 |
|
T14 |
8949 |
|
T17 |
19 |
| auto[1] |
auto[1] |
auto[0] |
1755623 |
1 |
|
|
T1 |
1329 |
|
T14 |
14204 |
|
T17 |
19 |
| auto[1] |
auto[1] |
auto[1] |
1231128 |
1 |
|
|
T1 |
1225 |
|
T14 |
8723 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |