Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8094458 |
1 |
|
|
T1 |
8325 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6024217 |
1 |
|
|
T1 |
6798 |
|
T14 |
42280 |
|
T17 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11649308 |
1 |
|
|
T1 |
12141 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2469367 |
1 |
|
|
T1 |
2982 |
|
T14 |
16819 |
|
T17 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8131083 |
1 |
|
|
T1 |
8688 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5987592 |
1 |
|
|
T1 |
6435 |
|
T14 |
43993 |
|
T17 |
64 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1744336 |
1 |
|
|
T1 |
1516 |
|
T14 |
14964 |
|
T17 |
25 |
| auto[1] |
auto[0] |
auto[1] |
1230707 |
1 |
|
|
T1 |
1354 |
|
T14 |
9133 |
|
T17 |
17 |
| auto[1] |
auto[1] |
auto[0] |
1773889 |
1 |
|
|
T1 |
1937 |
|
T14 |
12210 |
|
T17 |
15 |
| auto[1] |
auto[1] |
auto[1] |
1238660 |
1 |
|
|
T1 |
1628 |
|
T14 |
7686 |
|
T17 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |