Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8140319 |
1 |
|
|
T1 |
8850 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5978356 |
1 |
|
|
T1 |
6273 |
|
T14 |
46034 |
|
T17 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11654544 |
1 |
|
|
T1 |
12673 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2464131 |
1 |
|
|
T1 |
2450 |
|
T14 |
18597 |
|
T17 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8144675 |
1 |
|
|
T1 |
9817 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5974000 |
1 |
|
|
T1 |
5306 |
|
T14 |
47804 |
|
T17 |
51 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1757886 |
1 |
|
|
T1 |
1434 |
|
T14 |
14584 |
|
T17 |
22 |
| auto[1] |
auto[0] |
auto[1] |
1233531 |
1 |
|
|
T1 |
1262 |
|
T14 |
9003 |
|
T17 |
18 |
| auto[1] |
auto[1] |
auto[0] |
1751983 |
1 |
|
|
T1 |
1422 |
|
T14 |
14623 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1230600 |
1 |
|
|
T1 |
1188 |
|
T14 |
9594 |
|
T17 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |