Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8162628 |
1 |
|
|
T1 |
9041 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5956047 |
1 |
|
|
T1 |
6082 |
|
T14 |
45366 |
|
T17 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11652843 |
1 |
|
|
T1 |
11877 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2465832 |
1 |
|
|
T1 |
3246 |
|
T14 |
17463 |
|
T17 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8132963 |
1 |
|
|
T1 |
7736 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5985712 |
1 |
|
|
T1 |
7387 |
|
T14 |
45511 |
|
T17 |
66 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1768414 |
1 |
|
|
T1 |
2319 |
|
T14 |
13584 |
|
T17 |
19 |
| auto[1] |
auto[0] |
auto[1] |
1242232 |
1 |
|
|
T1 |
1821 |
|
T14 |
8797 |
|
T17 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1751466 |
1 |
|
|
T1 |
1822 |
|
T14 |
14464 |
|
T17 |
20 |
| auto[1] |
auto[1] |
auto[1] |
1223600 |
1 |
|
|
T1 |
1425 |
|
T14 |
8666 |
|
T17 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |