Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8114713 |
1 |
|
|
T1 |
7766 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6003962 |
1 |
|
|
T1 |
7357 |
|
T14 |
46384 |
|
T17 |
80 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11645810 |
1 |
|
|
T1 |
12263 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2472865 |
1 |
|
|
T1 |
2860 |
|
T14 |
17836 |
|
T17 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8108885 |
1 |
|
|
T1 |
8814 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6009790 |
1 |
|
|
T1 |
6309 |
|
T14 |
46109 |
|
T17 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1765494 |
1 |
|
|
T1 |
1290 |
|
T14 |
13907 |
|
T17 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1237076 |
1 |
|
|
T1 |
1262 |
|
T14 |
8646 |
|
T17 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1771431 |
1 |
|
|
T1 |
2159 |
|
T14 |
14366 |
|
T17 |
23 |
| auto[1] |
auto[1] |
auto[1] |
1235789 |
1 |
|
|
T1 |
1598 |
|
T14 |
9190 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |