Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8121124 |
1 |
|
|
T1 |
9386 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5997551 |
1 |
|
|
T1 |
5737 |
|
T14 |
44579 |
|
T17 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11651220 |
1 |
|
|
T1 |
12293 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2467455 |
1 |
|
|
T1 |
2830 |
|
T14 |
16968 |
|
T17 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8124237 |
1 |
|
|
T1 |
9133 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5994438 |
1 |
|
|
T1 |
5990 |
|
T14 |
45382 |
|
T17 |
69 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1763344 |
1 |
|
|
T1 |
1594 |
|
T14 |
13912 |
|
T17 |
20 |
| auto[1] |
auto[0] |
auto[1] |
1233187 |
1 |
|
|
T1 |
1418 |
|
T14 |
8132 |
|
T17 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1763639 |
1 |
|
|
T1 |
1566 |
|
T14 |
14502 |
|
T17 |
24 |
| auto[1] |
auto[1] |
auto[1] |
1234268 |
1 |
|
|
T1 |
1412 |
|
T14 |
8836 |
|
T17 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |