Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8109530 |
1 |
|
|
T1 |
9093 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6009145 |
1 |
|
|
T1 |
6030 |
|
T14 |
44654 |
|
T17 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11642070 |
1 |
|
|
T1 |
11903 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2476605 |
1 |
|
|
T1 |
3220 |
|
T14 |
17199 |
|
T17 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8092061 |
1 |
|
|
T1 |
7318 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6026614 |
1 |
|
|
T1 |
7805 |
|
T14 |
44921 |
|
T17 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1769257 |
1 |
|
|
T1 |
2631 |
|
T14 |
14182 |
|
T17 |
14 |
| auto[1] |
auto[0] |
auto[1] |
1239079 |
1 |
|
|
T1 |
1739 |
|
T14 |
8681 |
|
T17 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1780752 |
1 |
|
|
T1 |
1954 |
|
T14 |
13540 |
|
T17 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1237526 |
1 |
|
|
T1 |
1481 |
|
T14 |
8518 |
|
T17 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |