Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8148355 |
1 |
|
|
T1 |
8975 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5970320 |
1 |
|
|
T1 |
6148 |
|
T14 |
46431 |
|
T17 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659815 |
1 |
|
|
T1 |
11898 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2458860 |
1 |
|
|
T1 |
3225 |
|
T14 |
17852 |
|
T17 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8156161 |
1 |
|
|
T1 |
8043 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5962514 |
1 |
|
|
T1 |
7080 |
|
T14 |
46812 |
|
T17 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1763035 |
1 |
|
|
T1 |
2067 |
|
T14 |
14319 |
|
T17 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1235460 |
1 |
|
|
T1 |
1613 |
|
T14 |
8559 |
|
T17 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1740619 |
1 |
|
|
T1 |
1788 |
|
T14 |
14641 |
|
T18 |
40 |
| auto[1] |
auto[1] |
auto[1] |
1223400 |
1 |
|
|
T1 |
1612 |
|
T14 |
9293 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |