Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8113179 |
1 |
|
|
T1 |
9829 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6005496 |
1 |
|
|
T1 |
5294 |
|
T14 |
46948 |
|
T17 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11654506 |
1 |
|
|
T1 |
11925 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2464169 |
1 |
|
|
T1 |
3198 |
|
T14 |
16468 |
|
T17 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8136680 |
1 |
|
|
T1 |
7810 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5981995 |
1 |
|
|
T1 |
7313 |
|
T14 |
42900 |
|
T17 |
89 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1762811 |
1 |
|
|
T1 |
2689 |
|
T14 |
13229 |
|
T17 |
38 |
| auto[1] |
auto[0] |
auto[1] |
1233889 |
1 |
|
|
T1 |
2080 |
|
T14 |
8184 |
|
T17 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1755015 |
1 |
|
|
T1 |
1426 |
|
T14 |
13203 |
|
T17 |
19 |
| auto[1] |
auto[1] |
auto[1] |
1230280 |
1 |
|
|
T1 |
1118 |
|
T14 |
8284 |
|
T17 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |