Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8138058 |
1 |
|
|
T1 |
7366 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5980617 |
1 |
|
|
T1 |
7757 |
|
T14 |
47324 |
|
T17 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11657344 |
1 |
|
|
T1 |
12001 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
2461331 |
1 |
|
|
T1 |
3122 |
|
T14 |
17611 |
|
T17 |
29 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8141145 |
1 |
|
|
T1 |
8026 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5977530 |
1 |
|
|
T1 |
7097 |
|
T14 |
46002 |
|
T17 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1767130 |
1 |
|
|
T1 |
1392 |
|
T14 |
13524 |
|
T17 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1231312 |
1 |
|
|
T1 |
1272 |
|
T14 |
8457 |
|
T17 |
26 |
| auto[1] |
auto[1] |
auto[0] |
1749069 |
1 |
|
|
T1 |
2583 |
|
T14 |
14867 |
|
T17 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1230019 |
1 |
|
|
T1 |
1850 |
|
T14 |
9154 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |