Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8116835 |
1 |
|
|
T1 |
7361 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6001840 |
1 |
|
|
T1 |
7762 |
|
T14 |
47690 |
|
T17 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13345125 |
1 |
|
|
T1 |
13855 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
773550 |
1 |
|
|
T1 |
1268 |
|
T14 |
5639 |
|
T17 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8103432 |
1 |
|
|
T1 |
7119 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6015243 |
1 |
|
|
T1 |
8004 |
|
T14 |
45266 |
|
T17 |
48 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2620626 |
1 |
|
|
T1 |
2754 |
|
T14 |
18612 |
|
T17 |
23 |
| auto[1] |
auto[0] |
auto[1] |
386114 |
1 |
|
|
T1 |
518 |
|
T14 |
2550 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2621067 |
1 |
|
|
T1 |
3982 |
|
T14 |
21015 |
|
T17 |
22 |
| auto[1] |
auto[1] |
auto[1] |
387436 |
1 |
|
|
T1 |
750 |
|
T14 |
3089 |
|
T17 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |