Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8119092 |
1 |
|
|
T1 |
8075 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5999583 |
1 |
|
|
T1 |
7048 |
|
T14 |
45948 |
|
T17 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13343754 |
1 |
|
|
T1 |
14095 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
774921 |
1 |
|
|
T1 |
1028 |
|
T14 |
5546 |
|
T17 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8102298 |
1 |
|
|
T1 |
8494 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6016377 |
1 |
|
|
T1 |
6629 |
|
T14 |
44716 |
|
T17 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2625624 |
1 |
|
|
T1 |
2393 |
|
T14 |
19740 |
|
T17 |
8 |
| auto[1] |
auto[0] |
auto[1] |
388124 |
1 |
|
|
T1 |
391 |
|
T14 |
2829 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2615832 |
1 |
|
|
T1 |
3208 |
|
T14 |
19430 |
|
T18 |
122 |
| auto[1] |
auto[1] |
auto[1] |
386797 |
1 |
|
|
T1 |
637 |
|
T14 |
2717 |
|
T18 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |