Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8128184 |
1 |
|
|
T1 |
8704 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5990491 |
1 |
|
|
T1 |
6419 |
|
T14 |
45711 |
|
T17 |
54 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13348389 |
1 |
|
|
T1 |
14248 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
770286 |
1 |
|
|
T1 |
875 |
|
T14 |
5544 |
|
T17 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8136525 |
1 |
|
|
T1 |
9585 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5982150 |
1 |
|
|
T1 |
5538 |
|
T14 |
44833 |
|
T17 |
70 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2602339 |
1 |
|
|
T1 |
2659 |
|
T14 |
18680 |
|
T17 |
48 |
| auto[1] |
auto[0] |
auto[1] |
384846 |
1 |
|
|
T1 |
506 |
|
T14 |
2554 |
|
T17 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2609525 |
1 |
|
|
T1 |
2004 |
|
T14 |
20609 |
|
T17 |
18 |
| auto[1] |
auto[1] |
auto[1] |
385440 |
1 |
|
|
T1 |
369 |
|
T14 |
2990 |
|
T18 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |