Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8114860 |
1 |
|
|
T1 |
8212 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6003815 |
1 |
|
|
T1 |
6911 |
|
T14 |
45302 |
|
T17 |
42 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13351678 |
1 |
|
|
T1 |
14048 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
766997 |
1 |
|
|
T1 |
1075 |
|
T14 |
5910 |
|
T17 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8145675 |
1 |
|
|
T1 |
8281 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5973000 |
1 |
|
|
T1 |
6842 |
|
T14 |
47106 |
|
T17 |
93 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2610188 |
1 |
|
|
T1 |
2911 |
|
T14 |
21187 |
|
T17 |
47 |
| auto[1] |
auto[0] |
auto[1] |
384158 |
1 |
|
|
T1 |
557 |
|
T14 |
3089 |
|
T17 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2595815 |
1 |
|
|
T1 |
2856 |
|
T14 |
20009 |
|
T17 |
41 |
| auto[1] |
auto[1] |
auto[1] |
382839 |
1 |
|
|
T1 |
518 |
|
T14 |
2821 |
|
T17 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |