Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8114706 |
1 |
|
|
T1 |
6981 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
6003969 |
1 |
|
|
T1 |
8142 |
|
T14 |
45831 |
|
T17 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13352954 |
1 |
|
|
T1 |
14110 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
765721 |
1 |
|
|
T1 |
1013 |
|
T14 |
5504 |
|
T17 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8151010 |
1 |
|
|
T1 |
8629 |
|
T11 |
333 |
|
T12 |
209 |
| auto[1] |
5967665 |
1 |
|
|
T1 |
6494 |
|
T14 |
44881 |
|
T17 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2597246 |
1 |
|
|
T1 |
2166 |
|
T14 |
18877 |
|
T17 |
27 |
| auto[1] |
auto[0] |
auto[1] |
382163 |
1 |
|
|
T1 |
420 |
|
T14 |
2643 |
|
T17 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2604698 |
1 |
|
|
T1 |
3315 |
|
T14 |
20500 |
|
T17 |
24 |
| auto[1] |
auto[1] |
auto[1] |
383558 |
1 |
|
|
T1 |
593 |
|
T14 |
2861 |
|
T17 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |