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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
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T87 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.737914307 Jul 27 04:59:30 PM PDT 24 Jul 27 04:59:31 PM PDT 24 20264386 ps
T761 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3462583450 Jul 27 04:59:31 PM PDT 24 Jul 27 04:59:33 PM PDT 24 40922080 ps
T762 /workspace/coverage/cover_reg_top/45.gpio_intr_test.262630797 Jul 27 04:59:35 PM PDT 24 Jul 27 04:59:36 PM PDT 24 15314445 ps
T763 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2743156882 Jul 27 04:59:22 PM PDT 24 Jul 27 04:59:23 PM PDT 24 41680960 ps
T764 /workspace/coverage/cover_reg_top/36.gpio_intr_test.725886543 Jul 27 04:59:54 PM PDT 24 Jul 27 04:59:55 PM PDT 24 31184867 ps
T765 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2391217317 Jul 27 04:59:13 PM PDT 24 Jul 27 04:59:16 PM PDT 24 387330826 ps
T38 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3616682498 Jul 27 04:59:18 PM PDT 24 Jul 27 04:59:19 PM PDT 24 227541678 ps
T766 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4023892109 Jul 27 04:59:22 PM PDT 24 Jul 27 04:59:23 PM PDT 24 58340334 ps
T98 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3076627838 Jul 27 04:59:19 PM PDT 24 Jul 27 04:59:20 PM PDT 24 19137828 ps
T767 /workspace/coverage/cover_reg_top/32.gpio_intr_test.209309305 Jul 27 04:59:34 PM PDT 24 Jul 27 04:59:35 PM PDT 24 36108871 ps
T768 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3883147037 Jul 27 04:59:17 PM PDT 24 Jul 27 04:59:20 PM PDT 24 43748177 ps
T769 /workspace/coverage/cover_reg_top/43.gpio_intr_test.4077449004 Jul 27 04:59:57 PM PDT 24 Jul 27 04:59:58 PM PDT 24 14794267 ps
T99 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1001433071 Jul 27 04:59:23 PM PDT 24 Jul 27 04:59:24 PM PDT 24 100014988 ps
T770 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.960588866 Jul 27 04:59:00 PM PDT 24 Jul 27 04:59:00 PM PDT 24 13453846 ps
T771 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3053899038 Jul 27 04:59:23 PM PDT 24 Jul 27 04:59:24 PM PDT 24 21153681 ps
T772 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1331318148 Jul 27 04:59:13 PM PDT 24 Jul 27 04:59:13 PM PDT 24 18506761 ps
T773 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1941586794 Jul 27 04:59:35 PM PDT 24 Jul 27 04:59:35 PM PDT 24 14839667 ps
T88 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.567197206 Jul 27 04:59:23 PM PDT 24 Jul 27 04:59:25 PM PDT 24 32415348 ps
T774 /workspace/coverage/cover_reg_top/5.gpio_intr_test.4083894331 Jul 27 04:59:03 PM PDT 24 Jul 27 04:59:04 PM PDT 24 23549922 ps
T775 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1528137656 Jul 27 04:59:35 PM PDT 24 Jul 27 04:59:36 PM PDT 24 43874767 ps
T776 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2343469846 Jul 27 04:59:06 PM PDT 24 Jul 27 04:59:07 PM PDT 24 21175704 ps
T777 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1210124175 Jul 27 04:59:35 PM PDT 24 Jul 27 04:59:36 PM PDT 24 35338265 ps
T778 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1169414490 Jul 27 04:59:44 PM PDT 24 Jul 27 04:59:50 PM PDT 24 45904157 ps
T779 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4098409720 Jul 27 04:59:10 PM PDT 24 Jul 27 04:59:10 PM PDT 24 14788397 ps
T780 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2355106433 Jul 27 04:59:09 PM PDT 24 Jul 27 04:59:10 PM PDT 24 15558971 ps
T781 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3146040660 Jul 27 04:59:31 PM PDT 24 Jul 27 04:59:32 PM PDT 24 16112085 ps
T782 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4244775381 Jul 27 04:59:29 PM PDT 24 Jul 27 04:59:30 PM PDT 24 17715713 ps
T43 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2246924951 Jul 27 04:59:18 PM PDT 24 Jul 27 04:59:20 PM PDT 24 238325765 ps
T783 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2718959788 Jul 27 04:59:33 PM PDT 24 Jul 27 04:59:34 PM PDT 24 19099000 ps
T784 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1923837371 Jul 27 04:59:24 PM PDT 24 Jul 27 04:59:25 PM PDT 24 16777170 ps
T785 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1330326617 Jul 27 04:59:27 PM PDT 24 Jul 27 04:59:28 PM PDT 24 18566517 ps
T786 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2609757424 Jul 27 04:59:20 PM PDT 24 Jul 27 04:59:21 PM PDT 24 62972679 ps
T787 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1522829300 Jul 27 04:59:20 PM PDT 24 Jul 27 04:59:21 PM PDT 24 230243247 ps
T788 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1310428309 Jul 27 04:59:31 PM PDT 24 Jul 27 04:59:32 PM PDT 24 24207746 ps
T789 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2109459836 Jul 27 04:59:33 PM PDT 24 Jul 27 04:59:36 PM PDT 24 49818630 ps
T790 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3370795190 Jul 27 04:59:16 PM PDT 24 Jul 27 04:59:17 PM PDT 24 44239723 ps
T791 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4197583786 Jul 27 04:59:30 PM PDT 24 Jul 27 04:59:41 PM PDT 24 91494433 ps
T792 /workspace/coverage/cover_reg_top/10.gpio_intr_test.506333045 Jul 27 04:59:20 PM PDT 24 Jul 27 04:59:21 PM PDT 24 11557701 ps
T793 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1216345673 Jul 27 04:59:26 PM PDT 24 Jul 27 04:59:26 PM PDT 24 230857899 ps
T794 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2785214468 Jul 27 04:59:23 PM PDT 24 Jul 27 04:59:24 PM PDT 24 14428608 ps
T795 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2522906202 Jul 27 04:59:30 PM PDT 24 Jul 27 04:59:31 PM PDT 24 15514140 ps
T796 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2032348389 Jul 27 04:59:20 PM PDT 24 Jul 27 04:59:21 PM PDT 24 37874089 ps
T797 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3202565256 Jul 27 04:59:13 PM PDT 24 Jul 27 04:59:14 PM PDT 24 86127114 ps
T798 /workspace/coverage/cover_reg_top/39.gpio_intr_test.726410357 Jul 27 04:59:33 PM PDT 24 Jul 27 04:59:33 PM PDT 24 28371896 ps
T799 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.609548299 Jul 27 04:59:18 PM PDT 24 Jul 27 04:59:19 PM PDT 24 39663408 ps
T800 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2586362296 Jul 27 04:59:24 PM PDT 24 Jul 27 04:59:25 PM PDT 24 40237777 ps
T801 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1689349565 Jul 27 04:59:26 PM PDT 24 Jul 27 04:59:27 PM PDT 24 48196354 ps
T802 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2868699594 Jul 27 04:59:15 PM PDT 24 Jul 27 04:59:17 PM PDT 24 601348644 ps
T803 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2034567205 Jul 27 04:59:13 PM PDT 24 Jul 27 04:59:14 PM PDT 24 31703038 ps
T804 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.223241221 Jul 27 04:59:33 PM PDT 24 Jul 27 04:59:35 PM PDT 24 621307716 ps
T805 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.460935726 Jul 27 04:59:34 PM PDT 24 Jul 27 04:59:35 PM PDT 24 346508807 ps
T90 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2577577453 Jul 27 04:59:06 PM PDT 24 Jul 27 04:59:07 PM PDT 24 13240242 ps
T806 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3444612215 Jul 27 04:59:08 PM PDT 24 Jul 27 04:59:10 PM PDT 24 36856366 ps
T807 /workspace/coverage/cover_reg_top/31.gpio_intr_test.236743371 Jul 27 04:59:48 PM PDT 24 Jul 27 04:59:49 PM PDT 24 13838279 ps
T808 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2240544118 Jul 27 04:59:32 PM PDT 24 Jul 27 04:59:33 PM PDT 24 62360027 ps
T809 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1710702835 Jul 27 04:59:27 PM PDT 24 Jul 27 04:59:28 PM PDT 24 14885497 ps
T810 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2068178398 Jul 27 04:59:25 PM PDT 24 Jul 27 04:59:26 PM PDT 24 105000628 ps
T811 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2083023083 Jul 27 04:59:11 PM PDT 24 Jul 27 04:59:12 PM PDT 24 160482803 ps
T812 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2664183057 Jul 27 04:59:21 PM PDT 24 Jul 27 04:59:22 PM PDT 24 41638376 ps
T813 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3548359145 Jul 27 04:59:25 PM PDT 24 Jul 27 04:59:26 PM PDT 24 12676634 ps
T814 /workspace/coverage/cover_reg_top/1.gpio_intr_test.720286876 Jul 27 04:59:22 PM PDT 24 Jul 27 04:59:23 PM PDT 24 13122777 ps
T815 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3660870823 Jul 27 04:59:26 PM PDT 24 Jul 27 04:59:28 PM PDT 24 157908329 ps
T109 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1339059580 Jul 27 04:59:15 PM PDT 24 Jul 27 04:59:16 PM PDT 24 44656024 ps
T816 /workspace/coverage/cover_reg_top/47.gpio_intr_test.989025687 Jul 27 04:59:19 PM PDT 24 Jul 27 04:59:19 PM PDT 24 43549987 ps
T817 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3511088798 Jul 27 04:58:54 PM PDT 24 Jul 27 04:58:54 PM PDT 24 20580379 ps
T818 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3624068748 Jul 27 04:59:27 PM PDT 24 Jul 27 04:59:28 PM PDT 24 25317608 ps
T819 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3024669442 Jul 27 04:59:25 PM PDT 24 Jul 27 04:59:27 PM PDT 24 178596641 ps
T820 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1980287832 Jul 27 04:59:40 PM PDT 24 Jul 27 04:59:41 PM PDT 24 308561605 ps
T821 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1951173209 Jul 27 04:59:38 PM PDT 24 Jul 27 04:59:39 PM PDT 24 13181032 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1650238322 Jul 27 04:59:21 PM PDT 24 Jul 27 04:59:22 PM PDT 24 496932253 ps
T823 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.863313494 Jul 27 04:59:22 PM PDT 24 Jul 27 04:59:23 PM PDT 24 39285303 ps
T824 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3199919375 Jul 27 04:59:17 PM PDT 24 Jul 27 04:59:19 PM PDT 24 303488514 ps
T825 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.500718698 Jul 27 04:59:02 PM PDT 24 Jul 27 04:59:03 PM PDT 24 17422977 ps
T826 /workspace/coverage/cover_reg_top/49.gpio_intr_test.725395591 Jul 27 04:59:21 PM PDT 24 Jul 27 04:59:21 PM PDT 24 35718480 ps
T827 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4091652854 Jul 27 04:59:23 PM PDT 24 Jul 27 04:59:24 PM PDT 24 10401653 ps
T828 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2812603112 Jul 27 04:59:22 PM PDT 24 Jul 27 04:59:23 PM PDT 24 21879796 ps
T829 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2685537734 Jul 27 04:59:36 PM PDT 24 Jul 27 04:59:37 PM PDT 24 116085239 ps
T830 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1958471059 Jul 27 04:59:39 PM PDT 24 Jul 27 04:59:40 PM PDT 24 44582756 ps
T831 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.843627306 Jul 27 04:59:15 PM PDT 24 Jul 27 04:59:16 PM PDT 24 27659017 ps
T832 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1553060235 Jul 27 04:59:26 PM PDT 24 Jul 27 04:59:27 PM PDT 24 35741310 ps
T91 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2834010031 Jul 27 04:59:28 PM PDT 24 Jul 27 04:59:29 PM PDT 24 11145844 ps
T833 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1619648398 Jul 27 04:59:09 PM PDT 24 Jul 27 04:59:11 PM PDT 24 1529165288 ps
T834 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3160919383 Jul 27 04:59:30 PM PDT 24 Jul 27 04:59:32 PM PDT 24 111796965 ps
T835 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2141785073 Jul 27 04:59:15 PM PDT 24 Jul 27 04:59:16 PM PDT 24 14949592 ps
T836 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3258783709 Jul 27 05:00:27 PM PDT 24 Jul 27 05:00:28 PM PDT 24 56059735 ps
T837 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2224831518 Jul 27 04:59:01 PM PDT 24 Jul 27 04:59:12 PM PDT 24 21968023 ps
T838 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.491498730 Jul 27 04:59:15 PM PDT 24 Jul 27 04:59:17 PM PDT 24 107390025 ps
T92 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1155265330 Jul 27 04:59:11 PM PDT 24 Jul 27 04:59:13 PM PDT 24 1024365117 ps
T839 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1147181959 Jul 27 04:58:58 PM PDT 24 Jul 27 04:58:59 PM PDT 24 20085361 ps
T840 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1014681712 Jul 27 04:59:20 PM PDT 24 Jul 27 04:59:21 PM PDT 24 105255370 ps
T841 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3732697347 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:20 PM PDT 24 112771731 ps
T842 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.270029111 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:27 PM PDT 24 151142251 ps
T843 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1258759232 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:20 PM PDT 24 193012303 ps
T844 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.150549995 Jul 27 05:55:27 PM PDT 24 Jul 27 05:55:28 PM PDT 24 84327438 ps
T845 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1223637636 Jul 27 05:55:28 PM PDT 24 Jul 27 05:55:29 PM PDT 24 34194151 ps
T846 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1702679791 Jul 27 05:55:20 PM PDT 24 Jul 27 05:55:21 PM PDT 24 35983017 ps
T847 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1880280788 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:21 PM PDT 24 76287681 ps
T848 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4260022098 Jul 27 05:55:31 PM PDT 24 Jul 27 05:55:32 PM PDT 24 454140335 ps
T849 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3179921193 Jul 27 05:55:30 PM PDT 24 Jul 27 05:55:32 PM PDT 24 248398143 ps
T850 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3085582705 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:26 PM PDT 24 126608565 ps
T851 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2656344791 Jul 27 05:55:20 PM PDT 24 Jul 27 05:55:22 PM PDT 24 42569229 ps
T852 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3517379849 Jul 27 05:55:31 PM PDT 24 Jul 27 05:55:33 PM PDT 24 872334195 ps
T853 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2181536349 Jul 27 05:55:28 PM PDT 24 Jul 27 05:55:30 PM PDT 24 196660063 ps
T854 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3059326146 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:26 PM PDT 24 149434646 ps
T855 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2875972869 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:27 PM PDT 24 245772053 ps
T856 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2449569598 Jul 27 05:55:24 PM PDT 24 Jul 27 05:55:25 PM PDT 24 51408778 ps
T857 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3686373823 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:26 PM PDT 24 120418914 ps
T858 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.289972772 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:26 PM PDT 24 29651491 ps
T859 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4183689601 Jul 27 05:55:31 PM PDT 24 Jul 27 05:55:32 PM PDT 24 137976113 ps
T860 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.918296502 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:27 PM PDT 24 142939695 ps
T861 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1623723774 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:24 PM PDT 24 128579323 ps
T862 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3880158264 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:27 PM PDT 24 73400335 ps
T863 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1094280034 Jul 27 05:55:27 PM PDT 24 Jul 27 05:55:29 PM PDT 24 1100594824 ps
T864 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.486351332 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:27 PM PDT 24 107026676 ps
T865 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3456565638 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:20 PM PDT 24 211072220 ps
T866 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4226825104 Jul 27 05:55:24 PM PDT 24 Jul 27 05:55:25 PM PDT 24 29120080 ps
T867 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2715234736 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 42739879 ps
T868 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2051864659 Jul 27 05:55:32 PM PDT 24 Jul 27 05:55:33 PM PDT 24 24616785 ps
T869 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1151419839 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 109033895 ps
T870 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.805677126 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 108158707 ps
T871 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4095056337 Jul 27 05:55:27 PM PDT 24 Jul 27 05:55:28 PM PDT 24 73381476 ps
T872 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3652804533 Jul 27 05:55:21 PM PDT 24 Jul 27 05:55:22 PM PDT 24 65128687 ps
T873 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3613624103 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 190701477 ps
T874 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2325976388 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:24 PM PDT 24 223924959 ps
T875 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3996277741 Jul 27 05:55:32 PM PDT 24 Jul 27 05:55:33 PM PDT 24 43789628 ps
T876 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3305136972 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:27 PM PDT 24 45590834 ps
T877 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2504935919 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:20 PM PDT 24 120899306 ps
T878 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3591645085 Jul 27 05:55:28 PM PDT 24 Jul 27 05:55:30 PM PDT 24 355622651 ps
T879 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1217613957 Jul 27 05:55:32 PM PDT 24 Jul 27 05:55:33 PM PDT 24 39904815 ps
T880 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.60872867 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:27 PM PDT 24 90671117 ps
T881 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3326923706 Jul 27 05:55:29 PM PDT 24 Jul 27 05:55:31 PM PDT 24 77040681 ps
T882 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3139601962 Jul 27 05:55:30 PM PDT 24 Jul 27 05:55:32 PM PDT 24 63646040 ps
T883 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3464908376 Jul 27 05:55:20 PM PDT 24 Jul 27 05:55:21 PM PDT 24 142973252 ps
T884 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3856494049 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:26 PM PDT 24 76235194 ps
T885 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1976037883 Jul 27 05:55:32 PM PDT 24 Jul 27 05:55:34 PM PDT 24 99617714 ps
T886 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2467360876 Jul 27 05:55:24 PM PDT 24 Jul 27 05:55:25 PM PDT 24 55177495 ps
T887 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1322719195 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:24 PM PDT 24 57253050 ps
T888 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1554837193 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:27 PM PDT 24 216152171 ps
T889 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2988822767 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:26 PM PDT 24 92487391 ps
T890 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1905442505 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:26 PM PDT 24 131049629 ps
T891 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2353318584 Jul 27 05:55:31 PM PDT 24 Jul 27 05:55:32 PM PDT 24 80732057 ps
T892 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3680321457 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:24 PM PDT 24 141178278 ps
T893 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1585787332 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:28 PM PDT 24 205868647 ps
T894 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3140364586 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:28 PM PDT 24 34256328 ps
T895 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3161270446 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 128700467 ps
T896 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4252962883 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:28 PM PDT 24 47513119 ps
T897 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2133316616 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 35000860 ps
T898 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3382818178 Jul 27 05:55:24 PM PDT 24 Jul 27 05:55:26 PM PDT 24 53993631 ps
T899 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2028617254 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:20 PM PDT 24 98219428 ps
T900 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2885992781 Jul 27 05:55:22 PM PDT 24 Jul 27 05:55:23 PM PDT 24 180614289 ps
T901 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2299697263 Jul 27 05:55:17 PM PDT 24 Jul 27 05:55:19 PM PDT 24 65649253 ps
T902 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.823732954 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:20 PM PDT 24 35184471 ps
T903 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4082168000 Jul 27 05:55:21 PM PDT 24 Jul 27 05:55:21 PM PDT 24 23503205 ps
T904 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1302258883 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 161746761 ps
T905 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.637719599 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:25 PM PDT 24 152898046 ps
T906 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1903669461 Jul 27 05:55:21 PM PDT 24 Jul 27 05:55:22 PM PDT 24 44432212 ps
T907 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3365472581 Jul 27 05:55:30 PM PDT 24 Jul 27 05:55:32 PM PDT 24 80100319 ps
T908 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1937333596 Jul 27 05:55:21 PM PDT 24 Jul 27 05:55:22 PM PDT 24 556133345 ps
T909 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.193723653 Jul 27 05:55:24 PM PDT 24 Jul 27 05:55:26 PM PDT 24 91735439 ps
T910 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2253516717 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:20 PM PDT 24 33711518 ps
T911 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.333227272 Jul 27 05:55:17 PM PDT 24 Jul 27 05:55:18 PM PDT 24 33220339 ps
T912 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3250776629 Jul 27 05:55:16 PM PDT 24 Jul 27 05:55:17 PM PDT 24 827938988 ps
T913 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1184344834 Jul 27 05:55:17 PM PDT 24 Jul 27 05:55:18 PM PDT 24 216308615 ps
T914 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894588030 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:28 PM PDT 24 343209464 ps
T915 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3448364359 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:24 PM PDT 24 97624061 ps
T916 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.747487988 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:24 PM PDT 24 268862104 ps
T917 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3824982878 Jul 27 05:55:28 PM PDT 24 Jul 27 05:55:30 PM PDT 24 74339001 ps
T918 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.72036525 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 94138241 ps
T919 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2508112300 Jul 27 05:55:20 PM PDT 24 Jul 27 05:55:21 PM PDT 24 65494915 ps
T920 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2711495180 Jul 27 05:55:27 PM PDT 24 Jul 27 05:55:29 PM PDT 24 39422165 ps
T921 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1212575587 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:20 PM PDT 24 109585790 ps
T922 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3563466310 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:27 PM PDT 24 72165313 ps
T923 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3011385779 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:24 PM PDT 24 48670487 ps
T924 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3678570208 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 38369273 ps
T925 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3874338153 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:26 PM PDT 24 145561407 ps
T926 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1045557428 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:26 PM PDT 24 33906440 ps
T927 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.324806724 Jul 27 05:55:32 PM PDT 24 Jul 27 05:55:34 PM PDT 24 134979773 ps
T928 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2409185404 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:27 PM PDT 24 89023997 ps
T929 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2927478486 Jul 27 05:55:28 PM PDT 24 Jul 27 05:55:29 PM PDT 24 419536099 ps
T930 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.282932849 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:28 PM PDT 24 79747169 ps
T931 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2432470038 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:27 PM PDT 24 108727976 ps
T932 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.454606179 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:27 PM PDT 24 41546766 ps
T933 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.152104126 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:21 PM PDT 24 46371520 ps
T934 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3964194654 Jul 27 05:55:25 PM PDT 24 Jul 27 05:55:27 PM PDT 24 78395755 ps
T935 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.863811209 Jul 27 05:55:23 PM PDT 24 Jul 27 05:55:25 PM PDT 24 96538799 ps
T936 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1516488260 Jul 27 05:55:21 PM PDT 24 Jul 27 05:55:22 PM PDT 24 45448832 ps
T937 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3179039857 Jul 27 05:55:26 PM PDT 24 Jul 27 05:55:28 PM PDT 24 29100069 ps
T938 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.112132830 Jul 27 05:55:18 PM PDT 24 Jul 27 05:55:19 PM PDT 24 107190461 ps
T939 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3214256296 Jul 27 05:55:31 PM PDT 24 Jul 27 05:55:32 PM PDT 24 263002142 ps
T940 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3256205689 Jul 27 05:55:19 PM PDT 24 Jul 27 05:55:20 PM PDT 24 68654070 ps

Test location /workspace/coverage/default/33.gpio_stress_all.3546568487
Short name T1
Test name
Test status
Simulation time 8477019920 ps
CPU time 24.77 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:54:09 PM PDT 24
Peak memory 198648 kb
Host smart-f57e42a9-dab7-4ee6-b549-ee436a133356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546568487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3546568487
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2803735821
Short name T118
Test name
Test status
Simulation time 311161739 ps
CPU time 2.68 seconds
Started Jul 27 05:54:16 PM PDT 24
Finished Jul 27 05:54:19 PM PDT 24
Peak memory 198596 kb
Host smart-6bcfa63d-65f0-4e33-8b24-64322b61084f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803735821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2803735821
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2787581182
Short name T25
Test name
Test status
Simulation time 32607971824 ps
CPU time 688.67 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 06:05:37 PM PDT 24
Peak memory 198744 kb
Host smart-2b2854a2-b0bc-4999-925c-f048e6a5e01a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2787581182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2787581182
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3232235025
Short name T32
Test name
Test status
Simulation time 75796881 ps
CPU time 0.87 seconds
Started Jul 27 05:52:17 PM PDT 24
Finished Jul 27 05:52:18 PM PDT 24
Peak memory 215336 kb
Host smart-a9d4d7fb-8b02-4cf9-87b0-05d0b7aedf46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232235025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3232235025
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2095823218
Short name T76
Test name
Test status
Simulation time 22795323 ps
CPU time 0.61 seconds
Started Jul 27 04:59:28 PM PDT 24
Finished Jul 27 04:59:28 PM PDT 24
Peak memory 194868 kb
Host smart-559d8cc3-e68d-46e9-9e49-0519ea08741c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095823218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2095823218
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2052313278
Short name T29
Test name
Test status
Simulation time 244251978 ps
CPU time 1.46 seconds
Started Jul 27 04:59:09 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 198272 kb
Host smart-73a1e899-d08d-4354-af3e-ba81109130af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052313278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2052313278
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2509491879
Short name T136
Test name
Test status
Simulation time 36283838 ps
CPU time 0.56 seconds
Started Jul 27 05:52:45 PM PDT 24
Finished Jul 27 05:52:45 PM PDT 24
Peak memory 194652 kb
Host smart-3ad5b0d8-0fab-42b0-9889-8a570297c1e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509491879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2509491879
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1650238322
Short name T822
Test name
Test status
Simulation time 496932253 ps
CPU time 1.38 seconds
Started Jul 27 04:59:21 PM PDT 24
Finished Jul 27 04:59:22 PM PDT 24
Peak memory 198388 kb
Host smart-0da0419c-6ab1-4e7d-9863-0343d722e1c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650238322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1650238322
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2535948938
Short name T89
Test name
Test status
Simulation time 380104976 ps
CPU time 3.51 seconds
Started Jul 27 04:58:58 PM PDT 24
Finished Jul 27 04:59:02 PM PDT 24
Peak memory 197500 kb
Host smart-9c70295f-79e9-4caa-9daf-ce94caf655d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535948938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2535948938
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3263590616
Short name T94
Test name
Test status
Simulation time 66104970 ps
CPU time 0.67 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 195912 kb
Host smart-f9dd626e-84ca-4eb5-8666-f35d4cdc67eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263590616 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3263590616
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1014681712
Short name T840
Test name
Test status
Simulation time 105255370 ps
CPU time 1.16 seconds
Started Jul 27 04:59:20 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 198348 kb
Host smart-252ffe02-5d9e-4d17-be91-dc816c8c1aea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014681712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1014681712
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3518969511
Short name T82
Test name
Test status
Simulation time 55538857 ps
CPU time 0.63 seconds
Started Jul 27 04:59:31 PM PDT 24
Finished Jul 27 04:59:32 PM PDT 24
Peak memory 194716 kb
Host smart-9b7aaa75-0043-4e8a-9d0a-080536d23368
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518969511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3518969511
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4288410133
Short name T79
Test name
Test status
Simulation time 17594371 ps
CPU time 0.67 seconds
Started Jul 27 04:59:14 PM PDT 24
Finished Jul 27 04:59:15 PM PDT 24
Peak memory 194884 kb
Host smart-85594807-86ed-4f43-a108-09e6dbd4e181
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288410133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4288410133
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3202565256
Short name T797
Test name
Test status
Simulation time 86127114 ps
CPU time 1.18 seconds
Started Jul 27 04:59:13 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 198376 kb
Host smart-e1ab93cb-5e5c-4a1b-8019-0ce27aa6ab89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202565256 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3202565256
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2338634768
Short name T86
Test name
Test status
Simulation time 22790090 ps
CPU time 0.63 seconds
Started Jul 27 04:59:08 PM PDT 24
Finished Jul 27 04:59:09 PM PDT 24
Peak memory 195224 kb
Host smart-0bed2cce-9771-4231-894f-902120dcc822
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338634768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2338634768
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1378655669
Short name T751
Test name
Test status
Simulation time 18666325 ps
CPU time 0.6 seconds
Started Jul 27 04:59:04 PM PDT 24
Finished Jul 27 04:59:05 PM PDT 24
Peak memory 194112 kb
Host smart-4f5d8cb2-1a7b-4469-922c-9259a4aa20c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378655669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1378655669
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2343469846
Short name T776
Test name
Test status
Simulation time 21175704 ps
CPU time 1.1 seconds
Started Jul 27 04:59:06 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 198392 kb
Host smart-be5a4c77-4f5f-4b81-ad8a-d991fe7c84a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343469846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2343469846
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3024669442
Short name T819
Test name
Test status
Simulation time 178596641 ps
CPU time 1.42 seconds
Started Jul 27 04:59:25 PM PDT 24
Finished Jul 27 04:59:27 PM PDT 24
Peak memory 198360 kb
Host smart-90cd4fc6-4958-4cb7-99a4-e448e77e6b93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024669442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3024669442
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1424810034
Short name T85
Test name
Test status
Simulation time 75651789 ps
CPU time 0.86 seconds
Started Jul 27 04:59:06 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 196792 kb
Host smart-1fe03719-08ed-47b1-8ace-291ab843d48d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424810034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1424810034
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1155265330
Short name T92
Test name
Test status
Simulation time 1024365117 ps
CPU time 2.38 seconds
Started Jul 27 04:59:11 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 197060 kb
Host smart-b0867faf-258c-4d05-9d29-1306170570ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155265330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1155265330
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2224831518
Short name T837
Test name
Test status
Simulation time 21968023 ps
CPU time 0.65 seconds
Started Jul 27 04:59:01 PM PDT 24
Finished Jul 27 04:59:12 PM PDT 24
Peak memory 195500 kb
Host smart-eb02c344-e47d-4b7a-98ea-5ab1d0c349bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224831518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2224831518
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3444612215
Short name T806
Test name
Test status
Simulation time 36856366 ps
CPU time 1.6 seconds
Started Jul 27 04:59:08 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 198356 kb
Host smart-78bc2f23-eebb-4391-975b-d4afe6974edd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444612215 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3444612215
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3237878878
Short name T745
Test name
Test status
Simulation time 14001455 ps
CPU time 0.61 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 194724 kb
Host smart-6a502ccf-c712-4b30-8a47-3dedfd50b5b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237878878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3237878878
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.720286876
Short name T814
Test name
Test status
Simulation time 13122777 ps
CPU time 0.66 seconds
Started Jul 27 04:59:22 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 194640 kb
Host smart-eaa67633-e70e-42bb-b642-c5a5a4a02606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720286876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.720286876
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3511088798
Short name T817
Test name
Test status
Simulation time 20580379 ps
CPU time 0.64 seconds
Started Jul 27 04:58:54 PM PDT 24
Finished Jul 27 04:58:54 PM PDT 24
Peak memory 195224 kb
Host smart-94d03f8f-9436-4ec3-8702-e32a54a1aed8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511088798 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3511088798
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2746369851
Short name T738
Test name
Test status
Simulation time 25723346 ps
CPU time 1.21 seconds
Started Jul 27 04:59:12 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 198300 kb
Host smart-77d0d689-8555-48d8-b386-c7ad765d3847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746369851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2746369851
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4104255864
Short name T716
Test name
Test status
Simulation time 115551924 ps
CPU time 0.88 seconds
Started Jul 27 04:59:13 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 198244 kb
Host smart-51cab6af-ab20-44ee-81e3-fa533375c252
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104255864 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.4104255864
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2785214468
Short name T794
Test name
Test status
Simulation time 14428608 ps
CPU time 0.61 seconds
Started Jul 27 04:59:23 PM PDT 24
Finished Jul 27 04:59:24 PM PDT 24
Peak memory 195136 kb
Host smart-68c69a24-287b-4d32-a9fb-e7578e9beb45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785214468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2785214468
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.506333045
Short name T792
Test name
Test status
Simulation time 11557701 ps
CPU time 0.6 seconds
Started Jul 27 04:59:20 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 194088 kb
Host smart-c340a6ca-d478-4765-a7b1-bcafabef7dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506333045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.506333045
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2718959788
Short name T783
Test name
Test status
Simulation time 19099000 ps
CPU time 0.81 seconds
Started Jul 27 04:59:33 PM PDT 24
Finished Jul 27 04:59:34 PM PDT 24
Peak memory 197496 kb
Host smart-cc5f40b8-2e43-49ac-846d-4bce81c6719c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718959788 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2718959788
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1588430027
Short name T743
Test name
Test status
Simulation time 154017884 ps
CPU time 1.02 seconds
Started Jul 27 04:59:17 PM PDT 24
Finished Jul 27 04:59:18 PM PDT 24
Peak memory 198128 kb
Host smart-4fbae647-85ee-49f2-9959-8fdf5a5184e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588430027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1588430027
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1522829300
Short name T787
Test name
Test status
Simulation time 230243247 ps
CPU time 0.78 seconds
Started Jul 27 04:59:20 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 198208 kb
Host smart-912dc524-f79e-4145-a324-f948f9a6d48d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522829300 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1522829300
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.737914307
Short name T87
Test name
Test status
Simulation time 20264386 ps
CPU time 0.59 seconds
Started Jul 27 04:59:30 PM PDT 24
Finished Jul 27 04:59:31 PM PDT 24
Peak memory 195816 kb
Host smart-1328ea37-7eb5-45b5-a1c6-f58c69b3377d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737914307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.737914307
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1169414490
Short name T778
Test name
Test status
Simulation time 45904157 ps
CPU time 0.56 seconds
Started Jul 27 04:59:44 PM PDT 24
Finished Jul 27 04:59:50 PM PDT 24
Peak memory 194608 kb
Host smart-5ba34cea-e560-4ba7-8e96-a00b39b95ce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169414490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1169414490
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1853235418
Short name T93
Test name
Test status
Simulation time 101930225 ps
CPU time 0.79 seconds
Started Jul 27 04:59:40 PM PDT 24
Finished Jul 27 04:59:41 PM PDT 24
Peak memory 197204 kb
Host smart-6a0b78c7-60ab-447d-b7a8-2c9d043a86fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853235418 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1853235418
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.517607930
Short name T722
Test name
Test status
Simulation time 114143483 ps
CPU time 2.03 seconds
Started Jul 27 04:59:32 PM PDT 24
Finished Jul 27 04:59:34 PM PDT 24
Peak memory 198328 kb
Host smart-4840bc28-0b28-45c7-afc2-cbdb1f4f51ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517607930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.517607930
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3616682498
Short name T38
Test name
Test status
Simulation time 227541678 ps
CPU time 1.48 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 04:59:19 PM PDT 24
Peak memory 198300 kb
Host smart-f7c7d498-4eb5-4ca0-a53a-1436aeec4f4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616682498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3616682498
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2812603112
Short name T828
Test name
Test status
Simulation time 21879796 ps
CPU time 0.93 seconds
Started Jul 27 04:59:22 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 198256 kb
Host smart-f7a22d96-7113-4d3f-9fb9-e2ffc357de29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812603112 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2812603112
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2834010031
Short name T91
Test name
Test status
Simulation time 11145844 ps
CPU time 0.57 seconds
Started Jul 27 04:59:28 PM PDT 24
Finished Jul 27 04:59:29 PM PDT 24
Peak memory 193840 kb
Host smart-c911a3a4-446e-4a24-b536-105a90b9fb13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834010031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2834010031
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1528137656
Short name T775
Test name
Test status
Simulation time 43874767 ps
CPU time 0.56 seconds
Started Jul 27 04:59:35 PM PDT 24
Finished Jul 27 04:59:36 PM PDT 24
Peak memory 194008 kb
Host smart-de378a3d-6253-4aa8-b09f-a6298d74ba63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528137656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1528137656
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3076627838
Short name T98
Test name
Test status
Simulation time 19137828 ps
CPU time 0.78 seconds
Started Jul 27 04:59:19 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 197192 kb
Host smart-6e37a239-fabd-4b3b-b1bc-62e0803f05ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076627838 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3076627838
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3160919383
Short name T834
Test name
Test status
Simulation time 111796965 ps
CPU time 1.97 seconds
Started Jul 27 04:59:30 PM PDT 24
Finished Jul 27 04:59:32 PM PDT 24
Peak memory 198352 kb
Host smart-2d6d69f6-cd32-4893-a7ce-3d76ee190733
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160919383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3160919383
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1339059580
Short name T109
Test name
Test status
Simulation time 44656024 ps
CPU time 0.86 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 198108 kb
Host smart-308e204a-7b4e-4d1f-bfae-e92c27db51d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339059580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1339059580
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4197583786
Short name T791
Test name
Test status
Simulation time 91494433 ps
CPU time 1.18 seconds
Started Jul 27 04:59:30 PM PDT 24
Finished Jul 27 04:59:41 PM PDT 24
Peak memory 198436 kb
Host smart-b1558d37-9226-4d55-8e31-f394f7900158
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197583786 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4197583786
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4244775381
Short name T782
Test name
Test status
Simulation time 17715713 ps
CPU time 0.59 seconds
Started Jul 27 04:59:29 PM PDT 24
Finished Jul 27 04:59:30 PM PDT 24
Peak memory 193576 kb
Host smart-5afede6b-ca24-4530-850f-f79cd5e9ac0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244775381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4244775381
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2664183057
Short name T812
Test name
Test status
Simulation time 41638376 ps
CPU time 0.6 seconds
Started Jul 27 04:59:21 PM PDT 24
Finished Jul 27 04:59:22 PM PDT 24
Peak memory 194044 kb
Host smart-c62ad1d2-edfa-496f-853d-38b490de4295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664183057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2664183057
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2068178398
Short name T810
Test name
Test status
Simulation time 105000628 ps
CPU time 0.74 seconds
Started Jul 27 04:59:25 PM PDT 24
Finished Jul 27 04:59:26 PM PDT 24
Peak memory 196556 kb
Host smart-7510b489-e410-4783-89b7-6870e92e082c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068178398 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2068178398
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2345674635
Short name T734
Test name
Test status
Simulation time 66292902 ps
CPU time 3.22 seconds
Started Jul 27 04:59:33 PM PDT 24
Finished Jul 27 04:59:38 PM PDT 24
Peak memory 198344 kb
Host smart-eb4836bd-b9c6-4fba-addc-d61b3fb1074c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345674635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2345674635
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3171264969
Short name T28
Test name
Test status
Simulation time 155814802 ps
CPU time 0.91 seconds
Started Jul 27 04:59:28 PM PDT 24
Finished Jul 27 04:59:29 PM PDT 24
Peak memory 197468 kb
Host smart-10035f4a-9950-440b-8c1b-833e139f37d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171264969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3171264969
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3624068748
Short name T818
Test name
Test status
Simulation time 25317608 ps
CPU time 0.76 seconds
Started Jul 27 04:59:27 PM PDT 24
Finished Jul 27 04:59:28 PM PDT 24
Peak memory 198156 kb
Host smart-0ec619a5-1714-4c67-a817-b772c56e567e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624068748 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3624068748
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4101246034
Short name T712
Test name
Test status
Simulation time 15136566 ps
CPU time 0.56 seconds
Started Jul 27 04:59:11 PM PDT 24
Finished Jul 27 04:59:11 PM PDT 24
Peak memory 194880 kb
Host smart-663de950-b6e8-4e13-b4da-b70d50148e16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101246034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4101246034
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1707441548
Short name T747
Test name
Test status
Simulation time 23414403 ps
CPU time 0.59 seconds
Started Jul 27 04:59:17 PM PDT 24
Finished Jul 27 04:59:18 PM PDT 24
Peak memory 194720 kb
Host smart-50c2d315-252b-4915-91ab-169e47dbc803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707441548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1707441548
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2240544118
Short name T808
Test name
Test status
Simulation time 62360027 ps
CPU time 0.63 seconds
Started Jul 27 04:59:32 PM PDT 24
Finished Jul 27 04:59:33 PM PDT 24
Peak memory 194908 kb
Host smart-3fae0959-e58c-4fb8-bf8b-bffbe8520ab1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240544118 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2240544118
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.223241221
Short name T804
Test name
Test status
Simulation time 621307716 ps
CPU time 2 seconds
Started Jul 27 04:59:33 PM PDT 24
Finished Jul 27 04:59:35 PM PDT 24
Peak memory 198388 kb
Host smart-17357acf-8165-4257-897f-0e8869c9e588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223241221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.223241221
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2868699594
Short name T802
Test name
Test status
Simulation time 601348644 ps
CPU time 1.43 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 198360 kb
Host smart-f6afde9d-2307-4bde-91fc-6f1574f9387d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868699594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2868699594
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.609548299
Short name T799
Test name
Test status
Simulation time 39663408 ps
CPU time 1.05 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 04:59:19 PM PDT 24
Peak memory 198232 kb
Host smart-2d8e16d3-be20-4d39-a624-198338f76a40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609548299 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.609548299
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1341310001
Short name T759
Test name
Test status
Simulation time 27896091 ps
CPU time 0.67 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 195236 kb
Host smart-457afb7d-92be-40de-98f1-520e382b41dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341310001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1341310001
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2586362296
Short name T800
Test name
Test status
Simulation time 40237777 ps
CPU time 0.58 seconds
Started Jul 27 04:59:24 PM PDT 24
Finished Jul 27 04:59:25 PM PDT 24
Peak memory 194004 kb
Host smart-66af5bf5-3cc1-46f9-9ed0-c396932e6168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586362296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2586362296
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2109459836
Short name T789
Test name
Test status
Simulation time 49818630 ps
CPU time 0.72 seconds
Started Jul 27 04:59:33 PM PDT 24
Finished Jul 27 04:59:36 PM PDT 24
Peak memory 196560 kb
Host smart-84df81a3-6caa-49e0-b2ae-f8a8e234923f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109459836 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2109459836
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3660870823
Short name T815
Test name
Test status
Simulation time 157908329 ps
CPU time 2.14 seconds
Started Jul 27 04:59:26 PM PDT 24
Finished Jul 27 04:59:28 PM PDT 24
Peak memory 198296 kb
Host smart-58d5c692-e880-481a-9928-21afe17c2adf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660870823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3660870823
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3190308632
Short name T753
Test name
Test status
Simulation time 49772509 ps
CPU time 0.83 seconds
Started Jul 27 04:59:30 PM PDT 24
Finished Jul 27 04:59:31 PM PDT 24
Peak memory 197544 kb
Host smart-feaccf4e-e5af-46d0-8ba4-86d3d3824562
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190308632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3190308632
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3150597231
Short name T725
Test name
Test status
Simulation time 55209519 ps
CPU time 0.83 seconds
Started Jul 27 04:59:24 PM PDT 24
Finished Jul 27 04:59:25 PM PDT 24
Peak memory 198232 kb
Host smart-ae824883-5341-4535-b809-6ae7c244d499
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150597231 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3150597231
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1710702835
Short name T809
Test name
Test status
Simulation time 14885497 ps
CPU time 0.58 seconds
Started Jul 27 04:59:27 PM PDT 24
Finished Jul 27 04:59:28 PM PDT 24
Peak memory 194984 kb
Host smart-6b9a40b3-f4ea-4454-b7ec-ef4877191400
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710702835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1710702835
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.414709277
Short name T726
Test name
Test status
Simulation time 16138302 ps
CPU time 0.61 seconds
Started Jul 27 04:59:24 PM PDT 24
Finished Jul 27 04:59:25 PM PDT 24
Peak memory 194028 kb
Host smart-3cf6bafa-a00f-4f1a-948f-ba327c12269c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414709277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.414709277
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.648609299
Short name T77
Test name
Test status
Simulation time 29437537 ps
CPU time 0.75 seconds
Started Jul 27 04:59:35 PM PDT 24
Finished Jul 27 04:59:36 PM PDT 24
Peak memory 196868 kb
Host smart-9a943865-6832-4119-a588-6cf4b7e8fea0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648609299 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.648609299
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3883147037
Short name T768
Test name
Test status
Simulation time 43748177 ps
CPU time 2.07 seconds
Started Jul 27 04:59:17 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 198312 kb
Host smart-c8c4645a-b329-4ce1-8fad-8f31c21db2d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883147037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3883147037
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.650456315
Short name T42
Test name
Test status
Simulation time 90421211 ps
CPU time 1.36 seconds
Started Jul 27 04:59:23 PM PDT 24
Finished Jul 27 04:59:24 PM PDT 24
Peak memory 198264 kb
Host smart-54334eca-57e4-4de2-887f-07bae27b8312
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650456315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.650456315
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3258783709
Short name T836
Test name
Test status
Simulation time 56059735 ps
CPU time 0.77 seconds
Started Jul 27 05:00:27 PM PDT 24
Finished Jul 27 05:00:28 PM PDT 24
Peak memory 197976 kb
Host smart-c1c9207c-91b0-42a6-b48d-9c06f5ffa81d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258783709 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3258783709
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4091652854
Short name T827
Test name
Test status
Simulation time 10401653 ps
CPU time 0.57 seconds
Started Jul 27 04:59:23 PM PDT 24
Finished Jul 27 04:59:24 PM PDT 24
Peak memory 195572 kb
Host smart-f4d62378-52d0-4049-b624-b09766c05083
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091652854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4091652854
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2347563736
Short name T721
Test name
Test status
Simulation time 45479166 ps
CPU time 0.63 seconds
Started Jul 27 05:00:08 PM PDT 24
Finished Jul 27 05:00:10 PM PDT 24
Peak memory 193032 kb
Host smart-749975ca-e5b7-4a77-ae0c-3121c3b93895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347563736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2347563736
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1216345673
Short name T793
Test name
Test status
Simulation time 230857899 ps
CPU time 0.7 seconds
Started Jul 27 04:59:26 PM PDT 24
Finished Jul 27 04:59:26 PM PDT 24
Peak memory 195508 kb
Host smart-e626a2cf-ef96-4b6a-aa77-9cac841a54d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216345673 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1216345673
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2095268596
Short name T717
Test name
Test status
Simulation time 102402600 ps
CPU time 1.97 seconds
Started Jul 27 05:00:30 PM PDT 24
Finished Jul 27 05:00:32 PM PDT 24
Peak memory 198116 kb
Host smart-fe19b2d5-d423-4dc3-b53a-feebb9cefdaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095268596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2095268596
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.491498730
Short name T838
Test name
Test status
Simulation time 107390025 ps
CPU time 1.37 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 198352 kb
Host smart-03a5a5f2-e789-436e-8e34-ed885821e1a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491498730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.491498730
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3462583450
Short name T761
Test name
Test status
Simulation time 40922080 ps
CPU time 1.29 seconds
Started Jul 27 04:59:31 PM PDT 24
Finished Jul 27 04:59:33 PM PDT 24
Peak memory 198384 kb
Host smart-789d2900-8dba-4d6d-97fa-14e03108d089
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462583450 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3462583450
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2141785073
Short name T835
Test name
Test status
Simulation time 14949592 ps
CPU time 0.59 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 194476 kb
Host smart-0a542f77-fe80-4cec-ab22-e7be0151b050
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141785073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2141785073
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1958471059
Short name T830
Test name
Test status
Simulation time 44582756 ps
CPU time 0.59 seconds
Started Jul 27 04:59:39 PM PDT 24
Finished Jul 27 04:59:40 PM PDT 24
Peak memory 193992 kb
Host smart-6d175864-3d5e-4246-8597-d8ff76abf74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958471059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1958471059
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4287958565
Short name T96
Test name
Test status
Simulation time 72751836 ps
CPU time 0.87 seconds
Started Jul 27 04:59:49 PM PDT 24
Finished Jul 27 04:59:50 PM PDT 24
Peak memory 196436 kb
Host smart-12946a3b-9752-40f1-b817-314b034d0c9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287958565 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.4287958565
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1759767376
Short name T750
Test name
Test status
Simulation time 132118708 ps
CPU time 2.04 seconds
Started Jul 27 04:59:33 PM PDT 24
Finished Jul 27 04:59:35 PM PDT 24
Peak memory 198408 kb
Host smart-f420215e-4cd4-41d9-b9fe-83de42eb2905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759767376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1759767376
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.460935726
Short name T805
Test name
Test status
Simulation time 346508807 ps
CPU time 0.86 seconds
Started Jul 27 04:59:34 PM PDT 24
Finished Jul 27 04:59:35 PM PDT 24
Peak memory 197404 kb
Host smart-91e8bee8-af6e-42ab-aab7-955bcaa8c47d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460935726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.460935726
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3370795190
Short name T790
Test name
Test status
Simulation time 44239723 ps
CPU time 0.79 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 198120 kb
Host smart-52994e6f-ff6a-4d8b-adc0-b37db6621e73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370795190 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3370795190
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.119169469
Short name T727
Test name
Test status
Simulation time 27632136 ps
CPU time 0.59 seconds
Started Jul 27 04:59:27 PM PDT 24
Finished Jul 27 04:59:33 PM PDT 24
Peak memory 194748 kb
Host smart-d5bedda8-ef49-45a1-b9ef-fca4bdcb754e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119169469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.119169469
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2609757424
Short name T786
Test name
Test status
Simulation time 62972679 ps
CPU time 0.73 seconds
Started Jul 27 04:59:20 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 197232 kb
Host smart-b1bed626-ff32-4b39-b42e-11e63b6d23db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609757424 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2609757424
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3647686892
Short name T711
Test name
Test status
Simulation time 247470593 ps
CPU time 1.42 seconds
Started Jul 27 04:59:34 PM PDT 24
Finished Jul 27 04:59:35 PM PDT 24
Peak memory 198316 kb
Host smart-84b3452c-06b6-4d61-a6c9-053dec82660e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647686892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3647686892
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3983393042
Short name T39
Test name
Test status
Simulation time 92820904 ps
CPU time 1.13 seconds
Started Jul 27 04:59:27 PM PDT 24
Finished Jul 27 04:59:29 PM PDT 24
Peak memory 198332 kb
Host smart-cc300c0b-02be-4dd2-8344-4b82813646f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983393042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3983393042
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2629809785
Short name T78
Test name
Test status
Simulation time 17763623 ps
CPU time 0.8 seconds
Started Jul 27 04:59:12 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 196880 kb
Host smart-c2063408-e8b2-4225-87de-49c7a8eb3cad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629809785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2629809785
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2391217317
Short name T765
Test name
Test status
Simulation time 387330826 ps
CPU time 3.48 seconds
Started Jul 27 04:59:13 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 197552 kb
Host smart-cae66778-54a8-48ce-95a2-9573d5b3e18e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391217317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2391217317
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.960588866
Short name T770
Test name
Test status
Simulation time 13453846 ps
CPU time 0.59 seconds
Started Jul 27 04:59:00 PM PDT 24
Finished Jul 27 04:59:00 PM PDT 24
Peak memory 195696 kb
Host smart-603d73f2-b046-4d2a-9a56-fadf0cd0814a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960588866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.960588866
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2180073416
Short name T718
Test name
Test status
Simulation time 46388575 ps
CPU time 1.01 seconds
Started Jul 27 04:59:12 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 198148 kb
Host smart-ed3d7019-9a43-4c89-a07c-52b61d4de8ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180073416 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2180073416
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2577577453
Short name T90
Test name
Test status
Simulation time 13240242 ps
CPU time 0.62 seconds
Started Jul 27 04:59:06 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 195880 kb
Host smart-ea114180-33b0-42f7-ae06-51c5c3961531
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577577453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2577577453
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1331318148
Short name T772
Test name
Test status
Simulation time 18506761 ps
CPU time 0.61 seconds
Started Jul 27 04:59:13 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 194684 kb
Host smart-f8bb3fac-ea0d-4e2f-80be-18ca30868803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331318148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1331318148
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1808484104
Short name T95
Test name
Test status
Simulation time 20532740 ps
CPU time 0.75 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 196260 kb
Host smart-8caec7cb-a199-41d9-a3eb-5cdc4ee449ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808484104 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1808484104
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.104176222
Short name T731
Test name
Test status
Simulation time 192645161 ps
CPU time 1.15 seconds
Started Jul 27 04:59:06 PM PDT 24
Finished Jul 27 04:59:08 PM PDT 24
Peak memory 198300 kb
Host smart-5c0fc383-e353-469a-95fe-1afe456813d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104176222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.104176222
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3199919375
Short name T824
Test name
Test status
Simulation time 303488514 ps
CPU time 1.1 seconds
Started Jul 27 04:59:17 PM PDT 24
Finished Jul 27 04:59:19 PM PDT 24
Peak memory 198368 kb
Host smart-8eafd8dd-54a6-4615-9538-2aeae788f3a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199919375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3199919375
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2027262823
Short name T733
Test name
Test status
Simulation time 22723597 ps
CPU time 0.54 seconds
Started Jul 27 04:59:34 PM PDT 24
Finished Jul 27 04:59:35 PM PDT 24
Peak memory 194692 kb
Host smart-56c6ff90-3da6-40eb-9d33-df71a0d16792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027262823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2027262823
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2609506753
Short name T739
Test name
Test status
Simulation time 16910637 ps
CPU time 0.6 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 194648 kb
Host smart-90ca328e-726e-4cbb-92b8-089238ebd7c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609506753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2609506753
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3053899038
Short name T771
Test name
Test status
Simulation time 21153681 ps
CPU time 0.57 seconds
Started Jul 27 04:59:23 PM PDT 24
Finished Jul 27 04:59:24 PM PDT 24
Peak memory 193964 kb
Host smart-d7c72ed5-ae19-46a7-90bb-4caaf3105044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053899038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3053899038
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.49256497
Short name T755
Test name
Test status
Simulation time 40818069 ps
CPU time 0.6 seconds
Started Jul 27 04:59:34 PM PDT 24
Finished Jul 27 04:59:40 PM PDT 24
Peak memory 193960 kb
Host smart-6f6f029b-58c4-424d-8e5f-cdbc7a71ea99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49256497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.49256497
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.893028768
Short name T729
Test name
Test status
Simulation time 47183847 ps
CPU time 0.61 seconds
Started Jul 27 04:59:35 PM PDT 24
Finished Jul 27 04:59:36 PM PDT 24
Peak memory 194668 kb
Host smart-7cd48d93-e4fb-4495-ae51-254925645ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893028768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.893028768
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1951173209
Short name T821
Test name
Test status
Simulation time 13181032 ps
CPU time 0.61 seconds
Started Jul 27 04:59:38 PM PDT 24
Finished Jul 27 04:59:39 PM PDT 24
Peak memory 194708 kb
Host smart-cc967c9e-3f78-4484-8284-93c95ad012d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951173209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1951173209
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2063168341
Short name T714
Test name
Test status
Simulation time 23462565 ps
CPU time 0.6 seconds
Started Jul 27 04:59:24 PM PDT 24
Finished Jul 27 04:59:24 PM PDT 24
Peak memory 193988 kb
Host smart-33f90e35-9479-4781-ac6c-586d82f38d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063168341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2063168341
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1210124175
Short name T777
Test name
Test status
Simulation time 35338265 ps
CPU time 0.56 seconds
Started Jul 27 04:59:35 PM PDT 24
Finished Jul 27 04:59:36 PM PDT 24
Peak memory 194616 kb
Host smart-93f7d755-735c-44bb-a781-9634ebed3490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210124175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1210124175
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.28440330
Short name T757
Test name
Test status
Simulation time 17056563 ps
CPU time 0.6 seconds
Started Jul 27 04:59:32 PM PDT 24
Finished Jul 27 04:59:32 PM PDT 24
Peak memory 194112 kb
Host smart-3935a5c7-4af9-422b-8d38-a94890ada9e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.28440330
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3128984833
Short name T713
Test name
Test status
Simulation time 15809056 ps
CPU time 0.6 seconds
Started Jul 27 04:59:50 PM PDT 24
Finished Jul 27 04:59:50 PM PDT 24
Peak memory 194124 kb
Host smart-112b5d47-5481-4817-b4b4-c33e5f691f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128984833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3128984833
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.500718698
Short name T825
Test name
Test status
Simulation time 17422977 ps
CPU time 0.62 seconds
Started Jul 27 04:59:02 PM PDT 24
Finished Jul 27 04:59:03 PM PDT 24
Peak memory 194648 kb
Host smart-57627f25-0a80-40f0-8bb0-2aff98c08659
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500718698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.500718698
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3910496277
Short name T724
Test name
Test status
Simulation time 473489439 ps
CPU time 2.86 seconds
Started Jul 27 04:59:02 PM PDT 24
Finished Jul 27 04:59:05 PM PDT 24
Peak memory 197404 kb
Host smart-c1a9c3d3-cde2-4295-98c6-7485cf293b03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910496277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3910496277
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4023892109
Short name T766
Test name
Test status
Simulation time 58340334 ps
CPU time 0.65 seconds
Started Jul 27 04:59:22 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 195136 kb
Host smart-b236d5bb-2cb0-461a-adba-d6880b88f2ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023892109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4023892109
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.188853912
Short name T728
Test name
Test status
Simulation time 96960832 ps
CPU time 0.81 seconds
Started Jul 27 04:59:14 PM PDT 24
Finished Jul 27 04:59:15 PM PDT 24
Peak memory 192552 kb
Host smart-d6f9672d-f7ff-4a2f-ac80-6e79119323b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188853912 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.188853912
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4098409720
Short name T779
Test name
Test status
Simulation time 14788397 ps
CPU time 0.62 seconds
Started Jul 27 04:59:10 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 195768 kb
Host smart-595438ff-876b-463a-a12f-e2aa1350992b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098409720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.4098409720
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2034567205
Short name T803
Test name
Test status
Simulation time 31703038 ps
CPU time 0.61 seconds
Started Jul 27 04:59:13 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 194140 kb
Host smart-70cdc5b4-ba69-42ec-ba26-7b9a133e3ec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034567205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2034567205
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2806929309
Short name T97
Test name
Test status
Simulation time 48022364 ps
CPU time 0.73 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 196380 kb
Host smart-a7820611-e810-4452-9df3-5c3707e360c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806929309 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2806929309
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2076565207
Short name T740
Test name
Test status
Simulation time 56848087 ps
CPU time 2.93 seconds
Started Jul 27 04:59:11 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 198356 kb
Host smart-951ca95e-846f-45ed-96f0-c6b70cf141a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076565207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2076565207
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1941586794
Short name T773
Test name
Test status
Simulation time 14839667 ps
CPU time 0.58 seconds
Started Jul 27 04:59:35 PM PDT 24
Finished Jul 27 04:59:35 PM PDT 24
Peak memory 193984 kb
Host smart-892210bc-10a1-438c-85aa-7797fc176a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941586794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1941586794
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.236743371
Short name T807
Test name
Test status
Simulation time 13838279 ps
CPU time 0.6 seconds
Started Jul 27 04:59:48 PM PDT 24
Finished Jul 27 04:59:49 PM PDT 24
Peak memory 193968 kb
Host smart-3b6d7916-1b11-4c65-b404-f839a16493fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236743371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.236743371
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.209309305
Short name T767
Test name
Test status
Simulation time 36108871 ps
CPU time 0.59 seconds
Started Jul 27 04:59:34 PM PDT 24
Finished Jul 27 04:59:35 PM PDT 24
Peak memory 194736 kb
Host smart-c2aaa2d0-0361-452b-b817-72e562c6b4c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209309305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.209309305
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3233598347
Short name T748
Test name
Test status
Simulation time 16474808 ps
CPU time 0.59 seconds
Started Jul 27 04:59:26 PM PDT 24
Finished Jul 27 04:59:26 PM PDT 24
Peak memory 194604 kb
Host smart-b3ce2539-a24b-4be1-a681-d1a9ad6576fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233598347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3233598347
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1553060235
Short name T832
Test name
Test status
Simulation time 35741310 ps
CPU time 0.58 seconds
Started Jul 27 04:59:26 PM PDT 24
Finished Jul 27 04:59:27 PM PDT 24
Peak memory 194028 kb
Host smart-678d19ee-8c89-4d40-a19e-cc3c6ace6dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553060235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1553060235
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3022441763
Short name T720
Test name
Test status
Simulation time 26993388 ps
CPU time 0.59 seconds
Started Jul 27 04:59:32 PM PDT 24
Finished Jul 27 04:59:33 PM PDT 24
Peak memory 194112 kb
Host smart-6b67130b-6f1b-471d-9227-ba1c35574d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022441763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3022441763
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.725886543
Short name T764
Test name
Test status
Simulation time 31184867 ps
CPU time 0.58 seconds
Started Jul 27 04:59:54 PM PDT 24
Finished Jul 27 04:59:55 PM PDT 24
Peak memory 194044 kb
Host smart-d8d357e8-3a6a-4264-b748-d60191dcaabc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725886543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.725886543
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3146040660
Short name T781
Test name
Test status
Simulation time 16112085 ps
CPU time 0.6 seconds
Started Jul 27 04:59:31 PM PDT 24
Finished Jul 27 04:59:32 PM PDT 24
Peak memory 194792 kb
Host smart-2937e731-731b-4751-bd1e-4e6dc2b89d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146040660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3146040660
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.780168135
Short name T730
Test name
Test status
Simulation time 18180885 ps
CPU time 0.6 seconds
Started Jul 27 04:59:29 PM PDT 24
Finished Jul 27 04:59:30 PM PDT 24
Peak memory 194668 kb
Host smart-3da3c1d7-e755-4645-85ab-9bf8eee6aa7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780168135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.780168135
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.726410357
Short name T798
Test name
Test status
Simulation time 28371896 ps
CPU time 0.58 seconds
Started Jul 27 04:59:33 PM PDT 24
Finished Jul 27 04:59:33 PM PDT 24
Peak memory 194800 kb
Host smart-0f0a9ce2-2713-4c03-a997-70d488c49997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726410357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.726410357
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.567197206
Short name T88
Test name
Test status
Simulation time 32415348 ps
CPU time 0.95 seconds
Started Jul 27 04:59:23 PM PDT 24
Finished Jul 27 04:59:25 PM PDT 24
Peak memory 197068 kb
Host smart-7dcc2e26-1952-453c-9120-48f1657480f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567197206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.567197206
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2237412347
Short name T741
Test name
Test status
Simulation time 93914601 ps
CPU time 1.45 seconds
Started Jul 27 04:59:22 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 196728 kb
Host smart-b8ff366a-4b4c-4aec-924b-07307860244e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237412347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2237412347
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.843627306
Short name T831
Test name
Test status
Simulation time 27659017 ps
CPU time 0.61 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 195328 kb
Host smart-5b56e05a-40ba-41f1-a05c-bfa3050f10ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843627306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.843627306
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1147181959
Short name T839
Test name
Test status
Simulation time 20085361 ps
CPU time 0.93 seconds
Started Jul 27 04:58:58 PM PDT 24
Finished Jul 27 04:58:59 PM PDT 24
Peak memory 198140 kb
Host smart-0a5ca3d4-a0b9-47b4-bcdb-0286338fca3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147181959 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1147181959
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2723443101
Short name T742
Test name
Test status
Simulation time 17814624 ps
CPU time 0.59 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 195124 kb
Host smart-f707a249-8f76-4353-a04f-eac3b345c530
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723443101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2723443101
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2444906961
Short name T746
Test name
Test status
Simulation time 15761581 ps
CPU time 0.58 seconds
Started Jul 27 04:59:09 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 194020 kb
Host smart-ef2ffa80-7ecd-4723-b289-30d78c16fe35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444906961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2444906961
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1980287832
Short name T820
Test name
Test status
Simulation time 308561605 ps
CPU time 0.82 seconds
Started Jul 27 04:59:40 PM PDT 24
Finished Jul 27 04:59:41 PM PDT 24
Peak memory 196840 kb
Host smart-f6cf19ae-09f9-4cf7-82f8-b8373bbdf887
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980287832 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1980287832
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2391787065
Short name T719
Test name
Test status
Simulation time 144653843 ps
CPU time 1.49 seconds
Started Jul 27 04:59:21 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 198296 kb
Host smart-eab58e1d-da02-422a-8608-6025ec8916df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391787065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2391787065
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1619648398
Short name T833
Test name
Test status
Simulation time 1529165288 ps
CPU time 1.38 seconds
Started Jul 27 04:59:09 PM PDT 24
Finished Jul 27 04:59:11 PM PDT 24
Peak memory 198400 kb
Host smart-a3175bb4-758f-4538-831d-3875c09eeb3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619648398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1619648398
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1773342197
Short name T715
Test name
Test status
Simulation time 20858908 ps
CPU time 0.59 seconds
Started Jul 27 04:59:33 PM PDT 24
Finished Jul 27 04:59:35 PM PDT 24
Peak memory 194708 kb
Host smart-76da2311-fcb3-4ce3-be67-68ecff631d96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773342197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1773342197
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.200641186
Short name T732
Test name
Test status
Simulation time 52692867 ps
CPU time 0.61 seconds
Started Jul 27 04:59:22 PM PDT 24
Finished Jul 27 04:59:22 PM PDT 24
Peak memory 194096 kb
Host smart-cab11ac0-c2ee-443d-87a8-b17d9a01f39a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200641186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.200641186
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1310428309
Short name T788
Test name
Test status
Simulation time 24207746 ps
CPU time 0.57 seconds
Started Jul 27 04:59:31 PM PDT 24
Finished Jul 27 04:59:32 PM PDT 24
Peak memory 194032 kb
Host smart-9fae5f98-908a-4f26-8f19-a5fead936dce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310428309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1310428309
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4077449004
Short name T769
Test name
Test status
Simulation time 14794267 ps
CPU time 0.57 seconds
Started Jul 27 04:59:57 PM PDT 24
Finished Jul 27 04:59:58 PM PDT 24
Peak memory 194648 kb
Host smart-54766ab2-a254-4946-9b8a-ab4398cdcc1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077449004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4077449004
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1689349565
Short name T801
Test name
Test status
Simulation time 48196354 ps
CPU time 0.57 seconds
Started Jul 27 04:59:26 PM PDT 24
Finished Jul 27 04:59:27 PM PDT 24
Peak memory 194716 kb
Host smart-38badef6-d34a-483d-9d5b-db5c6172f8be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689349565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1689349565
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.262630797
Short name T762
Test name
Test status
Simulation time 15314445 ps
CPU time 0.6 seconds
Started Jul 27 04:59:35 PM PDT 24
Finished Jul 27 04:59:36 PM PDT 24
Peak memory 193988 kb
Host smart-3d49fdf1-2b0c-4def-b0ea-ec43b1cd1374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262630797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.262630797
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2522906202
Short name T795
Test name
Test status
Simulation time 15514140 ps
CPU time 0.64 seconds
Started Jul 27 04:59:30 PM PDT 24
Finished Jul 27 04:59:31 PM PDT 24
Peak memory 194776 kb
Host smart-de84ce29-6d43-451e-81ca-5529a6b234b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522906202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2522906202
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.989025687
Short name T816
Test name
Test status
Simulation time 43549987 ps
CPU time 0.57 seconds
Started Jul 27 04:59:19 PM PDT 24
Finished Jul 27 04:59:19 PM PDT 24
Peak memory 194084 kb
Host smart-e4aa99d0-196b-4cc6-843c-643be242f7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989025687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.989025687
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2032348389
Short name T796
Test name
Test status
Simulation time 37874089 ps
CPU time 0.65 seconds
Started Jul 27 04:59:20 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 194004 kb
Host smart-7b3773f4-aeb0-4511-b6c7-f3764807558d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032348389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2032348389
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.725395591
Short name T826
Test name
Test status
Simulation time 35718480 ps
CPU time 0.59 seconds
Started Jul 27 04:59:21 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 193992 kb
Host smart-0baf421c-422b-4502-ba49-53698ed1bf54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725395591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.725395591
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1467433128
Short name T752
Test name
Test status
Simulation time 132917638 ps
CPU time 1.51 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 198376 kb
Host smart-c6a28706-b298-4c8d-acf2-e600851cd077
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467433128 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1467433128
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3805084624
Short name T81
Test name
Test status
Simulation time 75804260 ps
CPU time 0.56 seconds
Started Jul 27 04:59:21 PM PDT 24
Finished Jul 27 04:59:22 PM PDT 24
Peak memory 194152 kb
Host smart-71bee582-955a-499f-aeed-0f2ffd78c77c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805084624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3805084624
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.4083894331
Short name T774
Test name
Test status
Simulation time 23549922 ps
CPU time 0.58 seconds
Started Jul 27 04:59:03 PM PDT 24
Finished Jul 27 04:59:04 PM PDT 24
Peak memory 194008 kb
Host smart-f7d06556-303e-48dd-8c6d-b09c82ac9407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083894331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.4083894331
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.863313494
Short name T823
Test name
Test status
Simulation time 39285303 ps
CPU time 0.82 seconds
Started Jul 27 04:59:22 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 197160 kb
Host smart-be37a42d-81ce-4839-87c3-f81af3e46160
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863313494 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.863313494
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2102883779
Short name T756
Test name
Test status
Simulation time 182538493 ps
CPU time 1.74 seconds
Started Jul 27 04:59:03 PM PDT 24
Finished Jul 27 04:59:05 PM PDT 24
Peak memory 198332 kb
Host smart-970ce1f8-a50d-46e5-9d95-ed5c3680559a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102883779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2102883779
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2465248708
Short name T40
Test name
Test status
Simulation time 84943181 ps
CPU time 0.87 seconds
Started Jul 27 04:59:13 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 197264 kb
Host smart-88520d91-6594-43fa-b535-95875fc2a550
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465248708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2465248708
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3389567691
Short name T760
Test name
Test status
Simulation time 103964268 ps
CPU time 0.88 seconds
Started Jul 27 04:59:13 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 198224 kb
Host smart-53511330-c66b-4857-b8c6-06e6259bff1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389567691 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3389567691
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.4134407447
Short name T749
Test name
Test status
Simulation time 24532374 ps
CPU time 0.61 seconds
Started Jul 27 04:59:21 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 195556 kb
Host smart-12737ae3-55fb-42f5-9bab-65daee740a7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134407447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.4134407447
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2355106433
Short name T780
Test name
Test status
Simulation time 15558971 ps
CPU time 0.6 seconds
Started Jul 27 04:59:09 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 194064 kb
Host smart-9a1a777a-7bbd-4115-adf2-8f96760287e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355106433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2355106433
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1001433071
Short name T99
Test name
Test status
Simulation time 100014988 ps
CPU time 0.76 seconds
Started Jul 27 04:59:23 PM PDT 24
Finished Jul 27 04:59:24 PM PDT 24
Peak memory 196296 kb
Host smart-2e0fccf6-4977-4893-8d6d-b214d44c6a3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001433071 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1001433071
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2685537734
Short name T829
Test name
Test status
Simulation time 116085239 ps
CPU time 1.04 seconds
Started Jul 27 04:59:36 PM PDT 24
Finished Jul 27 04:59:37 PM PDT 24
Peak memory 198164 kb
Host smart-f747ec54-e726-44d4-8443-2d7395cf9576
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685537734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2685537734
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3959515855
Short name T37
Test name
Test status
Simulation time 124461396 ps
CPU time 1.44 seconds
Started Jul 27 04:58:59 PM PDT 24
Finished Jul 27 04:59:01 PM PDT 24
Peak memory 198364 kb
Host smart-aa6a7f3e-d4cb-4738-a908-42ced9eff994
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959515855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3959515855
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1137123709
Short name T754
Test name
Test status
Simulation time 92807566 ps
CPU time 1.18 seconds
Started Jul 27 04:59:30 PM PDT 24
Finished Jul 27 04:59:31 PM PDT 24
Peak memory 198372 kb
Host smart-914a2d52-d9db-4b39-9e85-df479499b525
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137123709 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1137123709
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2743156882
Short name T763
Test name
Test status
Simulation time 41680960 ps
CPU time 0.58 seconds
Started Jul 27 04:59:22 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 195012 kb
Host smart-c1d5fb70-3719-48f7-851d-a158ec2c38b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743156882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2743156882
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3858052713
Short name T736
Test name
Test status
Simulation time 18185677 ps
CPU time 0.64 seconds
Started Jul 27 04:59:22 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 194068 kb
Host smart-8e76641e-fe53-40e4-a907-e50a0d8db8c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858052713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3858052713
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1164668253
Short name T84
Test name
Test status
Simulation time 137045789 ps
CPU time 0.84 seconds
Started Jul 27 04:59:12 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 196688 kb
Host smart-2b829b90-0aab-42a1-87ac-88b310e341e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164668253 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1164668253
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3554984984
Short name T723
Test name
Test status
Simulation time 287078192 ps
CPU time 2.63 seconds
Started Jul 27 04:59:29 PM PDT 24
Finished Jul 27 04:59:37 PM PDT 24
Peak memory 198288 kb
Host smart-957805de-5032-404a-9e14-d52d93a99a99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554984984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3554984984
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.714005904
Short name T41
Test name
Test status
Simulation time 201188910 ps
CPU time 1.42 seconds
Started Jul 27 04:59:17 PM PDT 24
Finished Jul 27 04:59:19 PM PDT 24
Peak memory 198292 kb
Host smart-1f1aa552-e58f-4aa2-a7bc-6c9487f6150f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714005904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.714005904
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1330326617
Short name T785
Test name
Test status
Simulation time 18566517 ps
CPU time 0.85 seconds
Started Jul 27 04:59:27 PM PDT 24
Finished Jul 27 04:59:28 PM PDT 24
Peak memory 198172 kb
Host smart-730a431a-6cee-4a03-87cc-b2ac3509378b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330326617 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1330326617
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2861431084
Short name T83
Test name
Test status
Simulation time 41722206 ps
CPU time 0.6 seconds
Started Jul 27 04:59:33 PM PDT 24
Finished Jul 27 04:59:34 PM PDT 24
Peak memory 195308 kb
Host smart-183f3669-0374-4b9b-a4d7-51e5bf143732
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861431084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2861431084
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3548359145
Short name T813
Test name
Test status
Simulation time 12676634 ps
CPU time 0.6 seconds
Started Jul 27 04:59:25 PM PDT 24
Finished Jul 27 04:59:26 PM PDT 24
Peak memory 194600 kb
Host smart-5172c2bd-9567-4247-96f3-f982c732be59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548359145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3548359145
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3475050302
Short name T80
Test name
Test status
Simulation time 19692423 ps
CPU time 0.64 seconds
Started Jul 27 04:59:42 PM PDT 24
Finished Jul 27 04:59:42 PM PDT 24
Peak memory 195032 kb
Host smart-d402ac41-38da-460b-9837-ec739062195e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475050302 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3475050302
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2083023083
Short name T811
Test name
Test status
Simulation time 160482803 ps
CPU time 1.74 seconds
Started Jul 27 04:59:11 PM PDT 24
Finished Jul 27 04:59:12 PM PDT 24
Peak memory 198392 kb
Host smart-cf0c13eb-161b-4178-93df-3de245095a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083023083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2083023083
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2246924951
Short name T43
Test name
Test status
Simulation time 238325765 ps
CPU time 1.12 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 198368 kb
Host smart-c8fc3190-e47b-4f37-8b28-5ab57e8e5cf5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246924951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2246924951
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1758616230
Short name T758
Test name
Test status
Simulation time 24697597 ps
CPU time 1.22 seconds
Started Jul 27 04:59:21 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 198356 kb
Host smart-2fb786ef-c3f3-42f0-b081-d2e5c2a38b6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758616230 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1758616230
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.680206862
Short name T744
Test name
Test status
Simulation time 22994859 ps
CPU time 0.61 seconds
Started Jul 27 04:59:27 PM PDT 24
Finished Jul 27 04:59:27 PM PDT 24
Peak memory 195596 kb
Host smart-cd677779-6d1f-4531-b586-342a34c211c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680206862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.680206862
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.489731145
Short name T737
Test name
Test status
Simulation time 47968998 ps
CPU time 0.61 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 194068 kb
Host smart-37f7e51b-72e1-4b80-a11a-80e712bb39db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489731145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.489731145
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1923837371
Short name T784
Test name
Test status
Simulation time 16777170 ps
CPU time 0.7 seconds
Started Jul 27 04:59:24 PM PDT 24
Finished Jul 27 04:59:25 PM PDT 24
Peak memory 195188 kb
Host smart-93c52153-8da6-4fad-8ede-7c62740ad5ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923837371 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1923837371
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.835139152
Short name T735
Test name
Test status
Simulation time 67543803 ps
CPU time 1.97 seconds
Started Jul 27 04:59:37 PM PDT 24
Finished Jul 27 04:59:39 PM PDT 24
Peak memory 198352 kb
Host smart-e511ebbc-8a4f-4eea-887d-bcccd8812679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835139152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.835139152
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2766528979
Short name T30
Test name
Test status
Simulation time 296555264 ps
CPU time 1.08 seconds
Started Jul 27 05:00:28 PM PDT 24
Finished Jul 27 05:00:29 PM PDT 24
Peak memory 197792 kb
Host smart-6528b1f9-82b4-426c-b692-d9304fe5999b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766528979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2766528979
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1124121338
Short name T249
Test name
Test status
Simulation time 14568321 ps
CPU time 0.58 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:05 PM PDT 24
Peak memory 194392 kb
Host smart-fac07521-eda5-4ad2-a9e8-188505cc7470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124121338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1124121338
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3395846303
Short name T212
Test name
Test status
Simulation time 48171836 ps
CPU time 0.71 seconds
Started Jul 27 05:51:57 PM PDT 24
Finished Jul 27 05:51:58 PM PDT 24
Peak memory 196336 kb
Host smart-d3e6438c-942d-4333-8c06-86a75b104811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395846303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3395846303
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1932156543
Short name T695
Test name
Test status
Simulation time 454221208 ps
CPU time 15.26 seconds
Started Jul 27 05:52:06 PM PDT 24
Finished Jul 27 05:52:21 PM PDT 24
Peak memory 197404 kb
Host smart-9f211432-4665-4ff4-8dd2-d72f29197493
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932156543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1932156543
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1782267498
Short name T139
Test name
Test status
Simulation time 60533721 ps
CPU time 0.78 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:06 PM PDT 24
Peak memory 196460 kb
Host smart-196667cc-a9dd-4861-bafe-fc4bab489415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782267498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1782267498
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.187493968
Short name T203
Test name
Test status
Simulation time 44489740 ps
CPU time 0.68 seconds
Started Jul 27 05:51:58 PM PDT 24
Finished Jul 27 05:51:58 PM PDT 24
Peak memory 194836 kb
Host smart-47994798-1a20-43a2-a7c5-2e9e002a6ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187493968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.187493968
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.454492985
Short name T13
Test name
Test status
Simulation time 201913578 ps
CPU time 2.05 seconds
Started Jul 27 05:52:03 PM PDT 24
Finished Jul 27 05:52:05 PM PDT 24
Peak memory 198496 kb
Host smart-736bd84a-1227-4fa3-9173-b36e5d83042d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454492985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.454492985
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.93270197
Short name T385
Test name
Test status
Simulation time 133627973 ps
CPU time 2.32 seconds
Started Jul 27 05:52:06 PM PDT 24
Finished Jul 27 05:52:09 PM PDT 24
Peak memory 198540 kb
Host smart-48af29d2-edd9-4888-95df-7726760c4e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93270197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.93270197
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1882229149
Short name T213
Test name
Test status
Simulation time 139873459 ps
CPU time 1.34 seconds
Started Jul 27 05:51:58 PM PDT 24
Finished Jul 27 05:51:59 PM PDT 24
Peak memory 196344 kb
Host smart-b7a5a282-2c41-4419-b6c0-acb971a8582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882229149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1882229149
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.683729017
Short name T343
Test name
Test status
Simulation time 109726969 ps
CPU time 1.17 seconds
Started Jul 27 05:51:58 PM PDT 24
Finished Jul 27 05:52:00 PM PDT 24
Peak memory 196516 kb
Host smart-f4446331-d548-43fe-abe2-b717112bf3e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683729017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.683729017
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1245111080
Short name T537
Test name
Test status
Simulation time 798858714 ps
CPU time 6.37 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:12 PM PDT 24
Peak memory 198432 kb
Host smart-cbd3e858-0618-4e48-8e65-998f571e10b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245111080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1245111080
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3252702170
Short name T33
Test name
Test status
Simulation time 45525169 ps
CPU time 0.79 seconds
Started Jul 27 05:52:06 PM PDT 24
Finished Jul 27 05:52:07 PM PDT 24
Peak memory 214448 kb
Host smart-8d8079db-5ae3-4142-95d1-dea0928f86df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252702170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3252702170
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1785674990
Short name T240
Test name
Test status
Simulation time 364068646 ps
CPU time 1.57 seconds
Started Jul 27 05:51:58 PM PDT 24
Finished Jul 27 05:52:00 PM PDT 24
Peak memory 196088 kb
Host smart-4e07a710-9ae4-437d-8643-d3f6dab844c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785674990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1785674990
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1804104016
Short name T462
Test name
Test status
Simulation time 180293279 ps
CPU time 1.21 seconds
Started Jul 27 05:51:57 PM PDT 24
Finished Jul 27 05:51:59 PM PDT 24
Peak memory 196072 kb
Host smart-a1141fbc-4529-4b2e-a3c3-9d8ce5a9e1f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804104016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1804104016
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.692502379
Short name T271
Test name
Test status
Simulation time 3000731705 ps
CPU time 69.16 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 198624 kb
Host smart-e5c1b0a0-dd12-4830-9a21-72ed1ffd1031
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692502379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.692502379
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1237562438
Short name T504
Test name
Test status
Simulation time 11053320 ps
CPU time 0.58 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:06 PM PDT 24
Peak memory 195480 kb
Host smart-a9780973-7c9d-4c47-873c-9b8be28a2ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237562438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1237562438
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2988614723
Short name T334
Test name
Test status
Simulation time 101454777 ps
CPU time 0.79 seconds
Started Jul 27 05:52:06 PM PDT 24
Finished Jul 27 05:52:07 PM PDT 24
Peak memory 196356 kb
Host smart-9e7c79c3-dbe5-4f07-ad0f-833c542d7314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988614723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2988614723
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.793717716
Short name T175
Test name
Test status
Simulation time 363564832 ps
CPU time 10.21 seconds
Started Jul 27 05:52:06 PM PDT 24
Finished Jul 27 05:52:17 PM PDT 24
Peak memory 196944 kb
Host smart-7a0eaa22-ee96-455e-ab86-7585679ebf81
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793717716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.793717716
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3369373122
Short name T491
Test name
Test status
Simulation time 223513279 ps
CPU time 0.82 seconds
Started Jul 27 05:52:07 PM PDT 24
Finished Jul 27 05:52:08 PM PDT 24
Peak memory 196972 kb
Host smart-60e383eb-1879-40d0-a51d-6dcaa5367baf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369373122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3369373122
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.940907068
Short name T223
Test name
Test status
Simulation time 84620624 ps
CPU time 0.71 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:06 PM PDT 24
Peak memory 195596 kb
Host smart-900e10e3-0c32-43d7-acd1-cb10384b4418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940907068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.940907068
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2009041764
Short name T554
Test name
Test status
Simulation time 170119730 ps
CPU time 3.31 seconds
Started Jul 27 05:52:04 PM PDT 24
Finished Jul 27 05:52:08 PM PDT 24
Peak memory 198668 kb
Host smart-f1877f95-25c2-4bf3-99a5-cd2beae42508
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009041764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2009041764
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.736111310
Short name T583
Test name
Test status
Simulation time 295104341 ps
CPU time 1.95 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:07 PM PDT 24
Peak memory 196472 kb
Host smart-0d3f0208-da8a-40df-b4cb-804950bc77e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736111310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.736111310
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2193007740
Short name T140
Test name
Test status
Simulation time 68676275 ps
CPU time 1.33 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:07 PM PDT 24
Peak memory 198604 kb
Host smart-497fc393-e8e5-4fa9-bd27-c6d7e74729e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193007740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2193007740
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2156938977
Short name T101
Test name
Test status
Simulation time 75636624 ps
CPU time 1.29 seconds
Started Jul 27 05:52:04 PM PDT 24
Finished Jul 27 05:52:05 PM PDT 24
Peak memory 197632 kb
Host smart-803b71b7-e3a5-40b6-be65-1b3e31f49452
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156938977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2156938977
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3027638509
Short name T476
Test name
Test status
Simulation time 476663969 ps
CPU time 4 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:09 PM PDT 24
Peak memory 198492 kb
Host smart-da36323c-2fed-447a-bbb0-bf9f077f5f6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027638509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3027638509
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.970845721
Short name T45
Test name
Test status
Simulation time 60488903 ps
CPU time 0.85 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:06 PM PDT 24
Peak memory 214420 kb
Host smart-91f4d151-6561-4962-b371-a207ca86ccd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970845721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.970845721
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.957290399
Short name T697
Test name
Test status
Simulation time 128692721 ps
CPU time 1.32 seconds
Started Jul 27 05:52:03 PM PDT 24
Finished Jul 27 05:52:05 PM PDT 24
Peak memory 198560 kb
Host smart-24dda6d1-247d-4e2e-8fe3-ef6b11acb862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957290399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.957290399
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1623331192
Short name T657
Test name
Test status
Simulation time 344411292 ps
CPU time 1.42 seconds
Started Jul 27 05:52:03 PM PDT 24
Finished Jul 27 05:52:04 PM PDT 24
Peak memory 196288 kb
Host smart-0b8ffe2f-ec55-4a2f-b56a-9efdd3e47a86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623331192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1623331192
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.659694172
Short name T102
Test name
Test status
Simulation time 74932649571 ps
CPU time 223.05 seconds
Started Jul 27 05:52:07 PM PDT 24
Finished Jul 27 05:55:51 PM PDT 24
Peak memory 198660 kb
Host smart-45ccee33-c7cf-4fb4-8f36-1c8935a94c0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659694172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.659694172
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1737546505
Short name T209
Test name
Test status
Simulation time 11858756 ps
CPU time 0.56 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 05:52:46 PM PDT 24
Peak memory 194396 kb
Host smart-0a45f25c-b967-4487-85ca-b278065711ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737546505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1737546505
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2909732712
Short name T494
Test name
Test status
Simulation time 36599822 ps
CPU time 0.76 seconds
Started Jul 27 05:52:38 PM PDT 24
Finished Jul 27 05:52:39 PM PDT 24
Peak memory 195724 kb
Host smart-754c8023-6abf-4513-865f-8427d36454e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909732712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2909732712
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1645686453
Short name T317
Test name
Test status
Simulation time 1285436866 ps
CPU time 11.99 seconds
Started Jul 27 05:52:44 PM PDT 24
Finished Jul 27 05:52:56 PM PDT 24
Peak memory 197212 kb
Host smart-9c95e2cf-c54b-46ad-83f9-70c9e16a786e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645686453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1645686453
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.924060313
Short name T22
Test name
Test status
Simulation time 62531161 ps
CPU time 0.92 seconds
Started Jul 27 05:52:49 PM PDT 24
Finished Jul 27 05:52:50 PM PDT 24
Peak memory 197632 kb
Host smart-a173581a-d33c-429d-83ab-d9ab4552d66a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924060313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.924060313
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3568523747
Short name T402
Test name
Test status
Simulation time 206799520 ps
CPU time 0.95 seconds
Started Jul 27 05:52:38 PM PDT 24
Finished Jul 27 05:52:39 PM PDT 24
Peak memory 197036 kb
Host smart-4bb1ac83-e30f-4263-8b7b-fd0b8c117aad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568523747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3568523747
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3424262959
Short name T660
Test name
Test status
Simulation time 94484327 ps
CPU time 3.68 seconds
Started Jul 27 05:52:48 PM PDT 24
Finished Jul 27 05:52:51 PM PDT 24
Peak memory 198572 kb
Host smart-9ec35361-a92b-4840-bf18-0b9994b8a757
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424262959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3424262959
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1800295230
Short name T128
Test name
Test status
Simulation time 81966280 ps
CPU time 2.13 seconds
Started Jul 27 05:52:39 PM PDT 24
Finished Jul 27 05:52:41 PM PDT 24
Peak memory 197352 kb
Host smart-0b22ad92-5b1f-46ae-b849-6b88ab7c9a7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800295230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1800295230
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2963142581
Short name T312
Test name
Test status
Simulation time 52810820 ps
CPU time 1.08 seconds
Started Jul 27 05:52:39 PM PDT 24
Finished Jul 27 05:52:40 PM PDT 24
Peak memory 196340 kb
Host smart-5c482461-bc9f-4157-9151-82bdc572e72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963142581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2963142581
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.593340143
Short name T184
Test name
Test status
Simulation time 174854636 ps
CPU time 0.78 seconds
Started Jul 27 05:52:41 PM PDT 24
Finished Jul 27 05:52:41 PM PDT 24
Peak memory 196016 kb
Host smart-834c94c6-5576-4c68-b662-8517571a73ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593340143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.593340143
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1627568242
Short name T593
Test name
Test status
Simulation time 355267982 ps
CPU time 4.47 seconds
Started Jul 27 05:52:47 PM PDT 24
Finished Jul 27 05:52:52 PM PDT 24
Peak memory 198488 kb
Host smart-de8f6d49-2c6a-4d37-ae5d-1a392e1d2d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627568242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1627568242
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1812422519
Short name T395
Test name
Test status
Simulation time 98885908 ps
CPU time 1.45 seconds
Started Jul 27 05:52:41 PM PDT 24
Finished Jul 27 05:52:42 PM PDT 24
Peak memory 197340 kb
Host smart-6d9975cc-8cac-4a29-bf03-544e4168809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812422519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1812422519
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.364193327
Short name T152
Test name
Test status
Simulation time 141912877 ps
CPU time 1.07 seconds
Started Jul 27 05:52:41 PM PDT 24
Finished Jul 27 05:52:42 PM PDT 24
Peak memory 196316 kb
Host smart-bafda4f7-faf6-40ba-ad2f-42fcdefc3e0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364193327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.364193327
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.206740320
Short name T14
Test name
Test status
Simulation time 12977976845 ps
CPU time 178.33 seconds
Started Jul 27 05:52:45 PM PDT 24
Finished Jul 27 05:55:44 PM PDT 24
Peak memory 198632 kb
Host smart-0ef0c52e-2399-4e96-b577-1814e3042f05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206740320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.206740320
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3846045940
Short name T457
Test name
Test status
Simulation time 11282500 ps
CPU time 0.57 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 05:52:47 PM PDT 24
Peak memory 194388 kb
Host smart-20b5c3a5-d9cb-42c6-8121-6017c73dd274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846045940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3846045940
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.4291250536
Short name T464
Test name
Test status
Simulation time 33628771 ps
CPU time 0.79 seconds
Started Jul 27 05:52:45 PM PDT 24
Finished Jul 27 05:52:46 PM PDT 24
Peak memory 195628 kb
Host smart-b3b3bc3d-c686-417c-ad17-1466fdb9e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291250536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.4291250536
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.4037680965
Short name T390
Test name
Test status
Simulation time 604215719 ps
CPU time 8.13 seconds
Started Jul 27 05:52:50 PM PDT 24
Finished Jul 27 05:52:58 PM PDT 24
Peak memory 197408 kb
Host smart-e32cdad4-0efb-4311-9e08-2e8351da089e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037680965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.4037680965
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.132637998
Short name T69
Test name
Test status
Simulation time 93506394 ps
CPU time 0.62 seconds
Started Jul 27 05:52:49 PM PDT 24
Finished Jul 27 05:52:49 PM PDT 24
Peak memory 194896 kb
Host smart-e0168816-dbfb-4bb9-aa26-d9854b3b61e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132637998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.132637998
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3237333170
Short name T119
Test name
Test status
Simulation time 33244049 ps
CPU time 0.83 seconds
Started Jul 27 05:52:42 PM PDT 24
Finished Jul 27 05:52:43 PM PDT 24
Peak memory 196700 kb
Host smart-fc6b2857-b504-43b6-8bcd-9869bbdb8793
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237333170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3237333170
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.82818421
Short name T239
Test name
Test status
Simulation time 128312694 ps
CPU time 2.6 seconds
Started Jul 27 05:52:45 PM PDT 24
Finished Jul 27 05:52:48 PM PDT 24
Peak memory 198508 kb
Host smart-e1be985f-9867-43d5-85eb-39bb12cc9cff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82818421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.gpio_intr_with_filter_rand_intr_event.82818421
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.490913718
Short name T690
Test name
Test status
Simulation time 2211745849 ps
CPU time 2.64 seconds
Started Jul 27 05:52:44 PM PDT 24
Finished Jul 27 05:52:47 PM PDT 24
Peak memory 197756 kb
Host smart-af7a813e-2fd2-4df1-a42f-d000a7ba14bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490913718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
490913718
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3026380363
Short name T532
Test name
Test status
Simulation time 164659740 ps
CPU time 0.97 seconds
Started Jul 27 05:52:44 PM PDT 24
Finished Jul 27 05:52:45 PM PDT 24
Peak memory 197108 kb
Host smart-34df9c7a-2365-4de1-a931-ca81ecd0c0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026380363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3026380363
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3053608386
Short name T673
Test name
Test status
Simulation time 24518596 ps
CPU time 0.7 seconds
Started Jul 27 05:52:44 PM PDT 24
Finished Jul 27 05:52:45 PM PDT 24
Peak memory 196580 kb
Host smart-37c95040-18a4-4a1a-8f3b-ecf995e7ffcd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053608386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3053608386
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.991895239
Short name T310
Test name
Test status
Simulation time 652529648 ps
CPU time 3.94 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 05:52:51 PM PDT 24
Peak memory 198472 kb
Host smart-87d0055e-6f37-48ff-a281-947ff882cb33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991895239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.991895239
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.191745298
Short name T528
Test name
Test status
Simulation time 79661259 ps
CPU time 0.93 seconds
Started Jul 27 05:52:47 PM PDT 24
Finished Jul 27 05:52:48 PM PDT 24
Peak memory 196948 kb
Host smart-436e3d92-f134-4d88-b711-922435a9ef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191745298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.191745298
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.253506229
Short name T666
Test name
Test status
Simulation time 126091886 ps
CPU time 0.83 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 05:52:47 PM PDT 24
Peak memory 196528 kb
Host smart-61679bba-bed2-4aae-98e8-4df7491a7b79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253506229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.253506229
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3993321319
Short name T647
Test name
Test status
Simulation time 9359038457 ps
CPU time 105 seconds
Started Jul 27 05:52:49 PM PDT 24
Finished Jul 27 05:54:34 PM PDT 24
Peak memory 198608 kb
Host smart-c7ef58cb-db76-41cb-a35a-c8b36c237ce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993321319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3993321319
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.2180969803
Short name T108
Test name
Test status
Simulation time 62184941431 ps
CPU time 1559.24 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 06:18:45 PM PDT 24
Peak memory 198760 kb
Host smart-b974baaf-9337-4aee-85e0-ed6bdf8638ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2180969803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.2180969803
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.589834182
Short name T683
Test name
Test status
Simulation time 58135781 ps
CPU time 0.62 seconds
Started Jul 27 05:52:44 PM PDT 24
Finished Jul 27 05:52:45 PM PDT 24
Peak memory 194428 kb
Host smart-f11bc188-c63a-491c-8e9e-038b25c84a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589834182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.589834182
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1268895262
Short name T552
Test name
Test status
Simulation time 439364625 ps
CPU time 24.71 seconds
Started Jul 27 05:52:51 PM PDT 24
Finished Jul 27 05:53:16 PM PDT 24
Peak memory 197488 kb
Host smart-802d9cb5-85f2-4e5b-b4f8-e3b01cc14a25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268895262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1268895262
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2176663679
Short name T503
Test name
Test status
Simulation time 352568258 ps
CPU time 0.85 seconds
Started Jul 27 05:52:44 PM PDT 24
Finished Jul 27 05:52:45 PM PDT 24
Peak memory 197164 kb
Host smart-60847eb1-98b2-4e92-8718-6942c0133d11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176663679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2176663679
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3380644315
Short name T678
Test name
Test status
Simulation time 77460697 ps
CPU time 1.2 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 05:52:47 PM PDT 24
Peak memory 196596 kb
Host smart-dc9f20d4-4f31-41eb-8a5d-4bdf3abc1945
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380644315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3380644315
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.328690771
Short name T404
Test name
Test status
Simulation time 88352427 ps
CPU time 3.81 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 05:52:50 PM PDT 24
Peak memory 198540 kb
Host smart-64527e3d-9700-4b38-af7c-33053aad4e0d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328690771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.328690771
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.872819644
Short name T430
Test name
Test status
Simulation time 151225440 ps
CPU time 2.71 seconds
Started Jul 27 05:52:49 PM PDT 24
Finished Jul 27 05:52:52 PM PDT 24
Peak memory 197720 kb
Host smart-f0ddc438-407f-4820-bc27-426a40ac76e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872819644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
872819644
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2518913765
Short name T321
Test name
Test status
Simulation time 27499301 ps
CPU time 1.05 seconds
Started Jul 27 05:52:45 PM PDT 24
Finished Jul 27 05:52:47 PM PDT 24
Peak memory 197204 kb
Host smart-317b0b1e-e01d-48cb-b4f1-e2d28e176921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518913765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2518913765
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3448703227
Short name T31
Test name
Test status
Simulation time 16221148 ps
CPU time 0.67 seconds
Started Jul 27 05:52:48 PM PDT 24
Finished Jul 27 05:52:48 PM PDT 24
Peak memory 195516 kb
Host smart-1a0c5b32-ec69-4c8f-a0d2-84a50c0c828c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448703227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3448703227
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.160014018
Short name T278
Test name
Test status
Simulation time 3148829340 ps
CPU time 5.38 seconds
Started Jul 27 05:52:47 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 198568 kb
Host smart-25c26ff6-d59f-4af0-a312-6445bf938974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160014018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.160014018
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2553669282
Short name T612
Test name
Test status
Simulation time 365574307 ps
CPU time 1.13 seconds
Started Jul 27 05:52:45 PM PDT 24
Finished Jul 27 05:52:46 PM PDT 24
Peak memory 196072 kb
Host smart-afcb92f8-8e44-4d6b-95a3-0e17e78882a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553669282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2553669282
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1800193339
Short name T256
Test name
Test status
Simulation time 32843615 ps
CPU time 0.96 seconds
Started Jul 27 05:52:47 PM PDT 24
Finished Jul 27 05:52:48 PM PDT 24
Peak memory 196892 kb
Host smart-d128cc25-b8d1-4691-9b28-cd77f7acb64f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800193339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1800193339
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3011257096
Short name T548
Test name
Test status
Simulation time 8125738300 ps
CPU time 106.24 seconds
Started Jul 27 05:52:49 PM PDT 24
Finished Jul 27 05:54:35 PM PDT 24
Peak memory 198596 kb
Host smart-c7584d33-ed52-4c64-815e-e7435d2445b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011257096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3011257096
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.370200003
Short name T55
Test name
Test status
Simulation time 113854648257 ps
CPU time 490.52 seconds
Started Jul 27 05:52:47 PM PDT 24
Finished Jul 27 06:00:58 PM PDT 24
Peak memory 198776 kb
Host smart-5360c8d6-622d-470a-8c2c-7afa1a5d575c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=370200003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.370200003
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.475394162
Short name T291
Test name
Test status
Simulation time 13245353 ps
CPU time 0.56 seconds
Started Jul 27 05:52:50 PM PDT 24
Finished Jul 27 05:52:51 PM PDT 24
Peak memory 195096 kb
Host smart-9888cb7d-724c-4a58-98bc-2c551651a56a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475394162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.475394162
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.539454539
Short name T486
Test name
Test status
Simulation time 86667445 ps
CPU time 0.81 seconds
Started Jul 27 05:52:48 PM PDT 24
Finished Jul 27 05:52:49 PM PDT 24
Peak memory 195708 kb
Host smart-359b2f64-427b-4fbb-96c2-635c7918f9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539454539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.539454539
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.854226122
Short name T170
Test name
Test status
Simulation time 298543817 ps
CPU time 10.83 seconds
Started Jul 27 05:52:45 PM PDT 24
Finished Jul 27 05:52:56 PM PDT 24
Peak memory 198472 kb
Host smart-a70b0193-c957-47b5-b83f-aba5873fbabc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854226122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.854226122
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1874616949
Short name T154
Test name
Test status
Simulation time 90364592 ps
CPU time 0.9 seconds
Started Jul 27 05:52:53 PM PDT 24
Finished Jul 27 05:52:54 PM PDT 24
Peak memory 197680 kb
Host smart-9b41284d-5ca2-4889-ad30-ada3791af061
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874616949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1874616949
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3173619539
Short name T595
Test name
Test status
Simulation time 105158622 ps
CPU time 1.08 seconds
Started Jul 27 05:52:47 PM PDT 24
Finished Jul 27 05:52:48 PM PDT 24
Peak memory 197064 kb
Host smart-da301f10-94ab-4e97-9277-8c5af6212258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173619539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3173619539
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.123201736
Short name T227
Test name
Test status
Simulation time 226431831 ps
CPU time 2.34 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 05:52:48 PM PDT 24
Peak memory 196812 kb
Host smart-fa3952eb-cae5-49f2-b1d2-297460477e65
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123201736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.123201736
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1873902906
Short name T348
Test name
Test status
Simulation time 1639573497 ps
CPU time 3.64 seconds
Started Jul 27 05:52:48 PM PDT 24
Finished Jul 27 05:52:52 PM PDT 24
Peak memory 198516 kb
Host smart-05db9c71-003a-4b6c-aaad-73e6658c9b5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873902906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1873902906
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3513857967
Short name T428
Test name
Test status
Simulation time 130863597 ps
CPU time 0.67 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 05:52:47 PM PDT 24
Peak memory 195544 kb
Host smart-378b48c0-5405-4b66-9562-9f190491aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513857967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3513857967
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1258395646
Short name T496
Test name
Test status
Simulation time 22722283 ps
CPU time 0.75 seconds
Started Jul 27 05:52:51 PM PDT 24
Finished Jul 27 05:52:52 PM PDT 24
Peak memory 195912 kb
Host smart-a9a9e43b-54de-4b7c-a7e6-dc6bf0b5a6cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258395646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1258395646
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.935877549
Short name T431
Test name
Test status
Simulation time 328538408 ps
CPU time 5.25 seconds
Started Jul 27 05:52:53 PM PDT 24
Finished Jul 27 05:52:59 PM PDT 24
Peak memory 198528 kb
Host smart-88012c17-fe00-48a7-98ca-905662e1e322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935877549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.935877549
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3340210535
Short name T237
Test name
Test status
Simulation time 132429542 ps
CPU time 1.25 seconds
Started Jul 27 05:52:46 PM PDT 24
Finished Jul 27 05:52:47 PM PDT 24
Peak memory 196152 kb
Host smart-a6b3d371-c5e4-4f94-b658-0332f99f09a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340210535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3340210535
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2560243345
Short name T125
Test name
Test status
Simulation time 48369724 ps
CPU time 1.38 seconds
Started Jul 27 05:52:48 PM PDT 24
Finished Jul 27 05:52:49 PM PDT 24
Peak memory 197404 kb
Host smart-f1e9b752-8b3d-43b4-a8f6-99acad637351
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560243345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2560243345
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3557702417
Short name T358
Test name
Test status
Simulation time 10727936362 ps
CPU time 153.17 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 198820 kb
Host smart-68104dc3-6c69-4671-84b1-5010a7c9708a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557702417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3557702417
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.866557699
Short name T222
Test name
Test status
Simulation time 12228122 ps
CPU time 0.57 seconds
Started Jul 27 05:52:54 PM PDT 24
Finished Jul 27 05:52:55 PM PDT 24
Peak memory 194388 kb
Host smart-21b62ec1-66ce-4fc1-89df-1424a652f432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866557699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.866557699
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2704784925
Short name T387
Test name
Test status
Simulation time 276660860 ps
CPU time 0.95 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 196560 kb
Host smart-0b3439cd-c972-40e5-8a0f-de4e6bbd74e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704784925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2704784925
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1601188512
Short name T166
Test name
Test status
Simulation time 218342261 ps
CPU time 11.18 seconds
Started Jul 27 05:52:53 PM PDT 24
Finished Jul 27 05:53:05 PM PDT 24
Peak memory 196064 kb
Host smart-9724fb41-2286-4ae9-b1dd-864091e86361
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601188512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1601188512
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.249575803
Short name T392
Test name
Test status
Simulation time 200948020 ps
CPU time 0.8 seconds
Started Jul 27 05:52:53 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 196360 kb
Host smart-c7ed55dd-e0a0-451c-adf1-9a3c30f833d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249575803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.249575803
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3149118486
Short name T251
Test name
Test status
Simulation time 31876060 ps
CPU time 0.78 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 195856 kb
Host smart-31c3b89b-94fa-49e9-bf7f-be2ae9c2593a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149118486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3149118486
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3563658024
Short name T450
Test name
Test status
Simulation time 124233951 ps
CPU time 1.41 seconds
Started Jul 27 05:52:54 PM PDT 24
Finished Jul 27 05:52:55 PM PDT 24
Peak memory 197024 kb
Host smart-59701e22-8339-4096-9cc4-a372b1437fc7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563658024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3563658024
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.443527320
Short name T268
Test name
Test status
Simulation time 150906751 ps
CPU time 2.91 seconds
Started Jul 27 05:52:51 PM PDT 24
Finished Jul 27 05:52:54 PM PDT 24
Peak memory 197684 kb
Host smart-8fe8d78c-cf85-4b96-af0a-5047994004e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443527320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
443527320
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2720905319
Short name T138
Test name
Test status
Simulation time 234428088 ps
CPU time 1.09 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 196532 kb
Host smart-0f576dc1-2a78-4675-bfa2-908deebb299f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720905319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2720905319
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.773528293
Short name T529
Test name
Test status
Simulation time 21862112 ps
CPU time 0.82 seconds
Started Jul 27 05:52:51 PM PDT 24
Finished Jul 27 05:52:52 PM PDT 24
Peak memory 196976 kb
Host smart-fc5ed9e4-6836-4476-9efa-d13bfe34c938
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773528293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.773528293
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2127006441
Short name T178
Test name
Test status
Simulation time 354191774 ps
CPU time 5.91 seconds
Started Jul 27 05:52:56 PM PDT 24
Finished Jul 27 05:53:02 PM PDT 24
Peak memory 198448 kb
Host smart-c7a3de05-c86e-4c8a-81e9-c571aa2e4c28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127006441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2127006441
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1720300881
Short name T372
Test name
Test status
Simulation time 744828450 ps
CPU time 1.63 seconds
Started Jul 27 05:52:51 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 197252 kb
Host smart-3b70b265-7254-4852-89c7-9b4f54d8902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720300881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1720300881
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1051299794
Short name T61
Test name
Test status
Simulation time 149366367 ps
CPU time 1.31 seconds
Started Jul 27 05:52:56 PM PDT 24
Finished Jul 27 05:52:58 PM PDT 24
Peak memory 197152 kb
Host smart-c4bf1b18-4cf6-47d5-840a-12b0f8aa69db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051299794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1051299794
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3214885168
Short name T2
Test name
Test status
Simulation time 4376640201 ps
CPU time 52.64 seconds
Started Jul 27 05:52:51 PM PDT 24
Finished Jul 27 05:53:44 PM PDT 24
Peak memory 198660 kb
Host smart-bd639e55-39a4-4eee-a8c3-12b235ff5c5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214885168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3214885168
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1732854053
Short name T26
Test name
Test status
Simulation time 351836816506 ps
CPU time 808.4 seconds
Started Jul 27 05:52:51 PM PDT 24
Finished Jul 27 06:06:20 PM PDT 24
Peak memory 198700 kb
Host smart-6673dc6c-4020-4c7c-811e-b45bcbe00028
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1732854053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1732854053
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3779638979
Short name T246
Test name
Test status
Simulation time 51464534 ps
CPU time 0.59 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:52 PM PDT 24
Peak memory 194600 kb
Host smart-9a33c997-7009-48fd-991b-0de91fd94bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779638979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3779638979
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2474991542
Short name T623
Test name
Test status
Simulation time 35040098 ps
CPU time 0.69 seconds
Started Jul 27 05:52:56 PM PDT 24
Finished Jul 27 05:52:57 PM PDT 24
Peak memory 194652 kb
Host smart-8eff8b68-c7ad-4eaa-9cb6-90e7c164406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474991542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2474991542
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3122957684
Short name T485
Test name
Test status
Simulation time 286411115 ps
CPU time 14.79 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:53:07 PM PDT 24
Peak memory 197024 kb
Host smart-4d897d7b-c21b-49cf-990e-b3b05702a0a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122957684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3122957684
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.778257524
Short name T549
Test name
Test status
Simulation time 51602111 ps
CPU time 0.89 seconds
Started Jul 27 05:52:54 PM PDT 24
Finished Jul 27 05:52:55 PM PDT 24
Peak memory 197096 kb
Host smart-e384ae8e-38f2-4c53-b2cf-5db29e2e4b6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778257524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.778257524
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2589594819
Short name T519
Test name
Test status
Simulation time 326206526 ps
CPU time 1.21 seconds
Started Jul 27 05:52:51 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 196336 kb
Host smart-ed48846a-ca99-4809-9b96-958ef3af374a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589594819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2589594819
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2240066022
Short name T383
Test name
Test status
Simulation time 68705272 ps
CPU time 2.68 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:55 PM PDT 24
Peak memory 198564 kb
Host smart-66f9bce9-7c55-431d-bac9-fe3e84a04bf8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240066022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2240066022
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.952877969
Short name T602
Test name
Test status
Simulation time 204401343 ps
CPU time 2.54 seconds
Started Jul 27 05:52:54 PM PDT 24
Finished Jul 27 05:52:56 PM PDT 24
Peak memory 197676 kb
Host smart-17dab4ce-159e-491a-978d-299b06754fbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952877969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
952877969
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2095159968
Short name T269
Test name
Test status
Simulation time 61328829 ps
CPU time 1.39 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:54 PM PDT 24
Peak memory 197524 kb
Host smart-d69c165f-b617-42d4-9ce9-cc65aa13c44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095159968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2095159968
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3995171466
Short name T202
Test name
Test status
Simulation time 54680108 ps
CPU time 1.08 seconds
Started Jul 27 05:52:51 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 196472 kb
Host smart-3b65cfd2-96f8-489d-ab15-19538cf742d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995171466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3995171466
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1803435950
Short name T420
Test name
Test status
Simulation time 283874494 ps
CPU time 3.55 seconds
Started Jul 27 05:52:54 PM PDT 24
Finished Jul 27 05:52:58 PM PDT 24
Peak memory 198496 kb
Host smart-597278ea-b75a-489b-830d-55fa5c4f11a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803435950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1803435950
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.363719889
Short name T156
Test name
Test status
Simulation time 50823560 ps
CPU time 1.06 seconds
Started Jul 27 05:52:53 PM PDT 24
Finished Jul 27 05:52:54 PM PDT 24
Peak memory 196764 kb
Host smart-921243e8-f0fc-4430-86a5-763529bfac92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363719889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.363719889
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.897972876
Short name T560
Test name
Test status
Simulation time 102331610 ps
CPU time 0.85 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 196520 kb
Host smart-5002265d-e9ca-4e7a-9923-87834b05b001
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897972876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.897972876
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.390184928
Short name T367
Test name
Test status
Simulation time 6757588693 ps
CPU time 22.25 seconds
Started Jul 27 05:52:54 PM PDT 24
Finished Jul 27 05:53:16 PM PDT 24
Peak memory 198660 kb
Host smart-150a4702-509d-4205-9a20-f305ca15ca8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390184928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.390184928
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2966987398
Short name T634
Test name
Test status
Simulation time 17426738 ps
CPU time 0.6 seconds
Started Jul 27 05:52:59 PM PDT 24
Finished Jul 27 05:53:00 PM PDT 24
Peak memory 195356 kb
Host smart-c5c1a78f-9302-4e91-bd84-a73fd0ad6115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966987398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2966987398
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2959287090
Short name T313
Test name
Test status
Simulation time 47697240 ps
CPU time 0.68 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 194488 kb
Host smart-db51758c-c0c5-40f7-85c5-8c566eeaf6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959287090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2959287090
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3117817698
Short name T292
Test name
Test status
Simulation time 289114745 ps
CPU time 3.23 seconds
Started Jul 27 05:52:59 PM PDT 24
Finished Jul 27 05:53:02 PM PDT 24
Peak memory 196312 kb
Host smart-4b7d3303-e8dd-4ee4-8fbe-8b0ea57709ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117817698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3117817698
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2350072141
Short name T449
Test name
Test status
Simulation time 26432065 ps
CPU time 0.69 seconds
Started Jul 27 05:53:02 PM PDT 24
Finished Jul 27 05:53:03 PM PDT 24
Peak memory 194960 kb
Host smart-0d4adb53-ffd5-4324-bf12-ff34ca3eaa46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350072141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2350072141
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2177884285
Short name T180
Test name
Test status
Simulation time 366534809 ps
CPU time 1.35 seconds
Started Jul 27 05:52:54 PM PDT 24
Finished Jul 27 05:52:55 PM PDT 24
Peak memory 197140 kb
Host smart-c2c44db5-bb39-4db8-9ae4-68ae844b05ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177884285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2177884285
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3220934721
Short name T23
Test name
Test status
Simulation time 55466196 ps
CPU time 1.1 seconds
Started Jul 27 05:53:02 PM PDT 24
Finished Jul 27 05:53:03 PM PDT 24
Peak memory 196936 kb
Host smart-64290315-4b57-42bf-bdb6-6f636df60d0e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220934721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3220934721
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1526772641
Short name T243
Test name
Test status
Simulation time 444461147 ps
CPU time 3.09 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:55 PM PDT 24
Peak memory 198524 kb
Host smart-dfd9bafa-8b94-419a-b0e9-e47291455ca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526772641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1526772641
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3461277572
Short name T219
Test name
Test status
Simulation time 195769234 ps
CPU time 1.08 seconds
Started Jul 27 05:52:53 PM PDT 24
Finished Jul 27 05:52:54 PM PDT 24
Peak memory 196440 kb
Host smart-81c8aa1a-52cc-4111-a2f5-ccc267b64db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461277572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3461277572
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3169436019
Short name T158
Test name
Test status
Simulation time 50098554 ps
CPU time 1.19 seconds
Started Jul 27 05:52:53 PM PDT 24
Finished Jul 27 05:52:54 PM PDT 24
Peak memory 196460 kb
Host smart-a72a7eed-2910-441c-ab67-1813acb933da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169436019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3169436019
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2370832259
Short name T620
Test name
Test status
Simulation time 465498718 ps
CPU time 5.58 seconds
Started Jul 27 05:53:02 PM PDT 24
Finished Jul 27 05:53:08 PM PDT 24
Peak memory 198464 kb
Host smart-513d2853-c937-4d2e-830f-13f40dda8519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370832259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2370832259
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2319094032
Short name T557
Test name
Test status
Simulation time 103241979 ps
CPU time 0.74 seconds
Started Jul 27 05:52:53 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 194596 kb
Host smart-860ffff5-236b-412f-8c7a-518baa4e3fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319094032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2319094032
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1172909215
Short name T454
Test name
Test status
Simulation time 27395676 ps
CPU time 0.82 seconds
Started Jul 27 05:52:52 PM PDT 24
Finished Jul 27 05:52:53 PM PDT 24
Peak memory 195732 kb
Host smart-7d745802-079c-4321-9c4e-70d2a501793b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172909215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1172909215
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.378052934
Short name T10
Test name
Test status
Simulation time 5184742626 ps
CPU time 61.63 seconds
Started Jul 27 05:53:02 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 198612 kb
Host smart-932ed8ae-6611-462b-9b0b-f64b3c783482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378052934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.378052934
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.251643730
Short name T131
Test name
Test status
Simulation time 15415358 ps
CPU time 0.61 seconds
Started Jul 27 05:53:00 PM PDT 24
Finished Jul 27 05:53:00 PM PDT 24
Peak memory 195120 kb
Host smart-310c264e-7220-4d96-a1ff-7c9864645140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251643730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.251643730
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1339325323
Short name T120
Test name
Test status
Simulation time 30633916 ps
CPU time 0.73 seconds
Started Jul 27 05:53:01 PM PDT 24
Finished Jul 27 05:53:02 PM PDT 24
Peak memory 194684 kb
Host smart-61d96ad1-d4db-4a90-b50b-06fb92b8990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339325323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1339325323
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3534065536
Short name T325
Test name
Test status
Simulation time 477455281 ps
CPU time 24.75 seconds
Started Jul 27 05:53:00 PM PDT 24
Finished Jul 27 05:53:25 PM PDT 24
Peak memory 198536 kb
Host smart-10e287be-76f9-4cbd-82bf-674d8dc7a9cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534065536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3534065536
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1190230922
Short name T692
Test name
Test status
Simulation time 114261766 ps
CPU time 0.73 seconds
Started Jul 27 05:53:02 PM PDT 24
Finished Jul 27 05:53:03 PM PDT 24
Peak memory 195808 kb
Host smart-651fa115-e16b-42e3-9d43-49c428911d6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190230922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1190230922
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2679865145
Short name T164
Test name
Test status
Simulation time 226143080 ps
CPU time 1.02 seconds
Started Jul 27 05:53:01 PM PDT 24
Finished Jul 27 05:53:02 PM PDT 24
Peak memory 197648 kb
Host smart-3795692c-0649-440b-a7f9-fd55a33ed3f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679865145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2679865145
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3519142458
Short name T347
Test name
Test status
Simulation time 285401710 ps
CPU time 3.02 seconds
Started Jul 27 05:53:03 PM PDT 24
Finished Jul 27 05:53:06 PM PDT 24
Peak memory 197020 kb
Host smart-fc484261-6bf4-43c0-92f8-ed55ab6c7d56
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519142458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3519142458
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3353466665
Short name T182
Test name
Test status
Simulation time 954559193 ps
CPU time 2.46 seconds
Started Jul 27 05:53:00 PM PDT 24
Finished Jul 27 05:53:03 PM PDT 24
Peak memory 197684 kb
Host smart-dc19bd07-1b76-41fd-86f8-ed16e41c1fa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353466665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3353466665
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3327177855
Short name T706
Test name
Test status
Simulation time 93328089 ps
CPU time 0.68 seconds
Started Jul 27 05:53:01 PM PDT 24
Finished Jul 27 05:53:02 PM PDT 24
Peak memory 194748 kb
Host smart-c886b096-43a8-4009-b892-f85cae8bca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327177855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3327177855
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1607718656
Short name T499
Test name
Test status
Simulation time 64916481 ps
CPU time 1.23 seconds
Started Jul 27 05:53:00 PM PDT 24
Finished Jul 27 05:53:01 PM PDT 24
Peak memory 198556 kb
Host smart-7e8748d0-01cd-4152-b893-ca8943217a53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607718656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1607718656
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.4060927379
Short name T366
Test name
Test status
Simulation time 439434266 ps
CPU time 5.23 seconds
Started Jul 27 05:53:00 PM PDT 24
Finished Jul 27 05:53:06 PM PDT 24
Peak memory 198500 kb
Host smart-1c35f9bc-8c03-43e6-af06-d2f02bee8884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060927379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.4060927379
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.560047470
Short name T445
Test name
Test status
Simulation time 39520839 ps
CPU time 1.18 seconds
Started Jul 27 05:53:01 PM PDT 24
Finished Jul 27 05:53:02 PM PDT 24
Peak memory 196992 kb
Host smart-4a22df05-50f6-4346-8c69-84b7f6c6ec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560047470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.560047470
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3302097989
Short name T228
Test name
Test status
Simulation time 156200104 ps
CPU time 0.89 seconds
Started Jul 27 05:53:04 PM PDT 24
Finished Jul 27 05:53:05 PM PDT 24
Peak memory 196372 kb
Host smart-76a8a257-1603-4685-a244-71deaecfec3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302097989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3302097989
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1385887042
Short name T437
Test name
Test status
Simulation time 44305185150 ps
CPU time 210.14 seconds
Started Jul 27 05:53:02 PM PDT 24
Finished Jul 27 05:56:32 PM PDT 24
Peak memory 198656 kb
Host smart-dcb2266f-643e-45ee-b992-f6780ce208fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385887042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1385887042
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3768265409
Short name T645
Test name
Test status
Simulation time 23109397 ps
CPU time 0.57 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:53:13 PM PDT 24
Peak memory 194676 kb
Host smart-5c27787c-e69a-4481-bdb3-075dd21d7ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768265409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3768265409
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.607034144
Short name T381
Test name
Test status
Simulation time 238779578 ps
CPU time 0.65 seconds
Started Jul 27 05:53:01 PM PDT 24
Finished Jul 27 05:53:02 PM PDT 24
Peak memory 194532 kb
Host smart-96d51d2d-99c2-4cfb-a05e-dcab982ed927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607034144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.607034144
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.4265487900
Short name T443
Test name
Test status
Simulation time 6638169650 ps
CPU time 20.19 seconds
Started Jul 27 05:53:05 PM PDT 24
Finished Jul 27 05:53:25 PM PDT 24
Peak memory 197220 kb
Host smart-a829ecb5-894a-4312-926c-e4be118d7bf9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265487900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4265487900
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3749624040
Short name T470
Test name
Test status
Simulation time 66397531 ps
CPU time 1.05 seconds
Started Jul 27 05:53:00 PM PDT 24
Finished Jul 27 05:53:01 PM PDT 24
Peak memory 198396 kb
Host smart-8a5effe0-baa3-4220-9aef-c099afb07813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749624040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3749624040
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.798940838
Short name T62
Test name
Test status
Simulation time 479360928 ps
CPU time 1.4 seconds
Started Jul 27 05:52:58 PM PDT 24
Finished Jul 27 05:53:00 PM PDT 24
Peak memory 197676 kb
Host smart-e9ce671b-6b43-4f5a-bbf4-30c44c8f5adc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798940838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.798940838
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2186009112
Short name T514
Test name
Test status
Simulation time 33274933 ps
CPU time 1.4 seconds
Started Jul 27 05:53:00 PM PDT 24
Finished Jul 27 05:53:01 PM PDT 24
Peak memory 197400 kb
Host smart-1eba0a7c-774e-4f8d-8f06-523e050d7875
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186009112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2186009112
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3556731314
Short name T662
Test name
Test status
Simulation time 51359230 ps
CPU time 1.99 seconds
Started Jul 27 05:53:02 PM PDT 24
Finished Jul 27 05:53:04 PM PDT 24
Peak memory 196636 kb
Host smart-953e9346-fdcd-4adb-b694-61c7dfe86066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556731314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3556731314
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3656107335
Short name T253
Test name
Test status
Simulation time 303284746 ps
CPU time 0.98 seconds
Started Jul 27 05:52:59 PM PDT 24
Finished Jul 27 05:53:00 PM PDT 24
Peak memory 196340 kb
Host smart-380fb7ba-2b13-448a-a80c-9980137c99b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656107335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3656107335
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2959880294
Short name T160
Test name
Test status
Simulation time 33816399 ps
CPU time 1.31 seconds
Started Jul 27 05:52:59 PM PDT 24
Finished Jul 27 05:53:01 PM PDT 24
Peak memory 197524 kb
Host smart-528cf33a-cc23-4313-a808-42840bf0a2cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959880294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2959880294
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1130836053
Short name T482
Test name
Test status
Simulation time 1601745780 ps
CPU time 3 seconds
Started Jul 27 05:53:03 PM PDT 24
Finished Jul 27 05:53:06 PM PDT 24
Peak memory 198360 kb
Host smart-b4151eda-257a-4be2-b235-fad352484782
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130836053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1130836053
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.101321566
Short name T424
Test name
Test status
Simulation time 74384050 ps
CPU time 1.28 seconds
Started Jul 27 05:53:00 PM PDT 24
Finished Jul 27 05:53:01 PM PDT 24
Peak memory 197244 kb
Host smart-b65fbdd9-548e-4f87-a20d-29fee40a6d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101321566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.101321566
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.4082419841
Short name T433
Test name
Test status
Simulation time 210203220 ps
CPU time 1.05 seconds
Started Jul 27 05:53:01 PM PDT 24
Finished Jul 27 05:53:02 PM PDT 24
Peak memory 197400 kb
Host smart-ac6fcff1-1453-4f11-89ca-74e41494d2ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082419841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.4082419841
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.4172663438
Short name T427
Test name
Test status
Simulation time 3506794122 ps
CPU time 96.36 seconds
Started Jul 27 05:53:00 PM PDT 24
Finished Jul 27 05:54:37 PM PDT 24
Peak memory 198668 kb
Host smart-2db48f1b-95d1-40e5-8450-1d410596b267
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172663438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.4172663438
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.661252105
Short name T168
Test name
Test status
Simulation time 26278639 ps
CPU time 0.6 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 195124 kb
Host smart-456175f4-577b-4bbf-9e2e-0cfdaade6a54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661252105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.661252105
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3439539621
Short name T280
Test name
Test status
Simulation time 168610561 ps
CPU time 0.63 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:11 PM PDT 24
Peak memory 194460 kb
Host smart-9f1eef45-604f-4b39-bae8-c47bcf2849cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439539621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3439539621
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.266059033
Short name T225
Test name
Test status
Simulation time 347189964 ps
CPU time 17.87 seconds
Started Jul 27 05:53:15 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 197000 kb
Host smart-0538e873-68d3-4371-8a16-313e908ca1df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266059033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.266059033
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2457712597
Short name T650
Test name
Test status
Simulation time 262281271 ps
CPU time 0.97 seconds
Started Jul 27 05:53:21 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 198128 kb
Host smart-2fa7334e-01e0-4a44-b798-bcdbc1433145
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457712597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2457712597
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3913171386
Short name T137
Test name
Test status
Simulation time 107553077 ps
CPU time 1.61 seconds
Started Jul 27 05:53:16 PM PDT 24
Finished Jul 27 05:53:18 PM PDT 24
Peak memory 198572 kb
Host smart-79b62149-3f49-47b2-bb81-ba99b731d864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913171386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3913171386
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3526944555
Short name T335
Test name
Test status
Simulation time 722635378 ps
CPU time 1.87 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 198604 kb
Host smart-beb8e049-4f68-439c-90f5-e037dfeec60b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526944555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3526944555
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3387326633
Short name T589
Test name
Test status
Simulation time 413628911 ps
CPU time 1.58 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 196492 kb
Host smart-5ccab2e4-0025-4ad3-81d3-99d8e68ec210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387326633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3387326633
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3755508173
Short name T509
Test name
Test status
Simulation time 709623091 ps
CPU time 1.14 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:53:13 PM PDT 24
Peak memory 196476 kb
Host smart-1930d50f-6207-47b4-9696-787007e73c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755508173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3755508173
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2312804922
Short name T483
Test name
Test status
Simulation time 207433883 ps
CPU time 1.24 seconds
Started Jul 27 05:53:10 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 197188 kb
Host smart-77bdf4e8-2d76-4197-884a-5267c651193b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312804922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2312804922
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1893443116
Short name T117
Test name
Test status
Simulation time 603275290 ps
CPU time 5.71 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:19 PM PDT 24
Peak memory 198416 kb
Host smart-b53da006-1a99-4fcd-a195-5e3acdb9f50b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893443116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1893443116
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1471849161
Short name T439
Test name
Test status
Simulation time 44492414 ps
CPU time 1.15 seconds
Started Jul 27 05:53:15 PM PDT 24
Finished Jul 27 05:53:16 PM PDT 24
Peak memory 197096 kb
Host smart-d8045124-2165-401f-87a1-1a1521a21fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471849161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1471849161
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4272662610
Short name T513
Test name
Test status
Simulation time 76833782 ps
CPU time 1.37 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 196768 kb
Host smart-31e91568-2c89-4901-9fce-17bdf5e7568c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272662610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4272662610
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1985275011
Short name T582
Test name
Test status
Simulation time 1800301295 ps
CPU time 22.32 seconds
Started Jul 27 05:53:10 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 198552 kb
Host smart-fd2b17ec-f4a2-4400-bc03-58feba541861
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985275011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1985275011
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1632018448
Short name T653
Test name
Test status
Simulation time 11089709 ps
CPU time 0.58 seconds
Started Jul 27 05:52:11 PM PDT 24
Finished Jul 27 05:52:11 PM PDT 24
Peak memory 195116 kb
Host smart-08de291d-5387-4eea-a0f1-d600a10c7b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632018448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1632018448
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1820437894
Short name T610
Test name
Test status
Simulation time 32644606 ps
CPU time 0.83 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:06 PM PDT 24
Peak memory 195708 kb
Host smart-fcba606e-a29d-4dbe-9f78-2b67970b242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820437894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1820437894
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1603508450
Short name T148
Test name
Test status
Simulation time 1069167563 ps
CPU time 14.3 seconds
Started Jul 27 05:52:12 PM PDT 24
Finished Jul 27 05:52:27 PM PDT 24
Peak memory 197680 kb
Host smart-06d577e5-5b61-4f3d-98e7-e9cf12f36091
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603508450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1603508450
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4148929181
Short name T397
Test name
Test status
Simulation time 68613065 ps
CPU time 0.67 seconds
Started Jul 27 05:52:11 PM PDT 24
Finished Jul 27 05:52:12 PM PDT 24
Peak memory 195080 kb
Host smart-24bac3fd-abfd-4c73-8bce-7b078a5d6a8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148929181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4148929181
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2647503760
Short name T214
Test name
Test status
Simulation time 734224459 ps
CPU time 1.22 seconds
Started Jul 27 05:52:04 PM PDT 24
Finished Jul 27 05:52:05 PM PDT 24
Peak memory 196624 kb
Host smart-206cb7ea-e5df-4386-b87f-2247d866a758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647503760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2647503760
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2183997095
Short name T134
Test name
Test status
Simulation time 69438295 ps
CPU time 1.64 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:07 PM PDT 24
Peak memory 197048 kb
Host smart-f493fdca-2541-4cbc-8594-657703d9a597
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183997095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2183997095
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.406649797
Short name T363
Test name
Test status
Simulation time 202099180 ps
CPU time 2.27 seconds
Started Jul 27 05:52:08 PM PDT 24
Finished Jul 27 05:52:10 PM PDT 24
Peak memory 196316 kb
Host smart-792a0c7e-98fa-49a6-aaf0-2ff13a1f117d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406649797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.406649797
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1233165479
Short name T282
Test name
Test status
Simulation time 370550603 ps
CPU time 1.32 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:07 PM PDT 24
Peak memory 197588 kb
Host smart-1ec100bb-7c7b-4511-b515-eb423d794018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233165479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1233165479
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.4242099704
Short name T681
Test name
Test status
Simulation time 83592916 ps
CPU time 1.09 seconds
Started Jul 27 05:52:07 PM PDT 24
Finished Jul 27 05:52:09 PM PDT 24
Peak memory 196600 kb
Host smart-6b33fbd1-3ee7-447e-a35e-71f4b14638d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242099704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.4242099704
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2838620690
Short name T326
Test name
Test status
Simulation time 241038506 ps
CPU time 3.24 seconds
Started Jul 27 05:52:13 PM PDT 24
Finished Jul 27 05:52:16 PM PDT 24
Peak memory 198520 kb
Host smart-520f0048-59f3-49cf-b2eb-8271133a57d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838620690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2838620690
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.148752727
Short name T44
Test name
Test status
Simulation time 163378369 ps
CPU time 0.83 seconds
Started Jul 27 05:52:11 PM PDT 24
Finished Jul 27 05:52:12 PM PDT 24
Peak memory 214372 kb
Host smart-bb6325ac-5f5a-4ecb-b3ca-ce7037461fb3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148752727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.148752727
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.902638176
Short name T474
Test name
Test status
Simulation time 126629208 ps
CPU time 1.24 seconds
Started Jul 27 05:52:05 PM PDT 24
Finished Jul 27 05:52:07 PM PDT 24
Peak memory 196132 kb
Host smart-55ae0fcc-188e-4c5c-b349-c03bd72558de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902638176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.902638176
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1713661037
Short name T667
Test name
Test status
Simulation time 176991562 ps
CPU time 0.99 seconds
Started Jul 27 05:52:06 PM PDT 24
Finished Jul 27 05:52:07 PM PDT 24
Peak memory 196028 kb
Host smart-11d77bfe-0fa8-4d2e-ad20-11b8acc79860
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713661037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1713661037
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2838061365
Short name T3
Test name
Test status
Simulation time 20450333674 ps
CPU time 54.76 seconds
Started Jul 27 05:52:13 PM PDT 24
Finished Jul 27 05:53:07 PM PDT 24
Peak memory 198608 kb
Host smart-d2cace12-919d-4728-83bb-43fc5ea88397
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838061365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2838061365
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.4256718964
Short name T56
Test name
Test status
Simulation time 97056458360 ps
CPU time 2207.98 seconds
Started Jul 27 05:52:10 PM PDT 24
Finished Jul 27 06:28:58 PM PDT 24
Peak memory 198784 kb
Host smart-0bb29852-4529-4bfa-b528-20d8f6644764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4256718964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.4256718964
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.90742934
Short name T403
Test name
Test status
Simulation time 19274709 ps
CPU time 0.59 seconds
Started Jul 27 05:53:15 PM PDT 24
Finished Jul 27 05:53:16 PM PDT 24
Peak memory 194416 kb
Host smart-ecb6d3fd-e5a4-4ab8-a126-06cc262d0abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90742934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.90742934
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1878103431
Short name T419
Test name
Test status
Simulation time 90488462 ps
CPU time 1.07 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:53:13 PM PDT 24
Peak memory 196484 kb
Host smart-2c2b90ad-e9ce-4b07-a329-d814670b4ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878103431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1878103431
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3149266210
Short name T516
Test name
Test status
Simulation time 2804015890 ps
CPU time 25.21 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:39 PM PDT 24
Peak memory 197536 kb
Host smart-f3ffaace-5a1f-4bd6-b2a3-f3733e943a2d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149266210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3149266210
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.321076677
Short name T236
Test name
Test status
Simulation time 65759837 ps
CPU time 0.9 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 197368 kb
Host smart-1f5da73d-f18e-4a41-8336-d4fd3b033e1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321076677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.321076677
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.682158950
Short name T410
Test name
Test status
Simulation time 63175390 ps
CPU time 1.01 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 197252 kb
Host smart-86d4b010-d0bb-4bfd-adc4-35a7356f1726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682158950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.682158950
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.923304605
Short name T659
Test name
Test status
Simulation time 347839748 ps
CPU time 3.28 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:15 PM PDT 24
Peak memory 198524 kb
Host smart-5e84b932-f68d-4337-911b-35105211c10f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923304605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.923304605
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2959436862
Short name T581
Test name
Test status
Simulation time 103928383 ps
CPU time 3.08 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 198564 kb
Host smart-4384a5aa-642e-4125-ae01-61843a820211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959436862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2959436862
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.723927297
Short name T351
Test name
Test status
Simulation time 71560195 ps
CPU time 1.13 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 196360 kb
Host smart-8d54474a-df6e-436a-ba68-c29de23f86fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723927297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.723927297
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2531384916
Short name T459
Test name
Test status
Simulation time 157426511 ps
CPU time 0.99 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 196452 kb
Host smart-8c9faf50-bb2c-4bb6-b1ac-bdae9c2f6823
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531384916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2531384916
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1213773936
Short name T193
Test name
Test status
Simulation time 179098723 ps
CPU time 2.94 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:53:15 PM PDT 24
Peak memory 196916 kb
Host smart-46604b94-0338-4c61-9865-b8164d4e6091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213773936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1213773936
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2909426378
Short name T75
Test name
Test status
Simulation time 246823099 ps
CPU time 1.1 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:15 PM PDT 24
Peak memory 196976 kb
Host smart-2018e8e6-0f61-4d58-acb8-bbb6d72421dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909426378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2909426378
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.654917308
Short name T566
Test name
Test status
Simulation time 26572643 ps
CPU time 0.92 seconds
Started Jul 27 05:53:10 PM PDT 24
Finished Jul 27 05:53:11 PM PDT 24
Peak memory 196288 kb
Host smart-eb0339fc-f5c2-4789-8d59-386b305b1de8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654917308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.654917308
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.758316135
Short name T252
Test name
Test status
Simulation time 2838203738 ps
CPU time 70.04 seconds
Started Jul 27 05:53:24 PM PDT 24
Finished Jul 27 05:54:34 PM PDT 24
Peak memory 198500 kb
Host smart-c5c90a59-48ca-4175-91ac-9c8e36de5433
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758316135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.758316135
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3243168116
Short name T169
Test name
Test status
Simulation time 83651391 ps
CPU time 0.56 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:18 PM PDT 24
Peak memory 195108 kb
Host smart-cd3b969b-b061-4d3f-a0fd-eeef806c3463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243168116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3243168116
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2042338911
Short name T273
Test name
Test status
Simulation time 40258321 ps
CPU time 0.98 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:53:13 PM PDT 24
Peak memory 197228 kb
Host smart-c02283d4-9c79-4b0f-bdf1-e559d85283f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042338911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2042338911
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3105643683
Short name T561
Test name
Test status
Simulation time 496201022 ps
CPU time 13.57 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:27 PM PDT 24
Peak memory 197464 kb
Host smart-bb7845bc-8c09-4760-82f9-6905bf5bc1bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105643683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3105643683
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2387571482
Short name T704
Test name
Test status
Simulation time 87290620 ps
CPU time 0.87 seconds
Started Jul 27 05:53:10 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 197116 kb
Host smart-68a6f373-1882-4b01-9656-f48c1362a22c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387571482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2387571482
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2166358282
Short name T17
Test name
Test status
Simulation time 45802332 ps
CPU time 0.81 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 196020 kb
Host smart-2fce26e6-d5eb-44df-833e-ebf2652ac8ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166358282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2166358282
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1970452237
Short name T413
Test name
Test status
Simulation time 30525408 ps
CPU time 1.39 seconds
Started Jul 27 05:53:13 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 198284 kb
Host smart-1c9d5aae-9344-47c1-8574-13152fb504e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970452237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1970452237
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3992123916
Short name T630
Test name
Test status
Simulation time 49263438 ps
CPU time 1.23 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:53:13 PM PDT 24
Peak memory 196948 kb
Host smart-799ccc67-bc4a-4c56-a893-45a8e5750e0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992123916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3992123916
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1476027566
Short name T52
Test name
Test status
Simulation time 54349341 ps
CPU time 0.67 seconds
Started Jul 27 05:53:10 PM PDT 24
Finished Jul 27 05:53:11 PM PDT 24
Peak memory 194724 kb
Host smart-11758da5-188e-4239-9d6d-dfecfc8eb60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476027566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1476027566
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2180313242
Short name T281
Test name
Test status
Simulation time 51964918 ps
CPU time 0.75 seconds
Started Jul 27 05:53:10 PM PDT 24
Finished Jul 27 05:53:11 PM PDT 24
Peak memory 195976 kb
Host smart-a99b03a5-605e-485c-a354-ca2d83b89f7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180313242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2180313242
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1497943493
Short name T448
Test name
Test status
Simulation time 43782727 ps
CPU time 1.93 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:13 PM PDT 24
Peak memory 198496 kb
Host smart-c1450d27-0d97-4009-b4bc-ece6ba0f8c1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497943493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1497943493
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3860234977
Short name T48
Test name
Test status
Simulation time 50100381 ps
CPU time 1.24 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:53:13 PM PDT 24
Peak memory 197236 kb
Host smart-c32e1ac7-ebc9-4e75-9941-c1fd83ee243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860234977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3860234977
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2743633700
Short name T613
Test name
Test status
Simulation time 257584387 ps
CPU time 1.24 seconds
Started Jul 27 05:53:10 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 196360 kb
Host smart-e456c3e0-4270-48e8-bb6c-7bdd011e69ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743633700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2743633700
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2287944255
Short name T293
Test name
Test status
Simulation time 18635522255 ps
CPU time 110.36 seconds
Started Jul 27 05:53:12 PM PDT 24
Finished Jul 27 05:55:03 PM PDT 24
Peak memory 198628 kb
Host smart-f728de5d-e462-4dc1-9cfa-ff92b98be081
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287944255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2287944255
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4209599554
Short name T190
Test name
Test status
Simulation time 44238836 ps
CPU time 0.59 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:17 PM PDT 24
Peak memory 195332 kb
Host smart-606d5607-7f26-46b6-af29-007863c90023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209599554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4209599554
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2892372604
Short name T238
Test name
Test status
Simulation time 35023607 ps
CPU time 0.82 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 195888 kb
Host smart-7f5411c1-53ec-4b80-ae19-b048a01def1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892372604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2892372604
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3473009781
Short name T600
Test name
Test status
Simulation time 279038767 ps
CPU time 3.91 seconds
Started Jul 27 05:53:18 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 196520 kb
Host smart-ef69833e-2ad0-41be-b1f8-dae410da8f7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473009781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3473009781
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1804244393
Short name T507
Test name
Test status
Simulation time 1152252297 ps
CPU time 1.06 seconds
Started Jul 27 05:53:15 PM PDT 24
Finished Jul 27 05:53:16 PM PDT 24
Peak memory 198264 kb
Host smart-1a6dae40-e203-4e72-8aa7-87b9b9292101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804244393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1804244393
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.532280216
Short name T304
Test name
Test status
Simulation time 79936469 ps
CPU time 1.31 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:13 PM PDT 24
Peak memory 197644 kb
Host smart-590559ba-6811-4ecb-b009-b07924fc40d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532280216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.532280216
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.328993187
Short name T24
Test name
Test status
Simulation time 65666330 ps
CPU time 1.36 seconds
Started Jul 27 05:53:22 PM PDT 24
Finished Jul 27 05:53:23 PM PDT 24
Peak memory 197076 kb
Host smart-64714a2d-097e-49ff-af13-b1d6eba246ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328993187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.328993187
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2842295348
Short name T543
Test name
Test status
Simulation time 462802830 ps
CPU time 2.55 seconds
Started Jul 27 05:53:22 PM PDT 24
Finished Jul 27 05:53:25 PM PDT 24
Peak memory 196300 kb
Host smart-34b26fe1-ab06-496d-a0d1-f7e585b65f3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842295348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2842295348
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3653454575
Short name T619
Test name
Test status
Simulation time 97381545 ps
CPU time 1.26 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 197632 kb
Host smart-0d1b2a75-6fd2-40a4-9797-50db95f7f697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653454575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3653454575
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.784539235
Short name T288
Test name
Test status
Simulation time 106874084 ps
CPU time 0.78 seconds
Started Jul 27 05:53:11 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 195964 kb
Host smart-6787073a-0349-4231-9f3c-8ff01ca70aa7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784539235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.784539235
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.933787558
Short name T339
Test name
Test status
Simulation time 94172751 ps
CPU time 4.02 seconds
Started Jul 27 05:53:15 PM PDT 24
Finished Jul 27 05:53:20 PM PDT 24
Peak memory 198500 kb
Host smart-985314c2-4ddb-4483-b4a8-00b1fb49290f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933787558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.933787558
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2191696098
Short name T525
Test name
Test status
Simulation time 113552287 ps
CPU time 1.15 seconds
Started Jul 27 05:53:10 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 196232 kb
Host smart-8a9a4946-592d-4c32-82a0-7a5db6df33ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191696098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2191696098
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1812381234
Short name T49
Test name
Test status
Simulation time 253609638 ps
CPU time 1.19 seconds
Started Jul 27 05:53:10 PM PDT 24
Finished Jul 27 05:53:11 PM PDT 24
Peak memory 196160 kb
Host smart-a44ae605-6ebc-41ba-8809-a0ab615b46fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812381234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1812381234
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2326727212
Short name T705
Test name
Test status
Simulation time 23632144853 ps
CPU time 156.41 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:55:54 PM PDT 24
Peak memory 198672 kb
Host smart-2becff9f-ba80-46f6-9acf-5b2bf1656d6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326727212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2326727212
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2777826521
Short name T488
Test name
Test status
Simulation time 35526280 ps
CPU time 0.56 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:17 PM PDT 24
Peak memory 194416 kb
Host smart-604e3547-8c54-4645-9765-695020a054c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777826521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2777826521
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2968174111
Short name T446
Test name
Test status
Simulation time 64457390 ps
CPU time 1.01 seconds
Started Jul 27 05:53:19 PM PDT 24
Finished Jul 27 05:53:20 PM PDT 24
Peak memory 196948 kb
Host smart-b2fbf2fd-2e4d-44cc-9d63-fe377e64baaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968174111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2968174111
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4279081348
Short name T435
Test name
Test status
Simulation time 1129213839 ps
CPU time 12.92 seconds
Started Jul 27 05:53:14 PM PDT 24
Finished Jul 27 05:53:27 PM PDT 24
Peak memory 197332 kb
Host smart-b9987527-081b-496b-8478-916ba8d64b40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279081348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4279081348
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2120278227
Short name T576
Test name
Test status
Simulation time 251922469 ps
CPU time 0.62 seconds
Started Jul 27 05:53:15 PM PDT 24
Finished Jul 27 05:53:16 PM PDT 24
Peak memory 195540 kb
Host smart-b3d37fcb-eeb6-404d-832d-80620863e739
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120278227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2120278227
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2394488073
Short name T18
Test name
Test status
Simulation time 390943823 ps
CPU time 1.32 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:19 PM PDT 24
Peak memory 197484 kb
Host smart-fcaaa7f8-d7db-4718-8daa-ed2b333cbf9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394488073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2394488073
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.20340657
Short name T126
Test name
Test status
Simulation time 69645358 ps
CPU time 2.09 seconds
Started Jul 27 05:53:18 PM PDT 24
Finished Jul 27 05:53:20 PM PDT 24
Peak memory 198520 kb
Host smart-933e1ee0-a5b2-4d64-bc11-4de9db82c82c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20340657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.gpio_intr_with_filter_rand_intr_event.20340657
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3994351734
Short name T206
Test name
Test status
Simulation time 158941126 ps
CPU time 0.89 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 195988 kb
Host smart-3f422ab5-2dce-4d18-a78d-51c1b2ae49f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994351734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3994351734
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2121474364
Short name T257
Test name
Test status
Simulation time 38037113 ps
CPU time 0.71 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:23 PM PDT 24
Peak memory 195744 kb
Host smart-3197f0b2-cfd6-4c94-9629-c6ff435afafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121474364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2121474364
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3239305481
Short name T113
Test name
Test status
Simulation time 66515345 ps
CPU time 0.84 seconds
Started Jul 27 05:53:15 PM PDT 24
Finished Jul 27 05:53:16 PM PDT 24
Peak memory 197132 kb
Host smart-5c0ad691-0a38-4229-b0e8-f5dfca795421
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239305481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3239305481
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3272480476
Short name T510
Test name
Test status
Simulation time 141618263 ps
CPU time 2.44 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:19 PM PDT 24
Peak memory 198536 kb
Host smart-388067a9-0fa9-47a2-8405-49edc0a827a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272480476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3272480476
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3737575060
Short name T365
Test name
Test status
Simulation time 258181098 ps
CPU time 1.15 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:18 PM PDT 24
Peak memory 196948 kb
Host smart-283be8a4-a1ff-496a-9704-7d9ca79db609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737575060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3737575060
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.4087218960
Short name T646
Test name
Test status
Simulation time 74099591 ps
CPU time 0.69 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:18 PM PDT 24
Peak memory 195292 kb
Host smart-76ccd7ec-a552-4969-b61d-b78c3111e75d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087218960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.4087218960
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.115502813
Short name T143
Test name
Test status
Simulation time 28069540587 ps
CPU time 136.31 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:55:34 PM PDT 24
Peak memory 198644 kb
Host smart-b52316f2-f34b-4330-b7c7-dd8c577ff37a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115502813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.115502813
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1652502522
Short name T456
Test name
Test status
Simulation time 165141535732 ps
CPU time 2327.51 seconds
Started Jul 27 05:53:16 PM PDT 24
Finished Jul 27 06:32:03 PM PDT 24
Peak memory 198828 kb
Host smart-de1238c4-e111-4e29-9855-38df67c27236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1652502522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1652502522
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1681790883
Short name T425
Test name
Test status
Simulation time 51797944 ps
CPU time 0.59 seconds
Started Jul 27 05:53:16 PM PDT 24
Finished Jul 27 05:53:17 PM PDT 24
Peak memory 195300 kb
Host smart-66e50cb7-2d42-4551-b023-98598377f4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681790883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1681790883
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1795154720
Short name T505
Test name
Test status
Simulation time 89339850 ps
CPU time 0.84 seconds
Started Jul 27 05:53:18 PM PDT 24
Finished Jul 27 05:53:19 PM PDT 24
Peak memory 196956 kb
Host smart-157f8274-b0b9-4c1b-aa8c-5b1569e76c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795154720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1795154720
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2214976235
Short name T684
Test name
Test status
Simulation time 116713685 ps
CPU time 4.17 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 195916 kb
Host smart-ec6a0377-332f-40b0-8361-1fce86d3a1aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214976235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2214976235
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3035604522
Short name T627
Test name
Test status
Simulation time 159247296 ps
CPU time 1.08 seconds
Started Jul 27 05:53:22 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 197124 kb
Host smart-fa87f4c1-a887-40ca-81bf-5892d25d7f1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035604522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3035604522
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3738228199
Short name T161
Test name
Test status
Simulation time 30760172 ps
CPU time 0.71 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:23 PM PDT 24
Peak memory 194732 kb
Host smart-73dfa8d9-4e86-42dd-ace3-1d06f6697193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738228199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3738228199
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.283978950
Short name T260
Test name
Test status
Simulation time 38258312 ps
CPU time 1.71 seconds
Started Jul 27 05:53:18 PM PDT 24
Finished Jul 27 05:53:20 PM PDT 24
Peak memory 198560 kb
Host smart-0436a022-7597-4b60-8b0f-67ff46e268e9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283978950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.283978950
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.203213631
Short name T204
Test name
Test status
Simulation time 811462111 ps
CPU time 3.23 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:26 PM PDT 24
Peak memory 197640 kb
Host smart-f628246a-bbe4-4a68-bff0-c92e015163e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203213631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
203213631
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.258789783
Short name T267
Test name
Test status
Simulation time 234300998 ps
CPU time 1.17 seconds
Started Jul 27 05:53:18 PM PDT 24
Finished Jul 27 05:53:19 PM PDT 24
Peak memory 196300 kb
Host smart-91233fd2-7ea8-4bdc-bf08-5542d1d93175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258789783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.258789783
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1580459374
Short name T518
Test name
Test status
Simulation time 79389536 ps
CPU time 0.85 seconds
Started Jul 27 05:53:15 PM PDT 24
Finished Jul 27 05:53:16 PM PDT 24
Peak memory 196352 kb
Host smart-8c1ad4bf-ed25-459b-9a06-757f011aa0a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580459374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1580459374
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.880264313
Short name T376
Test name
Test status
Simulation time 591900894 ps
CPU time 3.83 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:21 PM PDT 24
Peak memory 198516 kb
Host smart-ccbb08a7-1d3e-4cad-9ddd-8263bd1a6f50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880264313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.880264313
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1707345625
Short name T492
Test name
Test status
Simulation time 64663478 ps
CPU time 1.09 seconds
Started Jul 27 05:53:18 PM PDT 24
Finished Jul 27 05:53:19 PM PDT 24
Peak memory 196292 kb
Host smart-1cfceaad-bae0-418f-a55a-ee570ac359d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707345625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1707345625
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.83559775
Short name T114
Test name
Test status
Simulation time 51207604 ps
CPU time 1.42 seconds
Started Jul 27 05:53:21 PM PDT 24
Finished Jul 27 05:53:23 PM PDT 24
Peak memory 197196 kb
Host smart-a9d1cac4-87ea-4488-809c-024f5c82ead5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83559775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.83559775
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.344876442
Short name T440
Test name
Test status
Simulation time 38161562978 ps
CPU time 29.97 seconds
Started Jul 27 05:53:18 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 198580 kb
Host smart-7f5f9108-5d49-4bc3-8ec1-2b163ecfa838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344876442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.344876442
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2318635499
Short name T429
Test name
Test status
Simulation time 69759058719 ps
CPU time 1710.76 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 06:21:48 PM PDT 24
Peak memory 198992 kb
Host smart-61141ebb-1790-4b2e-afbb-ffcaee267d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2318635499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2318635499
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3203371654
Short name T517
Test name
Test status
Simulation time 12993808 ps
CPU time 0.57 seconds
Started Jul 27 05:53:22 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 194372 kb
Host smart-8f8d83b8-63a6-4c08-b848-02a2bbf65160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203371654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3203371654
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.61801635
Short name T46
Test name
Test status
Simulation time 18027726 ps
CPU time 0.72 seconds
Started Jul 27 05:53:19 PM PDT 24
Finished Jul 27 05:53:20 PM PDT 24
Peak memory 195304 kb
Host smart-1db53fd0-edf7-4dcd-9cba-757c7f6dc8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61801635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.61801635
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3166075754
Short name T362
Test name
Test status
Simulation time 311350731 ps
CPU time 8.67 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:26 PM PDT 24
Peak memory 197440 kb
Host smart-2cc8fe7c-fa03-42f4-9beb-84662249bc7f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166075754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3166075754
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3647458905
Short name T21
Test name
Test status
Simulation time 167483597 ps
CPU time 0.95 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 197520 kb
Host smart-6cee1fc0-2885-4848-a252-ba0f194d8ffa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647458905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3647458905
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3998227850
Short name T616
Test name
Test status
Simulation time 190723607 ps
CPU time 1.11 seconds
Started Jul 27 05:53:19 PM PDT 24
Finished Jul 27 05:53:20 PM PDT 24
Peak memory 196616 kb
Host smart-937ecdb5-843c-4ff4-95bb-d46bcdd7ff55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998227850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3998227850
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.652025176
Short name T676
Test name
Test status
Simulation time 271720108 ps
CPU time 2.52 seconds
Started Jul 27 05:53:15 PM PDT 24
Finished Jul 27 05:53:18 PM PDT 24
Peak memory 198712 kb
Host smart-2da9797c-ab37-4bab-98c7-a2bee2aa1562
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652025176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.652025176
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4292688216
Short name T327
Test name
Test status
Simulation time 135061499 ps
CPU time 2.46 seconds
Started Jul 27 05:53:18 PM PDT 24
Finished Jul 27 05:53:21 PM PDT 24
Peak memory 197672 kb
Host smart-700e97e7-16f2-4970-bce1-98beae5cac51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292688216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4292688216
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.612565468
Short name T649
Test name
Test status
Simulation time 67851434 ps
CPU time 0.96 seconds
Started Jul 27 05:53:21 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 196520 kb
Host smart-4cb2ff30-f81f-49c8-b612-4840d6c656ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612565468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.612565468
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4208065966
Short name T287
Test name
Test status
Simulation time 35990099 ps
CPU time 0.92 seconds
Started Jul 27 05:53:14 PM PDT 24
Finished Jul 27 05:53:15 PM PDT 24
Peak memory 196312 kb
Host smart-1a0c3e29-5514-4690-a287-d3034f9064cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208065966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4208065966
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3426955605
Short name T460
Test name
Test status
Simulation time 1608113573 ps
CPU time 1.53 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:19 PM PDT 24
Peak memory 198524 kb
Host smart-96e7cdec-f44c-4e1c-8af7-cb2d0906cb08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426955605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3426955605
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.800334391
Short name T200
Test name
Test status
Simulation time 164980995 ps
CPU time 0.96 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:19 PM PDT 24
Peak memory 196480 kb
Host smart-94dd0ecc-2cdc-4582-8cbc-349b831d7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800334391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.800334391
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2457540479
Short name T417
Test name
Test status
Simulation time 83159513 ps
CPU time 0.92 seconds
Started Jul 27 05:53:17 PM PDT 24
Finished Jul 27 05:53:18 PM PDT 24
Peak memory 197524 kb
Host smart-546ad5c4-0f18-477c-8856-f7dce88749d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457540479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2457540479
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1111807157
Short name T418
Test name
Test status
Simulation time 5208929436 ps
CPU time 137.67 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:55:41 PM PDT 24
Peak memory 198692 kb
Host smart-dbc876c8-f50a-475c-8532-664e9f262e14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111807157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1111807157
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2080547169
Short name T57
Test name
Test status
Simulation time 18155137475 ps
CPU time 277.78 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:58:01 PM PDT 24
Peak memory 198692 kb
Host smart-9b70f297-17ef-4a89-92db-61089af10caf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2080547169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.2080547169
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.4262481484
Short name T680
Test name
Test status
Simulation time 26991796 ps
CPU time 0.59 seconds
Started Jul 27 05:53:21 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 194624 kb
Host smart-db48feaa-afcf-4b02-b597-a3e2b85db478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262481484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.4262481484
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3108660740
Short name T533
Test name
Test status
Simulation time 28377744 ps
CPU time 0.83 seconds
Started Jul 27 05:53:21 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 195872 kb
Host smart-736053ac-fa4f-43b6-aa27-3d3ae093a0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108660740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3108660740
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2838493048
Short name T530
Test name
Test status
Simulation time 217208315 ps
CPU time 10.48 seconds
Started Jul 27 05:53:21 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 196024 kb
Host smart-a80f124f-5500-47f8-b173-df189840598c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838493048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2838493048
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1840383030
Short name T422
Test name
Test status
Simulation time 268040413 ps
CPU time 0.98 seconds
Started Jul 27 05:53:22 PM PDT 24
Finished Jul 27 05:53:23 PM PDT 24
Peak memory 197096 kb
Host smart-570f9acc-2219-4171-81ef-5792582395f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840383030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1840383030
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2752270516
Short name T110
Test name
Test status
Simulation time 274506577 ps
CPU time 1.3 seconds
Started Jul 27 05:53:25 PM PDT 24
Finished Jul 27 05:53:26 PM PDT 24
Peak memory 196568 kb
Host smart-8af4d39a-1e6c-4d9a-aa60-8e8a453190d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752270516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2752270516
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3905453816
Short name T539
Test name
Test status
Simulation time 83562530 ps
CPU time 3.36 seconds
Started Jul 27 05:53:24 PM PDT 24
Finished Jul 27 05:53:27 PM PDT 24
Peak memory 198524 kb
Host smart-708047cf-4326-4997-b0e7-dec798ca80ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905453816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3905453816
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1311593708
Short name T451
Test name
Test status
Simulation time 37340214 ps
CPU time 1.25 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 197028 kb
Host smart-0904d09a-f60c-4364-bc39-004cb8aadf28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311593708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1311593708
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2948160056
Short name T199
Test name
Test status
Simulation time 25612055 ps
CPU time 0.75 seconds
Started Jul 27 05:53:21 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 196644 kb
Host smart-195731c9-75c8-4819-911b-251cffef0695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948160056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2948160056
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.971324391
Short name T342
Test name
Test status
Simulation time 45486492 ps
CPU time 1.11 seconds
Started Jul 27 05:53:24 PM PDT 24
Finished Jul 27 05:53:25 PM PDT 24
Peak memory 197084 kb
Host smart-a9dfdfe5-57e8-4ee0-b172-ced44a377da7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971324391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.971324391
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2855274884
Short name T614
Test name
Test status
Simulation time 128419873 ps
CPU time 1.85 seconds
Started Jul 27 05:53:24 PM PDT 24
Finished Jul 27 05:53:26 PM PDT 24
Peak memory 198688 kb
Host smart-fa58ad4a-7f1b-4cf3-b36b-01f945b6b47e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855274884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2855274884
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2155436513
Short name T111
Test name
Test status
Simulation time 252538786 ps
CPU time 1.31 seconds
Started Jul 27 05:53:25 PM PDT 24
Finished Jul 27 05:53:26 PM PDT 24
Peak memory 196448 kb
Host smart-eba83c3f-300b-4195-9b71-88cebbb25030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155436513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2155436513
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.719470255
Short name T318
Test name
Test status
Simulation time 93765558 ps
CPU time 1.07 seconds
Started Jul 27 05:53:26 PM PDT 24
Finished Jul 27 05:53:27 PM PDT 24
Peak memory 197064 kb
Host smart-d4e0ac49-1ab6-4e30-ba3b-d28d69f884ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719470255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.719470255
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1632252844
Short name T668
Test name
Test status
Simulation time 10400635271 ps
CPU time 51.88 seconds
Started Jul 27 05:53:26 PM PDT 24
Finished Jul 27 05:54:18 PM PDT 24
Peak memory 198624 kb
Host smart-e13dc326-be67-4f54-b495-276c6bdd1fff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632252844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1632252844
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2142006121
Short name T608
Test name
Test status
Simulation time 20515801 ps
CPU time 0.57 seconds
Started Jul 27 05:53:26 PM PDT 24
Finished Jul 27 05:53:27 PM PDT 24
Peak memory 194388 kb
Host smart-064dd654-e066-408a-94b8-6922ec6f18d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142006121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2142006121
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2199717932
Short name T571
Test name
Test status
Simulation time 46348089 ps
CPU time 0.73 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 195712 kb
Host smart-ba64cdcf-bf33-4fe5-8663-6a9ea85c4217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199717932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2199717932
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3441362152
Short name T497
Test name
Test status
Simulation time 6050226696 ps
CPU time 19.07 seconds
Started Jul 27 05:53:28 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 198532 kb
Host smart-d3b8e5be-82e5-44c5-b198-9b94d7fe1f6f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441362152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3441362152
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.882125963
Short name T336
Test name
Test status
Simulation time 173975654 ps
CPU time 0.75 seconds
Started Jul 27 05:53:24 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 196428 kb
Host smart-09fbf95d-23df-41f8-83d4-f5a665149821
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882125963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.882125963
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1936508999
Short name T584
Test name
Test status
Simulation time 66836911 ps
CPU time 1.03 seconds
Started Jul 27 05:53:28 PM PDT 24
Finished Jul 27 05:53:29 PM PDT 24
Peak memory 196304 kb
Host smart-a3300b3e-5af9-43c5-87d1-21107e6a5560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936508999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1936508999
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3261054960
Short name T368
Test name
Test status
Simulation time 69373346 ps
CPU time 2.76 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:26 PM PDT 24
Peak memory 197040 kb
Host smart-cf747d98-a0b9-476e-a19a-6f1e3e111d8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261054960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3261054960
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.610621708
Short name T329
Test name
Test status
Simulation time 179889256 ps
CPU time 3.41 seconds
Started Jul 27 05:53:24 PM PDT 24
Finished Jul 27 05:53:27 PM PDT 24
Peak memory 197376 kb
Host smart-fbf90f5a-9988-42c4-bdd5-8a77445848e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610621708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
610621708
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2189515584
Short name T442
Test name
Test status
Simulation time 97731683 ps
CPU time 1.14 seconds
Started Jul 27 05:53:28 PM PDT 24
Finished Jul 27 05:53:29 PM PDT 24
Peak memory 197656 kb
Host smart-c5918724-3f89-496c-8e0c-d6fab9909dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189515584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2189515584
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3364996170
Short name T591
Test name
Test status
Simulation time 24055424 ps
CPU time 0.87 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 197044 kb
Host smart-5c567ef7-12dc-45d0-8916-353105fc97bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364996170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3364996170
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1301083154
Short name T502
Test name
Test status
Simulation time 698739477 ps
CPU time 5.62 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:29 PM PDT 24
Peak memory 198472 kb
Host smart-fcbe1d67-31e5-46cc-bfe3-4af7946b6939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301083154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1301083154
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.448347881
Short name T545
Test name
Test status
Simulation time 61334268 ps
CPU time 1.14 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 196328 kb
Host smart-b5c5e7a5-8f77-4843-a0c6-903fc7c8a5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448347881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.448347881
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.698611114
Short name T323
Test name
Test status
Simulation time 117312093 ps
CPU time 1.1 seconds
Started Jul 27 05:53:22 PM PDT 24
Finished Jul 27 05:53:23 PM PDT 24
Peak memory 196208 kb
Host smart-fea7b2c6-6795-4c6b-8bae-4b664e916fb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698611114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.698611114
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3440770212
Short name T314
Test name
Test status
Simulation time 62970636841 ps
CPU time 177.95 seconds
Started Jul 27 05:53:24 PM PDT 24
Finished Jul 27 05:56:22 PM PDT 24
Peak memory 198616 kb
Host smart-8a53937a-2cf3-4d5f-b18f-b12c976ded2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440770212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3440770212
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3771877908
Short name T691
Test name
Test status
Simulation time 21896426 ps
CPU time 0.61 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 194380 kb
Host smart-f6e86a15-e9d5-4fad-a5ee-2475dc000c32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771877908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3771877908
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.649653383
Short name T414
Test name
Test status
Simulation time 33559761 ps
CPU time 0.87 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 195660 kb
Host smart-2cbf7efa-668e-4839-a793-ad5f330e5c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649653383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.649653383
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2113413382
Short name T221
Test name
Test status
Simulation time 574148164 ps
CPU time 15.12 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:46 PM PDT 24
Peak memory 196068 kb
Host smart-3f791133-e426-480f-a8d8-517870c7f347
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113413382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2113413382
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1003156788
Short name T141
Test name
Test status
Simulation time 34368448 ps
CPU time 0.75 seconds
Started Jul 27 05:53:29 PM PDT 24
Finished Jul 27 05:53:30 PM PDT 24
Peak memory 195944 kb
Host smart-a9c902a6-5c15-49a1-a79f-85832e0abadf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003156788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1003156788
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2798084197
Short name T245
Test name
Test status
Simulation time 66811577 ps
CPU time 1.11 seconds
Started Jul 27 05:53:29 PM PDT 24
Finished Jul 27 05:53:30 PM PDT 24
Peak memory 197052 kb
Host smart-8fd8338f-d766-48b6-82fc-c79308702664
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798084197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2798084197
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3597704601
Short name T594
Test name
Test status
Simulation time 116861180 ps
CPU time 2.48 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:35 PM PDT 24
Peak memory 198600 kb
Host smart-e8843713-1a27-4406-ba41-fe14a49edcdf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597704601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3597704601
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4239732216
Short name T337
Test name
Test status
Simulation time 443149130 ps
CPU time 2.47 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:34 PM PDT 24
Peak memory 196336 kb
Host smart-a96c94d0-26fd-4312-b836-a58b35cc80e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239732216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4239732216
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2550666057
Short name T526
Test name
Test status
Simulation time 457307146 ps
CPU time 1.14 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 196464 kb
Host smart-0ff9b208-10a1-43aa-a175-2291ca7daf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550666057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2550666057
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.409018053
Short name T546
Test name
Test status
Simulation time 44040109 ps
CPU time 0.67 seconds
Started Jul 27 05:53:23 PM PDT 24
Finished Jul 27 05:53:24 PM PDT 24
Peak memory 194852 kb
Host smart-a8c74541-cb40-44f7-9001-5aa90f903a6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409018053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.409018053
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2349282512
Short name T541
Test name
Test status
Simulation time 114937884 ps
CPU time 2.42 seconds
Started Jul 27 05:53:33 PM PDT 24
Finished Jul 27 05:53:35 PM PDT 24
Peak memory 198480 kb
Host smart-f7a6fa7d-ef57-44a6-850c-1ea11b48562d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349282512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2349282512
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3878089185
Short name T360
Test name
Test status
Simulation time 85415005 ps
CPU time 1.29 seconds
Started Jul 27 05:53:21 PM PDT 24
Finished Jul 27 05:53:22 PM PDT 24
Peak memory 196076 kb
Host smart-c4df2a6b-a5f8-4bfc-a1ec-4fd2e261c62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878089185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3878089185
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.226521215
Short name T232
Test name
Test status
Simulation time 326213389 ps
CPU time 1.48 seconds
Started Jul 27 05:53:24 PM PDT 24
Finished Jul 27 05:53:26 PM PDT 24
Peak memory 197332 kb
Host smart-0568ef90-c93f-4687-9068-f3fc5345b7cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226521215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.226521215
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3777686126
Short name T570
Test name
Test status
Simulation time 2468088361 ps
CPU time 66 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:54:37 PM PDT 24
Peak memory 198508 kb
Host smart-938be656-a01e-407b-ab50-a2d8cf7014c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777686126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3777686126
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2249674339
Short name T151
Test name
Test status
Simulation time 37257313 ps
CPU time 0.59 seconds
Started Jul 27 05:53:30 PM PDT 24
Finished Jul 27 05:53:30 PM PDT 24
Peak memory 195144 kb
Host smart-0eabe774-7872-4f59-b9ba-c6b25c9aee29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249674339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2249674339
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4190665560
Short name T357
Test name
Test status
Simulation time 75231095 ps
CPU time 0.86 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 196976 kb
Host smart-b2172fa4-dd1c-433f-827b-1e74c37b8725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190665560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4190665560
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3328285794
Short name T651
Test name
Test status
Simulation time 471735277 ps
CPU time 12.8 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 197512 kb
Host smart-1f50c81f-f782-4db7-8e57-5dd74c388d8b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328285794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3328285794
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2066210294
Short name T122
Test name
Test status
Simulation time 70933385 ps
CPU time 0.88 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 196544 kb
Host smart-60bb3e7f-242b-4d56-ad36-6ee16c8d5a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066210294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2066210294
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1645162834
Short name T230
Test name
Test status
Simulation time 223444092 ps
CPU time 1.25 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 196304 kb
Host smart-ee7a976d-653a-4523-a57f-b72a2ebafffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645162834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1645162834
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1175340467
Short name T489
Test name
Test status
Simulation time 748305401 ps
CPU time 3.56 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:36 PM PDT 24
Peak memory 198656 kb
Host smart-dcb1a252-9bdf-491f-90dc-7d27d74f32ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175340467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1175340467
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3616582853
Short name T421
Test name
Test status
Simulation time 194163512 ps
CPU time 3.17 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:35 PM PDT 24
Peak memory 198548 kb
Host smart-6cb2e6af-3fe5-4ccb-b8b4-69f5208c0cc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616582853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3616582853
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3211812203
Short name T661
Test name
Test status
Simulation time 84112252 ps
CPU time 0.99 seconds
Started Jul 27 05:53:30 PM PDT 24
Finished Jul 27 05:53:31 PM PDT 24
Peak memory 196524 kb
Host smart-557abc84-437b-44ff-bdbe-49bd91c8e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211812203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3211812203
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4237752669
Short name T297
Test name
Test status
Simulation time 18162197 ps
CPU time 0.82 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 196016 kb
Host smart-49f30a6a-13d7-4f3b-88b3-d96ffb43c1c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237752669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.4237752669
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2743565162
Short name T438
Test name
Test status
Simulation time 567699583 ps
CPU time 4.91 seconds
Started Jul 27 05:53:30 PM PDT 24
Finished Jul 27 05:53:35 PM PDT 24
Peak memory 198444 kb
Host smart-abe0bd59-b34a-4565-b6cb-0b79d8b79b16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743565162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2743565162
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1996004038
Short name T573
Test name
Test status
Simulation time 124199814 ps
CPU time 1.13 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 196316 kb
Host smart-91048e25-d6e5-4584-80fd-2f04f8b4c63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996004038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1996004038
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1835791650
Short name T391
Test name
Test status
Simulation time 81590505 ps
CPU time 1.21 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 196252 kb
Host smart-ceddd474-fc22-4058-a309-e3fe643f5155
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835791650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1835791650
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.170568655
Short name T382
Test name
Test status
Simulation time 2969708554 ps
CPU time 81.72 seconds
Started Jul 27 05:53:29 PM PDT 24
Finished Jul 27 05:54:51 PM PDT 24
Peak memory 198636 kb
Host smart-38eea98a-6ceb-4171-ba6f-6449050ce1a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170568655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.170568655
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.314897093
Short name T611
Test name
Test status
Simulation time 68483293 ps
CPU time 0.6 seconds
Started Jul 27 05:52:09 PM PDT 24
Finished Jul 27 05:52:10 PM PDT 24
Peak memory 194428 kb
Host smart-7fccc15b-a92a-4422-9a97-7b8087fb8fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314897093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.314897093
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1070991998
Short name T286
Test name
Test status
Simulation time 69697120 ps
CPU time 0.86 seconds
Started Jul 27 05:52:11 PM PDT 24
Finished Jul 27 05:52:12 PM PDT 24
Peak memory 195700 kb
Host smart-25346b08-ecda-43bb-b808-8c86d591ada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070991998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1070991998
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1184317479
Short name T521
Test name
Test status
Simulation time 746132485 ps
CPU time 18.65 seconds
Started Jul 27 05:52:13 PM PDT 24
Finished Jul 27 05:52:32 PM PDT 24
Peak memory 197372 kb
Host smart-5aaaef1c-d18a-4bfc-a662-b2bc4cd863ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184317479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1184317479
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1947960158
Short name T375
Test name
Test status
Simulation time 141960113 ps
CPU time 0.98 seconds
Started Jul 27 05:52:12 PM PDT 24
Finished Jul 27 05:52:13 PM PDT 24
Peak memory 196892 kb
Host smart-04def526-afcd-49bb-8df9-45e2afe8617a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947960158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1947960158
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1888566500
Short name T452
Test name
Test status
Simulation time 83581203 ps
CPU time 0.73 seconds
Started Jul 27 05:52:08 PM PDT 24
Finished Jul 27 05:52:09 PM PDT 24
Peak memory 196780 kb
Host smart-ce2b89cc-b6e2-428c-8fb9-d5fb03bee5e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888566500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1888566500
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2749500913
Short name T475
Test name
Test status
Simulation time 107865873 ps
CPU time 3.46 seconds
Started Jul 27 05:52:10 PM PDT 24
Finished Jul 27 05:52:13 PM PDT 24
Peak memory 198528 kb
Host smart-c78e4ba7-5877-49f9-a129-f91fdbc2bc8a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749500913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2749500913
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.871254491
Short name T308
Test name
Test status
Simulation time 98166284 ps
CPU time 1.59 seconds
Started Jul 27 05:52:10 PM PDT 24
Finished Jul 27 05:52:11 PM PDT 24
Peak memory 196592 kb
Host smart-6ac88e07-9c09-44c4-ad7e-f083d6e0deae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871254491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.871254491
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3039568180
Short name T11
Test name
Test status
Simulation time 139385388 ps
CPU time 1.14 seconds
Started Jul 27 05:52:10 PM PDT 24
Finished Jul 27 05:52:11 PM PDT 24
Peak memory 197856 kb
Host smart-071120ac-e249-4d7a-9248-a1b58a398663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039568180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3039568180
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1707244731
Short name T369
Test name
Test status
Simulation time 62961478 ps
CPU time 1.21 seconds
Started Jul 27 05:52:11 PM PDT 24
Finished Jul 27 05:52:12 PM PDT 24
Peak memory 197472 kb
Host smart-2eb1c36c-cc3a-40e8-8e75-e35060fc3233
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707244731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1707244731
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1292669081
Short name T290
Test name
Test status
Simulation time 376878066 ps
CPU time 6.21 seconds
Started Jul 27 05:52:12 PM PDT 24
Finished Jul 27 05:52:19 PM PDT 24
Peak memory 198700 kb
Host smart-f4f72fd2-7744-4220-b513-d8e7a85d88cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292669081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1292669081
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1125391129
Short name T34
Test name
Test status
Simulation time 148081734 ps
CPU time 0.81 seconds
Started Jul 27 05:52:11 PM PDT 24
Finished Jul 27 05:52:12 PM PDT 24
Peak memory 214312 kb
Host smart-89346178-1550-488e-a871-56a24b94814b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125391129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1125391129
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2494131119
Short name T185
Test name
Test status
Simulation time 832024906 ps
CPU time 1.23 seconds
Started Jul 27 05:52:13 PM PDT 24
Finished Jul 27 05:52:14 PM PDT 24
Peak memory 197444 kb
Host smart-bf8f2cdd-7e94-419c-8864-20d513cae644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494131119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2494131119
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3606420152
Short name T179
Test name
Test status
Simulation time 564529169 ps
CPU time 1.3 seconds
Started Jul 27 05:52:10 PM PDT 24
Finished Jul 27 05:52:12 PM PDT 24
Peak memory 197104 kb
Host smart-efd18596-e174-4f40-a202-88716eb716c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606420152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3606420152
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2626471521
Short name T694
Test name
Test status
Simulation time 15563868222 ps
CPU time 224.16 seconds
Started Jul 27 05:52:09 PM PDT 24
Finished Jul 27 05:55:54 PM PDT 24
Peak memory 198548 kb
Host smart-32f15ab3-8548-483b-9865-0bcfeeb14066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626471521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2626471521
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1608782618
Short name T587
Test name
Test status
Simulation time 24951053233 ps
CPU time 753.44 seconds
Started Jul 27 05:52:11 PM PDT 24
Finished Jul 27 06:04:45 PM PDT 24
Peak memory 198764 kb
Host smart-b623bccb-8d02-4a1c-850a-5823d4bad7bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1608782618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1608782618
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3585030529
Short name T601
Test name
Test status
Simulation time 12917580 ps
CPU time 0.55 seconds
Started Jul 27 05:53:30 PM PDT 24
Finished Jul 27 05:53:30 PM PDT 24
Peak memory 195064 kb
Host smart-a26ea7c4-8a84-4d9d-8997-08cba1099fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585030529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3585030529
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.4076857150
Short name T603
Test name
Test status
Simulation time 23120069 ps
CPU time 0.8 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 195852 kb
Host smart-72c9efbc-0566-4de0-a635-b6b2f0025e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076857150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.4076857150
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2599165608
Short name T423
Test name
Test status
Simulation time 1044047897 ps
CPU time 18 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:49 PM PDT 24
Peak memory 197400 kb
Host smart-37dbebf1-a03b-4e66-8c6a-2a0e5b333121
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599165608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2599165608
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2833363174
Short name T635
Test name
Test status
Simulation time 107815359 ps
CPU time 1.17 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 196916 kb
Host smart-b512ce78-7c7d-4791-a8e1-a58b4d9b861e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833363174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2833363174
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1565130252
Short name T67
Test name
Test status
Simulation time 27650858 ps
CPU time 0.84 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 195924 kb
Host smart-5891c6b4-e1d5-4976-8bb7-e1ca0defbb67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565130252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1565130252
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2469704916
Short name T370
Test name
Test status
Simulation time 68213923 ps
CPU time 1.06 seconds
Started Jul 27 05:53:33 PM PDT 24
Finished Jul 27 05:53:34 PM PDT 24
Peak memory 196388 kb
Host smart-9ba11d6c-5b40-4afc-ae1a-045870459dde
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469704916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2469704916
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3529873294
Short name T235
Test name
Test status
Simulation time 183387089 ps
CPU time 2.78 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:35 PM PDT 24
Peak memory 198572 kb
Host smart-f14cd2aa-db0d-4257-80d6-2d471e798c56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529873294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3529873294
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.578927167
Short name T701
Test name
Test status
Simulation time 37265962 ps
CPU time 1.18 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 197496 kb
Host smart-2a371ccb-4007-4ca4-a089-75bbe56056ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578927167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.578927167
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.630340997
Short name T411
Test name
Test status
Simulation time 19241732 ps
CPU time 0.7 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 194736 kb
Host smart-0360db55-1ee2-4b1e-8c3d-1f7883b94983
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630340997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.630340997
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3108349802
Short name T8
Test name
Test status
Simulation time 380198704 ps
CPU time 2.54 seconds
Started Jul 27 05:53:30 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 198436 kb
Host smart-d490e68e-2eaa-4164-a6ed-d8edd9b575b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108349802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3108349802
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3278730763
Short name T296
Test name
Test status
Simulation time 121715875 ps
CPU time 0.93 seconds
Started Jul 27 05:53:29 PM PDT 24
Finished Jul 27 05:53:30 PM PDT 24
Peak memory 195804 kb
Host smart-89fc0caf-baa2-4052-8fc3-80c65c9902d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278730763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3278730763
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.85936315
Short name T300
Test name
Test status
Simulation time 57286391 ps
CPU time 1.43 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 197304 kb
Host smart-18cd2320-3e3e-4bee-b850-ae7fa1ab272f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85936315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.85936315
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3825294992
Short name T261
Test name
Test status
Simulation time 31592662909 ps
CPU time 159.16 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 198636 kb
Host smart-09433950-8e05-4e87-adfd-6a053ad67b68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825294992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3825294992
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.410007703
Short name T534
Test name
Test status
Simulation time 35935967 ps
CPU time 0.6 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 194612 kb
Host smart-33a41d24-a744-478e-bc1b-297026a61b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410007703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.410007703
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3708177360
Short name T364
Test name
Test status
Simulation time 178411040 ps
CPU time 1.01 seconds
Started Jul 27 05:53:46 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 196200 kb
Host smart-0f6f4dec-92af-4cae-9fcc-aa9185bfe30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708177360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3708177360
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3866001792
Short name T172
Test name
Test status
Simulation time 4155720802 ps
CPU time 24.06 seconds
Started Jul 27 05:53:40 PM PDT 24
Finished Jul 27 05:54:05 PM PDT 24
Peak memory 197552 kb
Host smart-84b0bd2b-470f-4fb5-a316-f597a63e0970
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866001792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3866001792
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3180360083
Short name T5
Test name
Test status
Simulation time 48331526 ps
CPU time 0.79 seconds
Started Jul 27 05:53:41 PM PDT 24
Finished Jul 27 05:53:42 PM PDT 24
Peak memory 196316 kb
Host smart-98a546d4-b27f-408d-808e-193afc3043cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180360083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3180360083
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3180542686
Short name T346
Test name
Test status
Simulation time 635725640 ps
CPU time 0.95 seconds
Started Jul 27 05:53:45 PM PDT 24
Finished Jul 27 05:53:46 PM PDT 24
Peak memory 196460 kb
Host smart-d52840ed-4c58-44de-a2ed-c6266f3df827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180542686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3180542686
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4069114189
Short name T189
Test name
Test status
Simulation time 244066984 ps
CPU time 2.59 seconds
Started Jul 27 05:53:42 PM PDT 24
Finished Jul 27 05:53:44 PM PDT 24
Peak memory 198640 kb
Host smart-71a0c7f5-b5bf-462d-9e06-196f4d13c8d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069114189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.4069114189
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2591118567
Short name T356
Test name
Test status
Simulation time 97111599 ps
CPU time 2.09 seconds
Started Jul 27 05:53:40 PM PDT 24
Finished Jul 27 05:53:42 PM PDT 24
Peak memory 196560 kb
Host smart-fd9376c6-36d4-46b8-8bf7-a01aac29a34c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591118567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2591118567
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3180341829
Short name T135
Test name
Test status
Simulation time 176222248 ps
CPU time 1.1 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 197356 kb
Host smart-d4f25d47-a988-46b7-ad63-2384a25d0ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180341829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3180341829
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3263834832
Short name T192
Test name
Test status
Simulation time 25065797 ps
CPU time 0.93 seconds
Started Jul 27 05:53:31 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 197288 kb
Host smart-721947b8-4d14-4aba-b226-0c259a4f286d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263834832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3263834832
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1021558782
Short name T210
Test name
Test status
Simulation time 121017044 ps
CPU time 1.29 seconds
Started Jul 27 05:53:41 PM PDT 24
Finished Jul 27 05:53:42 PM PDT 24
Peak memory 198492 kb
Host smart-48950ba2-fd48-4fe9-9e88-f00261eb538e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021558782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1021558782
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3011032244
Short name T47
Test name
Test status
Simulation time 189908364 ps
CPU time 1.08 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 196812 kb
Host smart-021262eb-9e7e-4e10-8cae-68ae84a62d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011032244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3011032244
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1113803118
Short name T12
Test name
Test status
Simulation time 135170217 ps
CPU time 0.94 seconds
Started Jul 27 05:53:32 PM PDT 24
Finished Jul 27 05:53:33 PM PDT 24
Peak memory 197632 kb
Host smart-62c2d078-3394-46b2-b01c-cfbbf032e6d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113803118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1113803118
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.132050058
Short name T144
Test name
Test status
Simulation time 13103841738 ps
CPU time 86.81 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:55:11 PM PDT 24
Peak memory 198640 kb
Host smart-3ebb84b9-5421-4219-b8f3-d3a933378d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132050058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.132050058
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.248709176
Short name T130
Test name
Test status
Simulation time 16700420 ps
CPU time 0.59 seconds
Started Jul 27 05:53:42 PM PDT 24
Finished Jul 27 05:53:43 PM PDT 24
Peak memory 195508 kb
Host smart-5257cb9b-72bb-4364-a24f-0e0bb24502e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248709176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.248709176
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.375224655
Short name T50
Test name
Test status
Simulation time 29703312 ps
CPU time 0.93 seconds
Started Jul 27 05:53:42 PM PDT 24
Finished Jul 27 05:53:43 PM PDT 24
Peak memory 196220 kb
Host smart-7bf8fe77-66c8-45f4-9725-f16eec737a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375224655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.375224655
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3873279921
Short name T333
Test name
Test status
Simulation time 1550298859 ps
CPU time 24.31 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:54:08 PM PDT 24
Peak memory 197396 kb
Host smart-55ffe843-563b-4aff-84b9-072375e9f6e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873279921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3873279921
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1505245389
Short name T176
Test name
Test status
Simulation time 124072931 ps
CPU time 0.76 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:53:44 PM PDT 24
Peak memory 196176 kb
Host smart-ffaa1c5c-fc76-41c9-a36f-a127b70d12af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505245389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1505245389
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3534211196
Short name T319
Test name
Test status
Simulation time 16472431 ps
CPU time 0.72 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:53:44 PM PDT 24
Peak memory 195576 kb
Host smart-420c386c-2967-4cf7-81c9-912b1d925803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534211196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3534211196
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2909265386
Short name T379
Test name
Test status
Simulation time 327332746 ps
CPU time 3.71 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 198532 kb
Host smart-d8863d04-fd79-49e1-9daa-8c2ec42dbac7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909265386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2909265386
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1262391437
Short name T68
Test name
Test status
Simulation time 1024525452 ps
CPU time 2.61 seconds
Started Jul 27 05:53:41 PM PDT 24
Finished Jul 27 05:53:44 PM PDT 24
Peak memory 197564 kb
Host smart-675ff56f-b4cb-40b1-a866-a15d5e374b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262391437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1262391437
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3962768812
Short name T231
Test name
Test status
Simulation time 21429434 ps
CPU time 0.74 seconds
Started Jul 27 05:53:45 PM PDT 24
Finished Jul 27 05:53:46 PM PDT 24
Peak memory 195596 kb
Host smart-58e2a95f-9c98-4c71-9307-7f12a897ba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962768812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3962768812
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.26808699
Short name T216
Test name
Test status
Simulation time 19471361 ps
CPU time 0.88 seconds
Started Jul 27 05:53:43 PM PDT 24
Finished Jul 27 05:53:44 PM PDT 24
Peak memory 197796 kb
Host smart-62f8dcbe-643f-4af5-8e21-723420dd1ffe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26808699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup_
pulldown.26808699
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2960009124
Short name T4
Test name
Test status
Simulation time 2856411800 ps
CPU time 6.04 seconds
Started Jul 27 05:53:41 PM PDT 24
Finished Jul 27 05:53:47 PM PDT 24
Peak memory 198588 kb
Host smart-b8ce3746-d3fe-4d7b-b91e-fdb4e515f261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960009124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2960009124
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3916644170
Short name T500
Test name
Test status
Simulation time 893239614 ps
CPU time 1.49 seconds
Started Jul 27 05:53:43 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 197324 kb
Host smart-5d8f6cfd-82d6-45f5-9f55-96b101bb4a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916644170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3916644170
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1938087900
Short name T265
Test name
Test status
Simulation time 91443652 ps
CPU time 1.51 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 198476 kb
Host smart-3a05f483-d70e-4a41-bd08-80e8be40264c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938087900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1938087900
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3695327932
Short name T604
Test name
Test status
Simulation time 13280462112 ps
CPU time 150.18 seconds
Started Jul 27 05:53:43 PM PDT 24
Finished Jul 27 05:56:13 PM PDT 24
Peak memory 198512 kb
Host smart-84421c47-94f4-4996-b4b6-9c0a00a450cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695327932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3695327932
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1604357476
Short name T59
Test name
Test status
Simulation time 150288725554 ps
CPU time 1139.46 seconds
Started Jul 27 05:53:42 PM PDT 24
Finished Jul 27 06:12:42 PM PDT 24
Peak memory 198796 kb
Host smart-3b1b3006-08ee-47a0-8d24-719ea04c82f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1604357476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1604357476
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.530869175
Short name T248
Test name
Test status
Simulation time 33467846 ps
CPU time 0.6 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 195064 kb
Host smart-32f6edcf-4f4d-4195-85a4-9d9bc5f02be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530869175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.530869175
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1661508156
Short name T574
Test name
Test status
Simulation time 336658532 ps
CPU time 0.86 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 197088 kb
Host smart-c4c59190-bb03-4af6-acd9-6c8e4e442a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661508156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1661508156
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.4268734848
Short name T186
Test name
Test status
Simulation time 2461846718 ps
CPU time 18.33 seconds
Started Jul 27 05:53:43 PM PDT 24
Finished Jul 27 05:54:02 PM PDT 24
Peak memory 197552 kb
Host smart-134cb069-2bcc-4f4f-9684-03255b4705b8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268734848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.4268734848
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.188576384
Short name T455
Test name
Test status
Simulation time 303732817 ps
CPU time 1.04 seconds
Started Jul 27 05:53:42 PM PDT 24
Finished Jul 27 05:53:43 PM PDT 24
Peak memory 197104 kb
Host smart-19871388-2cbe-4e55-b3c4-41e3db836260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188576384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.188576384
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.4059583874
Short name T463
Test name
Test status
Simulation time 50465956 ps
CPU time 0.93 seconds
Started Jul 27 05:53:43 PM PDT 24
Finished Jul 27 05:53:44 PM PDT 24
Peak memory 196792 kb
Host smart-ded1f041-3d3e-4e7f-a99f-ba5d684ac030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059583874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.4059583874
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2485634449
Short name T396
Test name
Test status
Simulation time 81674937 ps
CPU time 3.26 seconds
Started Jul 27 05:53:42 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 198528 kb
Host smart-e09e3e04-956c-4621-8ad4-65f84bece1d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485634449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2485634449
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1814193436
Short name T527
Test name
Test status
Simulation time 80609237 ps
CPU time 2.52 seconds
Started Jul 27 05:53:42 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 198536 kb
Host smart-dae86d89-b0d4-4f22-b817-00c492b1c276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814193436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1814193436
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1947879906
Short name T258
Test name
Test status
Simulation time 38348914 ps
CPU time 1.32 seconds
Started Jul 27 05:53:42 PM PDT 24
Finished Jul 27 05:53:44 PM PDT 24
Peak memory 197536 kb
Host smart-159be443-4857-435c-a842-f28d2c75d801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947879906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1947879906
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3182543563
Short name T572
Test name
Test status
Simulation time 40831272 ps
CPU time 1.01 seconds
Started Jul 27 05:53:45 PM PDT 24
Finished Jul 27 05:53:46 PM PDT 24
Peak memory 196348 kb
Host smart-e39b72dc-9134-449e-9d4b-d00a04fb745e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182543563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3182543563
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1382343855
Short name T679
Test name
Test status
Simulation time 973115996 ps
CPU time 4.04 seconds
Started Jul 27 05:53:43 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 198444 kb
Host smart-e7c65f10-f570-4141-88a6-d673cd93626d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382343855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1382343855
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3554572299
Short name T393
Test name
Test status
Simulation time 85933659 ps
CPU time 1.45 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:53:46 PM PDT 24
Peak memory 197228 kb
Host smart-0cd1898b-399a-4bb5-99e1-9c0ecf55540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554572299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3554572299
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3846537941
Short name T19
Test name
Test status
Simulation time 60104403 ps
CPU time 1.2 seconds
Started Jul 27 05:53:43 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 196300 kb
Host smart-b575cab4-05cb-4aae-b7d9-bf75ac34c53b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846537941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3846537941
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_alert_test.417805178
Short name T689
Test name
Test status
Simulation time 35408957 ps
CPU time 0.61 seconds
Started Jul 27 05:53:52 PM PDT 24
Finished Jul 27 05:53:52 PM PDT 24
Peak memory 194252 kb
Host smart-ef1782db-5821-4ad1-a999-09f8614a89e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417805178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.417805178
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.207553144
Short name T142
Test name
Test status
Simulation time 53122469 ps
CPU time 0.75 seconds
Started Jul 27 05:53:49 PM PDT 24
Finished Jul 27 05:53:50 PM PDT 24
Peak memory 195556 kb
Host smart-d7c3c402-6eb9-4013-9bd2-5b1595ef5609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207553144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.207553144
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2500763302
Short name T564
Test name
Test status
Simulation time 616303930 ps
CPU time 8.99 seconds
Started Jul 27 05:53:46 PM PDT 24
Finished Jul 27 05:53:56 PM PDT 24
Peak memory 198520 kb
Host smart-9b83c1c8-55ea-4308-a185-2798fc04e608
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500763302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2500763302
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2028157300
Short name T709
Test name
Test status
Simulation time 50036757 ps
CPU time 0.83 seconds
Started Jul 27 05:53:46 PM PDT 24
Finished Jul 27 05:53:47 PM PDT 24
Peak memory 196272 kb
Host smart-5b94327c-6863-483c-ad7e-b297a8eb0a47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028157300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2028157300
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3583202037
Short name T700
Test name
Test status
Simulation time 55366339 ps
CPU time 1.05 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 196532 kb
Host smart-70769ba5-e338-4150-a1c0-8b52684ffb74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583202037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3583202037
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1217207517
Short name T197
Test name
Test status
Simulation time 154155839 ps
CPU time 3.63 seconds
Started Jul 27 05:53:50 PM PDT 24
Finished Jul 27 05:53:54 PM PDT 24
Peak memory 198540 kb
Host smart-6f9352f4-1ae4-4a93-bc37-f85bffd4e9d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217207517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1217207517
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.4011323001
Short name T121
Test name
Test status
Simulation time 384764347 ps
CPU time 2.13 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:49 PM PDT 24
Peak memory 198776 kb
Host smart-5c6c6029-fd13-414e-83e0-0884f46c254b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011323001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.4011323001
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1122471960
Short name T242
Test name
Test status
Simulation time 33245679 ps
CPU time 1.18 seconds
Started Jul 27 05:53:49 PM PDT 24
Finished Jul 27 05:53:50 PM PDT 24
Peak memory 197040 kb
Host smart-7e4dcf6e-908e-457d-b473-7035a7c76bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122471960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1122471960
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4240149744
Short name T553
Test name
Test status
Simulation time 222827613 ps
CPU time 1.38 seconds
Started Jul 27 05:53:46 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 198496 kb
Host smart-092865ac-9137-40a9-a300-c45a44bfd983
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240149744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4240149744
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1451674525
Short name T702
Test name
Test status
Simulation time 117496016 ps
CPU time 3.29 seconds
Started Jul 27 05:53:48 PM PDT 24
Finished Jul 27 05:53:51 PM PDT 24
Peak memory 198520 kb
Host smart-75ffa0c6-d9d3-45dc-bd4e-da48552998fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451674525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1451674525
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2115048535
Short name T162
Test name
Test status
Simulation time 138024996 ps
CPU time 0.95 seconds
Started Jul 27 05:53:44 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 197720 kb
Host smart-897190c5-0c03-4d6d-93db-fa5021dbeb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115048535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2115048535
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3116228760
Short name T250
Test name
Test status
Simulation time 60999205 ps
CPU time 1.22 seconds
Started Jul 27 05:53:43 PM PDT 24
Finished Jul 27 05:53:45 PM PDT 24
Peak memory 198504 kb
Host smart-4cc602ad-4434-40fe-a841-d9ab183ae439
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116228760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3116228760
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2654245025
Short name T655
Test name
Test status
Simulation time 9957955472 ps
CPU time 115.86 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:55:43 PM PDT 24
Peak memory 198648 kb
Host smart-8248d3ca-e10a-47f9-9857-c3fa62c68d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654245025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2654245025
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.243802594
Short name T58
Test name
Test status
Simulation time 149595167710 ps
CPU time 1063.91 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 06:11:31 PM PDT 24
Peak memory 198792 kb
Host smart-e8e7757d-552e-4bbd-84c7-4c02dd2fc42b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=243802594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.243802594
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1008555342
Short name T596
Test name
Test status
Simulation time 10949338 ps
CPU time 0.58 seconds
Started Jul 27 05:53:50 PM PDT 24
Finished Jul 27 05:53:51 PM PDT 24
Peak memory 194368 kb
Host smart-1ef5539b-9b41-4524-8a1e-2c86af2bca50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008555342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1008555342
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2006809948
Short name T434
Test name
Test status
Simulation time 33270286 ps
CPU time 0.71 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 195552 kb
Host smart-99d04d6f-1dec-4490-b32c-6f54eb072af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006809948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2006809948
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1115932382
Short name T609
Test name
Test status
Simulation time 686054223 ps
CPU time 20.87 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:54:08 PM PDT 24
Peak memory 197124 kb
Host smart-b319ba57-26d3-41cf-8fd9-3743998b0ee0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115932382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1115932382
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3031846272
Short name T693
Test name
Test status
Simulation time 78241809 ps
CPU time 0.83 seconds
Started Jul 27 05:53:48 PM PDT 24
Finished Jul 27 05:53:49 PM PDT 24
Peak memory 196976 kb
Host smart-32924eb3-c310-4303-913b-e3ee82e6f603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031846272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3031846272
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3796858275
Short name T171
Test name
Test status
Simulation time 85878266 ps
CPU time 1.07 seconds
Started Jul 27 05:53:46 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 196276 kb
Host smart-29c8d1f8-f093-4558-b847-bb0ac5bc4494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796858275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3796858275
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.4268761911
Short name T472
Test name
Test status
Simulation time 106479213 ps
CPU time 2.43 seconds
Started Jul 27 05:53:52 PM PDT 24
Finished Jul 27 05:53:55 PM PDT 24
Peak memory 198452 kb
Host smart-f781a204-b238-4b2d-86be-08e81a1200a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268761911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.4268761911
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2978463597
Short name T487
Test name
Test status
Simulation time 336134977 ps
CPU time 2 seconds
Started Jul 27 05:53:46 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 196652 kb
Host smart-b9f83a4f-2d1d-4482-8fa1-a46cbe777244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978463597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2978463597
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.677271883
Short name T163
Test name
Test status
Simulation time 167130349 ps
CPU time 0.94 seconds
Started Jul 27 05:53:50 PM PDT 24
Finished Jul 27 05:53:51 PM PDT 24
Peak memory 196548 kb
Host smart-c3bab723-32bd-4562-9f85-e6be9cbdcca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677271883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.677271883
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.731369548
Short name T277
Test name
Test status
Simulation time 72730136 ps
CPU time 1.33 seconds
Started Jul 27 05:53:48 PM PDT 24
Finished Jul 27 05:53:49 PM PDT 24
Peak memory 197520 kb
Host smart-c5c34cba-0b10-42b0-96e3-2a0eba5e4dba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731369548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.731369548
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2278393580
Short name T648
Test name
Test status
Simulation time 96457682 ps
CPU time 4.6 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:52 PM PDT 24
Peak memory 198492 kb
Host smart-9021174b-1a60-4688-bfbd-8a709b20b9bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278393580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2278393580
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2797170233
Short name T129
Test name
Test status
Simulation time 57530908 ps
CPU time 1.13 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:49 PM PDT 24
Peak memory 196152 kb
Host smart-eb07982b-051a-411e-ab92-40a83e1d3f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797170233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2797170233
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.6169502
Short name T658
Test name
Test status
Simulation time 604684003 ps
CPU time 1.45 seconds
Started Jul 27 05:53:52 PM PDT 24
Finished Jul 27 05:53:53 PM PDT 24
Peak memory 197092 kb
Host smart-c29f1486-64d8-4847-857d-419a0639d5d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6169502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.6169502
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2441797641
Short name T266
Test name
Test status
Simulation time 6783865613 ps
CPU time 181.87 seconds
Started Jul 27 05:53:52 PM PDT 24
Finished Jul 27 05:56:54 PM PDT 24
Peak memory 198572 kb
Host smart-f3e3957e-e5c1-48dd-9143-ff247b85d69c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441797641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2441797641
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.4194329082
Short name T27
Test name
Test status
Simulation time 32186253457 ps
CPU time 651.46 seconds
Started Jul 27 05:53:50 PM PDT 24
Finished Jul 27 06:04:42 PM PDT 24
Peak memory 198736 kb
Host smart-e9ec5f42-3654-47b5-a483-90f503670b67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4194329082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.4194329082
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1258632307
Short name T295
Test name
Test status
Simulation time 35051239 ps
CPU time 0.59 seconds
Started Jul 27 05:53:50 PM PDT 24
Finished Jul 27 05:53:51 PM PDT 24
Peak memory 194412 kb
Host smart-82ac6061-364c-43d5-89ab-d980e0117459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258632307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1258632307
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4034277370
Short name T643
Test name
Test status
Simulation time 87899730 ps
CPU time 0.93 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 197088 kb
Host smart-4d9f3bfa-1f54-40f4-ad13-42c95d9a8d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034277370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4034277370
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2443766042
Short name T344
Test name
Test status
Simulation time 1214091549 ps
CPU time 7.78 seconds
Started Jul 27 05:53:52 PM PDT 24
Finished Jul 27 05:54:00 PM PDT 24
Peak memory 197380 kb
Host smart-e5ea29ae-18a9-4004-8e18-a30d59f522ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443766042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2443766042
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1048637326
Short name T328
Test name
Test status
Simulation time 70820416 ps
CPU time 0.78 seconds
Started Jul 27 05:53:48 PM PDT 24
Finished Jul 27 05:53:49 PM PDT 24
Peak memory 196444 kb
Host smart-eea9f36f-80e6-42bb-acfb-24cc0ebe3b92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048637326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1048637326
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2788310482
Short name T244
Test name
Test status
Simulation time 49767612 ps
CPU time 0.99 seconds
Started Jul 27 05:53:46 PM PDT 24
Finished Jul 27 05:53:47 PM PDT 24
Peak memory 197008 kb
Host smart-00cfd66a-21f1-4ded-8577-94ba20058e32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788310482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2788310482
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1142746861
Short name T322
Test name
Test status
Simulation time 89035975 ps
CPU time 3.41 seconds
Started Jul 27 05:53:49 PM PDT 24
Finished Jul 27 05:53:53 PM PDT 24
Peak memory 198620 kb
Host smart-c3417236-e6ee-4a19-a530-26252ba51c0c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142746861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1142746861
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.540902809
Short name T426
Test name
Test status
Simulation time 166258368 ps
CPU time 3.34 seconds
Started Jul 27 05:53:48 PM PDT 24
Finished Jul 27 05:53:52 PM PDT 24
Peak memory 197728 kb
Host smart-458be590-e12a-48a7-81fa-661af939fccd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540902809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
540902809
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2461099084
Short name T544
Test name
Test status
Simulation time 45500381 ps
CPU time 1.12 seconds
Started Jul 27 05:53:48 PM PDT 24
Finished Jul 27 05:53:49 PM PDT 24
Peak memory 196356 kb
Host smart-5fc7da9c-1c35-49b1-b53c-ab0ec22998b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461099084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2461099084
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2977526812
Short name T53
Test name
Test status
Simulation time 20433617 ps
CPU time 0.86 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:48 PM PDT 24
Peak memory 196444 kb
Host smart-c65d4b81-7718-4c7b-9fc6-b8edafb58463
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977526812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2977526812
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.114485358
Short name T558
Test name
Test status
Simulation time 3521931635 ps
CPU time 5.96 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:54 PM PDT 24
Peak memory 198564 kb
Host smart-0091f71a-b40a-48eb-8766-90c9c4b38db0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114485358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.114485358
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.779319502
Short name T315
Test name
Test status
Simulation time 230100119 ps
CPU time 1.2 seconds
Started Jul 27 05:53:50 PM PDT 24
Finished Jul 27 05:53:52 PM PDT 24
Peak memory 196228 kb
Host smart-954dae23-028c-4ea1-a01d-4c3a1efeb7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779319502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.779319502
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.609458558
Short name T458
Test name
Test status
Simulation time 41942501 ps
CPU time 1.03 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:53:49 PM PDT 24
Peak memory 196076 kb
Host smart-1482d289-0c48-4a8c-b556-4d9909ccbe9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609458558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.609458558
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2702922777
Short name T531
Test name
Test status
Simulation time 24298558203 ps
CPU time 171.85 seconds
Started Jul 27 05:53:47 PM PDT 24
Finished Jul 27 05:56:39 PM PDT 24
Peak memory 198624 kb
Host smart-265e8e26-df01-4c24-a3aa-53935313493e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702922777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2702922777
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3046870393
Short name T562
Test name
Test status
Simulation time 38023085 ps
CPU time 0.59 seconds
Started Jul 27 05:53:54 PM PDT 24
Finished Jul 27 05:53:55 PM PDT 24
Peak memory 194612 kb
Host smart-486705da-1317-4067-ab21-5886c28d298b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046870393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3046870393
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.798753105
Short name T116
Test name
Test status
Simulation time 182980663 ps
CPU time 0.97 seconds
Started Jul 27 05:53:54 PM PDT 24
Finished Jul 27 05:53:55 PM PDT 24
Peak memory 197012 kb
Host smart-74e8a86a-f7dc-461e-9432-7d6079b01bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798753105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.798753105
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1792901462
Short name T196
Test name
Test status
Simulation time 760421086 ps
CPU time 26.02 seconds
Started Jul 27 05:53:57 PM PDT 24
Finished Jul 27 05:54:23 PM PDT 24
Peak memory 197536 kb
Host smart-6ddbf769-2cd4-4be4-a93c-98db199ab213
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792901462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1792901462
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2254854817
Short name T9
Test name
Test status
Simulation time 231562971 ps
CPU time 0.84 seconds
Started Jul 27 05:53:58 PM PDT 24
Finished Jul 27 05:53:59 PM PDT 24
Peak memory 196340 kb
Host smart-447698bb-b63f-4b4a-ac41-d4b086ecdc1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254854817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2254854817
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2107484942
Short name T352
Test name
Test status
Simulation time 323922438 ps
CPU time 1.04 seconds
Started Jul 27 05:53:59 PM PDT 24
Finished Jul 27 05:54:00 PM PDT 24
Peak memory 197284 kb
Host smart-157696a6-ca8e-4ac4-969e-fa96dd110fb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107484942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2107484942
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2726177838
Short name T559
Test name
Test status
Simulation time 57185289 ps
CPU time 2.29 seconds
Started Jul 27 05:53:58 PM PDT 24
Finished Jul 27 05:54:01 PM PDT 24
Peak memory 198668 kb
Host smart-996c5a4d-e05f-49db-b522-3b27a66cf0f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726177838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2726177838
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2878566817
Short name T607
Test name
Test status
Simulation time 258541421 ps
CPU time 3.77 seconds
Started Jul 27 05:53:58 PM PDT 24
Finished Jul 27 05:54:02 PM PDT 24
Peak memory 197604 kb
Host smart-477ce224-6633-4e64-98ee-9676aabbfa2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878566817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2878566817
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1788219589
Short name T498
Test name
Test status
Simulation time 61980023 ps
CPU time 0.78 seconds
Started Jul 27 05:53:58 PM PDT 24
Finished Jul 27 05:53:59 PM PDT 24
Peak memory 196044 kb
Host smart-a88c053e-ad52-4f06-803b-68604cee5021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788219589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1788219589
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3016898734
Short name T353
Test name
Test status
Simulation time 71046427 ps
CPU time 0.71 seconds
Started Jul 27 05:53:56 PM PDT 24
Finished Jul 27 05:53:57 PM PDT 24
Peak memory 195864 kb
Host smart-ecfaba0a-7ad3-4a70-b7c6-117a61da822a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016898734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3016898734
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3080852839
Short name T399
Test name
Test status
Simulation time 814699181 ps
CPU time 5.45 seconds
Started Jul 27 05:53:58 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 198512 kb
Host smart-6044043d-3238-42bb-9b64-8ee625ca5eb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080852839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3080852839
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3040169947
Short name T632
Test name
Test status
Simulation time 78798176 ps
CPU time 1.46 seconds
Started Jul 27 05:53:52 PM PDT 24
Finished Jul 27 05:53:54 PM PDT 24
Peak memory 197272 kb
Host smart-5fedda70-eca1-4dc3-a85f-562ace9be120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040169947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3040169947
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3012101691
Short name T105
Test name
Test status
Simulation time 153695746 ps
CPU time 1.19 seconds
Started Jul 27 05:53:56 PM PDT 24
Finished Jul 27 05:53:57 PM PDT 24
Peak memory 197384 kb
Host smart-1ab2a0d5-bba5-4403-8e03-53f025d3bc39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012101691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3012101691
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2791029560
Short name T6
Test name
Test status
Simulation time 168981364604 ps
CPU time 223.15 seconds
Started Jul 27 05:53:56 PM PDT 24
Finished Jul 27 05:57:39 PM PDT 24
Peak memory 198632 kb
Host smart-08c27a00-46ae-4d2e-89ca-5997d77bd074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791029560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2791029560
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2579277847
Short name T535
Test name
Test status
Simulation time 37190642 ps
CPU time 0.6 seconds
Started Jul 27 05:54:01 PM PDT 24
Finished Jul 27 05:54:02 PM PDT 24
Peak memory 195104 kb
Host smart-80c2fa16-0688-465c-a866-7f99d5ada6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579277847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2579277847
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.270290636
Short name T621
Test name
Test status
Simulation time 48254776 ps
CPU time 0.84 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:53:56 PM PDT 24
Peak memory 196860 kb
Host smart-24dff84c-b6b6-4c56-88b2-6a6a2f07a827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270290636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.270290636
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3123023234
Short name T70
Test name
Test status
Simulation time 3468208494 ps
CPU time 25.88 seconds
Started Jul 27 05:53:54 PM PDT 24
Finished Jul 27 05:54:20 PM PDT 24
Peak memory 198660 kb
Host smart-4a517dda-9978-4c83-8b33-3a0f54a51ff5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123023234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3123023234
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2708775250
Short name T311
Test name
Test status
Simulation time 33507014 ps
CPU time 0.62 seconds
Started Jul 27 05:53:57 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 194900 kb
Host smart-402ede9e-2ed8-4039-89db-e9a04d44c714
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708775250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2708775250
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2746630490
Short name T132
Test name
Test status
Simulation time 27143593 ps
CPU time 0.74 seconds
Started Jul 27 05:54:00 PM PDT 24
Finished Jul 27 05:54:00 PM PDT 24
Peak memory 194748 kb
Host smart-f81c9c23-f94f-4a9e-ab8b-d9c97750d28e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746630490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2746630490
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2590212954
Short name T708
Test name
Test status
Simulation time 41185328 ps
CPU time 1.06 seconds
Started Jul 27 05:53:57 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 196996 kb
Host smart-8fdc13f1-c186-48d9-8d9f-43ab0e419906
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590212954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2590212954
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.207726333
Short name T478
Test name
Test status
Simulation time 686892801 ps
CPU time 3.6 seconds
Started Jul 27 05:53:54 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 197860 kb
Host smart-34c93000-dfd9-415e-bbab-d55a2c4630ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207726333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
207726333
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2530608180
Short name T208
Test name
Test status
Simulation time 346384609 ps
CPU time 1.01 seconds
Started Jul 27 05:53:58 PM PDT 24
Finished Jul 27 05:53:59 PM PDT 24
Peak memory 196352 kb
Host smart-a7dc042c-e19a-430f-bf74-302f2b15d180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530608180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2530608180
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3364111160
Short name T585
Test name
Test status
Simulation time 20220439 ps
CPU time 0.7 seconds
Started Jul 27 05:53:57 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 195632 kb
Host smart-ab420268-1e31-48dd-8e47-1401642df889
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364111160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3364111160
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.4290042287
Short name T522
Test name
Test status
Simulation time 1537297597 ps
CPU time 5.82 seconds
Started Jul 27 05:53:57 PM PDT 24
Finished Jul 27 05:54:03 PM PDT 24
Peak memory 198492 kb
Host smart-fb5a97a2-635d-4f93-a625-dd3b45d70cb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290042287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.4290042287
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1354526489
Short name T563
Test name
Test status
Simulation time 101303494 ps
CPU time 1.02 seconds
Started Jul 27 05:53:54 PM PDT 24
Finished Jul 27 05:53:55 PM PDT 24
Peak memory 197772 kb
Host smart-e8f2d22d-60f8-4ae6-94d0-1be4d1a7ba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354526489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1354526489
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1343914323
Short name T670
Test name
Test status
Simulation time 25934051 ps
CPU time 0.96 seconds
Started Jul 27 05:54:01 PM PDT 24
Finished Jul 27 05:54:02 PM PDT 24
Peak memory 196184 kb
Host smart-8992d8f2-dea0-43f3-a512-7dc5e5f14eed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343914323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1343914323
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3162800214
Short name T112
Test name
Test status
Simulation time 24873861003 ps
CPU time 171.51 seconds
Started Jul 27 05:54:01 PM PDT 24
Finished Jul 27 05:56:52 PM PDT 24
Peak memory 198568 kb
Host smart-c389ce3c-b247-4082-8e04-3a43209c8b4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162800214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3162800214
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3673146806
Short name T569
Test name
Test status
Simulation time 14611680 ps
CPU time 0.59 seconds
Started Jul 27 05:53:59 PM PDT 24
Finished Jul 27 05:54:00 PM PDT 24
Peak memory 195336 kb
Host smart-1c1e19aa-ded2-44f0-b4d2-8a1cdf02c6f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673146806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3673146806
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3726333300
Short name T506
Test name
Test status
Simulation time 80864341 ps
CPU time 0.66 seconds
Started Jul 27 05:53:59 PM PDT 24
Finished Jul 27 05:53:59 PM PDT 24
Peak memory 195200 kb
Host smart-421dcbe2-7da9-43a7-9036-a348ca69fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726333300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3726333300
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.599813706
Short name T104
Test name
Test status
Simulation time 672588789 ps
CPU time 24.19 seconds
Started Jul 27 05:53:56 PM PDT 24
Finished Jul 27 05:54:21 PM PDT 24
Peak memory 197384 kb
Host smart-e5782817-b3ad-40a4-b20b-f168266f2da3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599813706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.599813706
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.191443647
Short name T303
Test name
Test status
Simulation time 65227251 ps
CPU time 0.97 seconds
Started Jul 27 05:53:57 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 196948 kb
Host smart-f9ea0f19-5265-4605-bce6-a00dc13967d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191443647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.191443647
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1271260485
Short name T631
Test name
Test status
Simulation time 52167688 ps
CPU time 1.41 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:53:56 PM PDT 24
Peak memory 197560 kb
Host smart-2270fd4a-1f8d-4d94-9ead-8eaec7995349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271260485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1271260485
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3200348112
Short name T301
Test name
Test status
Simulation time 81842530 ps
CPU time 3.31 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 198508 kb
Host smart-45e49516-00e5-4dda-bf98-8243501e08e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200348112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3200348112
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.865464529
Short name T127
Test name
Test status
Simulation time 52940117 ps
CPU time 1.43 seconds
Started Jul 27 05:53:57 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 197708 kb
Host smart-3622455e-9c89-47a5-86ed-e8a81b231fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865464529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
865464529
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.156450096
Short name T641
Test name
Test status
Simulation time 22591823 ps
CPU time 0.72 seconds
Started Jul 27 05:53:56 PM PDT 24
Finished Jul 27 05:53:57 PM PDT 24
Peak memory 195808 kb
Host smart-7ace2288-9d88-4412-8a91-b5df451bad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156450096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.156450096
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.700255899
Short name T153
Test name
Test status
Simulation time 99766783 ps
CPU time 1.24 seconds
Started Jul 27 05:53:56 PM PDT 24
Finished Jul 27 05:53:57 PM PDT 24
Peak memory 197440 kb
Host smart-e7ff9899-5b5a-460b-945b-0fd19017ba47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700255899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.700255899
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.681390666
Short name T536
Test name
Test status
Simulation time 418058571 ps
CPU time 2.85 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 198500 kb
Host smart-ecac6a64-8d3f-4479-99aa-b4d6e0355b92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681390666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.681390666
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2444392960
Short name T686
Test name
Test status
Simulation time 138541572 ps
CPU time 0.88 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:53:56 PM PDT 24
Peak memory 197600 kb
Host smart-b47a637d-65fe-4f2f-9fa6-9bd9ae2aa294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444392960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2444392960
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.812400275
Short name T64
Test name
Test status
Simulation time 84925213 ps
CPU time 1.13 seconds
Started Jul 27 05:53:56 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 196416 kb
Host smart-760926c4-43ee-40df-9c1d-1bd5b00a7fa9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812400275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.812400275
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3763351948
Short name T551
Test name
Test status
Simulation time 85212850806 ps
CPU time 130.03 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:56:06 PM PDT 24
Peak memory 198848 kb
Host smart-3e910c4e-cebb-40e1-b1ea-512dab2c43d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763351948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3763351948
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3230318096
Short name T306
Test name
Test status
Simulation time 15545594 ps
CPU time 0.58 seconds
Started Jul 27 05:52:18 PM PDT 24
Finished Jul 27 05:52:19 PM PDT 24
Peak memory 194464 kb
Host smart-fbb2f542-9ff1-4a6c-95e9-8598e1ab963e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230318096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3230318096
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3308610967
Short name T515
Test name
Test status
Simulation time 25681140 ps
CPU time 0.92 seconds
Started Jul 27 05:52:19 PM PDT 24
Finished Jul 27 05:52:20 PM PDT 24
Peak memory 196764 kb
Host smart-14193659-daaa-4bb1-90f5-27621b57b43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308610967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3308610967
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2771180499
Short name T309
Test name
Test status
Simulation time 292081628 ps
CPU time 9.4 seconds
Started Jul 27 05:52:17 PM PDT 24
Finished Jul 27 05:52:26 PM PDT 24
Peak memory 197492 kb
Host smart-a89fc11f-f735-459f-947f-5728c6fa6b05
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771180499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2771180499
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1850585824
Short name T264
Test name
Test status
Simulation time 77623124 ps
CPU time 0.67 seconds
Started Jul 27 05:52:19 PM PDT 24
Finished Jul 27 05:52:20 PM PDT 24
Peak memory 195076 kb
Host smart-f0bb8986-fdce-4706-a23d-e4956959c688
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850585824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1850585824
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2494515102
Short name T592
Test name
Test status
Simulation time 297057607 ps
CPU time 1.03 seconds
Started Jul 27 05:52:20 PM PDT 24
Finished Jul 27 05:52:21 PM PDT 24
Peak memory 196628 kb
Host smart-fa402666-3d98-40ca-b2ac-e2c585670797
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494515102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2494515102
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2182167146
Short name T550
Test name
Test status
Simulation time 267317783 ps
CPU time 3.01 seconds
Started Jul 27 05:52:18 PM PDT 24
Finished Jul 27 05:52:21 PM PDT 24
Peak memory 197872 kb
Host smart-2f3f51f1-aaf7-40b2-9d05-f1331fe86853
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182167146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2182167146
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1629709011
Short name T272
Test name
Test status
Simulation time 192436659 ps
CPU time 0.95 seconds
Started Jul 27 05:52:17 PM PDT 24
Finished Jul 27 05:52:19 PM PDT 24
Peak memory 195920 kb
Host smart-fe53e31f-5fa0-4903-b464-d5e676935eb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629709011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1629709011
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2066174895
Short name T65
Test name
Test status
Simulation time 23479466 ps
CPU time 0.83 seconds
Started Jul 27 05:52:16 PM PDT 24
Finished Jul 27 05:52:17 PM PDT 24
Peak memory 197068 kb
Host smart-a0cb70c6-0d08-4ffb-81a2-deda3956ba7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066174895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2066174895
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2688193026
Short name T187
Test name
Test status
Simulation time 36910075 ps
CPU time 0.7 seconds
Started Jul 27 05:52:20 PM PDT 24
Finished Jul 27 05:52:21 PM PDT 24
Peak memory 194804 kb
Host smart-851afc4c-8561-490a-8d1a-4102d0b983ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688193026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2688193026
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.4003814338
Short name T565
Test name
Test status
Simulation time 56482892 ps
CPU time 1.17 seconds
Started Jul 27 05:52:18 PM PDT 24
Finished Jul 27 05:52:19 PM PDT 24
Peak memory 198528 kb
Host smart-68852d67-9c5f-4dc3-a747-b5b903c78208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003814338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.4003814338
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.2154763034
Short name T656
Test name
Test status
Simulation time 181721249 ps
CPU time 1.04 seconds
Started Jul 27 05:52:10 PM PDT 24
Finished Jul 27 05:52:11 PM PDT 24
Peak memory 197044 kb
Host smart-c78851b8-4220-4ea2-86cf-62aa403d2e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154763034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2154763034
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.153236313
Short name T664
Test name
Test status
Simulation time 180289126 ps
CPU time 1.07 seconds
Started Jul 27 05:52:17 PM PDT 24
Finished Jul 27 05:52:19 PM PDT 24
Peak memory 196256 kb
Host smart-d098908a-653d-4e5c-831b-b62c4464ff0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153236313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.153236313
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2247054789
Short name T696
Test name
Test status
Simulation time 3562400269 ps
CPU time 50.46 seconds
Started Jul 27 05:52:16 PM PDT 24
Finished Jul 27 05:53:06 PM PDT 24
Peak memory 198580 kb
Host smart-83102d1a-13ec-4b01-b55f-08488a02f2ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247054789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2247054789
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3874450574
Short name T626
Test name
Test status
Simulation time 13615547 ps
CPU time 0.59 seconds
Started Jul 27 05:54:03 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 195156 kb
Host smart-42b86d82-6afc-4c6c-ad0c-870391513bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874450574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3874450574
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.4205666933
Short name T201
Test name
Test status
Simulation time 39986735 ps
CPU time 0.84 seconds
Started Jul 27 05:53:59 PM PDT 24
Finished Jul 27 05:54:00 PM PDT 24
Peak memory 195872 kb
Host smart-24b99329-0ec3-4b7e-b30e-ee026d61b6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205666933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.4205666933
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3786878076
Short name T338
Test name
Test status
Simulation time 943367112 ps
CPU time 13.78 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:54:09 PM PDT 24
Peak memory 197432 kb
Host smart-e06a7500-b490-49b8-b2e5-27a0c872fa0e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786878076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3786878076
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1623278966
Short name T480
Test name
Test status
Simulation time 68388963 ps
CPU time 0.63 seconds
Started Jul 27 05:53:58 PM PDT 24
Finished Jul 27 05:53:59 PM PDT 24
Peak memory 194812 kb
Host smart-106d0f2f-1ad3-4c79-9b3b-b0995d154e21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623278966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1623278966
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.842846135
Short name T469
Test name
Test status
Simulation time 36874753 ps
CPU time 0.66 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:53:56 PM PDT 24
Peak memory 194684 kb
Host smart-5eb3c921-b451-48a8-9d66-a5d5048e01c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842846135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.842846135
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2311276312
Short name T388
Test name
Test status
Simulation time 66287127 ps
CPU time 2.65 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:53:57 PM PDT 24
Peak memory 198696 kb
Host smart-a438f17d-8af8-45bb-9e50-73c183db6aa7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311276312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2311276312
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.301768597
Short name T124
Test name
Test status
Simulation time 262084444 ps
CPU time 1.74 seconds
Started Jul 27 05:53:56 PM PDT 24
Finished Jul 27 05:53:58 PM PDT 24
Peak memory 196520 kb
Host smart-b812e0e0-36c3-422a-8a32-2e2b447315ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301768597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
301768597
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3797298375
Short name T624
Test name
Test status
Simulation time 57205005 ps
CPU time 1.15 seconds
Started Jul 27 05:53:55 PM PDT 24
Finished Jul 27 05:53:56 PM PDT 24
Peak memory 196568 kb
Host smart-40d28a07-eddd-47d6-9385-c26948b0938d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797298375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3797298375
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2900187335
Short name T167
Test name
Test status
Simulation time 104373359 ps
CPU time 1.05 seconds
Started Jul 27 05:53:54 PM PDT 24
Finished Jul 27 05:53:55 PM PDT 24
Peak memory 196460 kb
Host smart-d6bba22d-dd9b-43ae-a325-41b3d9cf97d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900187335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2900187335
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2508485828
Short name T698
Test name
Test status
Simulation time 406883876 ps
CPU time 4.32 seconds
Started Jul 27 05:53:58 PM PDT 24
Finished Jul 27 05:54:02 PM PDT 24
Peak memory 198360 kb
Host smart-f66999d9-9fa5-40b3-bfcd-1a2985411074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508485828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2508485828
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3753988637
Short name T699
Test name
Test status
Simulation time 134107729 ps
CPU time 1.27 seconds
Started Jul 27 05:53:54 PM PDT 24
Finished Jul 27 05:53:56 PM PDT 24
Peak memory 196244 kb
Host smart-8b89b8ed-fe04-4e6f-a039-376e42685450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753988637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3753988637
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2099873298
Short name T556
Test name
Test status
Simulation time 66312781 ps
CPU time 1.26 seconds
Started Jul 27 05:53:59 PM PDT 24
Finished Jul 27 05:54:00 PM PDT 24
Peak memory 196220 kb
Host smart-b19cf266-4ae6-41c2-8a9f-99234c9479f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099873298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2099873298
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3174896734
Short name T398
Test name
Test status
Simulation time 9463431154 ps
CPU time 108.56 seconds
Started Jul 27 05:54:02 PM PDT 24
Finished Jul 27 05:55:51 PM PDT 24
Peak memory 198524 kb
Host smart-57710951-ca26-4117-94f9-cb277412fc05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174896734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3174896734
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2870999652
Short name T663
Test name
Test status
Simulation time 21082036 ps
CPU time 0.59 seconds
Started Jul 27 05:54:03 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 195120 kb
Host smart-7ac392e2-5780-43d4-b97b-254df28ce46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870999652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2870999652
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3837662195
Short name T432
Test name
Test status
Simulation time 331085139 ps
CPU time 0.88 seconds
Started Jul 27 05:54:01 PM PDT 24
Finished Jul 27 05:54:02 PM PDT 24
Peak memory 197448 kb
Host smart-e3e82c92-7097-4516-b072-686816dbba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837662195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3837662195
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1069292590
Short name T672
Test name
Test status
Simulation time 1655459247 ps
CPU time 13.95 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:22 PM PDT 24
Peak memory 198524 kb
Host smart-4f8ef461-685d-4306-8566-58cdaf59bfa7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069292590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1069292590
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3509887345
Short name T401
Test name
Test status
Simulation time 161444541 ps
CPU time 0.7 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:54:05 PM PDT 24
Peak memory 195720 kb
Host smart-bce8c199-2c44-4857-b3ee-f1af5fa45646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509887345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3509887345
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2427003587
Short name T241
Test name
Test status
Simulation time 18929602 ps
CPU time 0.69 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:09 PM PDT 24
Peak memory 194844 kb
Host smart-5a781591-ef8b-4ead-a141-b7ffbb154d46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427003587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2427003587
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1414313479
Short name T157
Test name
Test status
Simulation time 106972168 ps
CPU time 2.21 seconds
Started Jul 27 05:54:02 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 196968 kb
Host smart-f169143f-318d-40d0-98d7-66f52afdf235
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414313479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1414313479
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1736121981
Short name T331
Test name
Test status
Simulation time 319076504 ps
CPU time 2.47 seconds
Started Jul 27 05:54:02 PM PDT 24
Finished Jul 27 05:54:05 PM PDT 24
Peak memory 197424 kb
Host smart-9bada4b8-f5b4-45f8-af88-d2bf05c68d1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736121981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1736121981
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.623725720
Short name T73
Test name
Test status
Simulation time 206856853 ps
CPU time 1.2 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:09 PM PDT 24
Peak memory 196360 kb
Host smart-a259443d-b086-4d05-ad7d-7026272881ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623725720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.623725720
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.742887626
Short name T145
Test name
Test status
Simulation time 67992822 ps
CPU time 1.34 seconds
Started Jul 27 05:54:05 PM PDT 24
Finished Jul 27 05:54:07 PM PDT 24
Peak memory 197432 kb
Host smart-b10d1e8e-9e5c-4ad8-be38-be7af36b140c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742887626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.742887626
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3787236633
Short name T191
Test name
Test status
Simulation time 426997954 ps
CPU time 2.82 seconds
Started Jul 27 05:54:05 PM PDT 24
Finished Jul 27 05:54:08 PM PDT 24
Peak memory 198492 kb
Host smart-d134137e-390a-4d07-ae37-7b63d5f19af6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787236633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3787236633
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.872904695
Short name T183
Test name
Test status
Simulation time 223532448 ps
CPU time 1.45 seconds
Started Jul 27 05:54:02 PM PDT 24
Finished Jul 27 05:54:03 PM PDT 24
Peak memory 196068 kb
Host smart-04e2b72f-c68b-4d6f-8a55-7d3231e09207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872904695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.872904695
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3429924897
Short name T217
Test name
Test status
Simulation time 324823659 ps
CPU time 1.26 seconds
Started Jul 27 05:54:03 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 196892 kb
Host smart-39d98df4-2019-4674-b174-46bef36916c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429924897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3429924897
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2361066223
Short name T675
Test name
Test status
Simulation time 18063799564 ps
CPU time 129.19 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:56:13 PM PDT 24
Peak memory 198608 kb
Host smart-08935b94-38bf-4d31-8c08-14d687b3d927
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361066223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2361066223
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.665566774
Short name T473
Test name
Test status
Simulation time 280686187704 ps
CPU time 1922.47 seconds
Started Jul 27 05:54:05 PM PDT 24
Finished Jul 27 06:26:08 PM PDT 24
Peak memory 198764 kb
Host smart-8731d8a7-1c00-40da-a09d-29ce2c86a5eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=665566774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.665566774
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.272675576
Short name T384
Test name
Test status
Simulation time 40866908 ps
CPU time 0.63 seconds
Started Jul 27 05:54:03 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 194408 kb
Host smart-081e6055-72ef-4619-a5cb-daffb1002d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272675576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.272675576
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1831682983
Short name T508
Test name
Test status
Simulation time 346056339 ps
CPU time 0.89 seconds
Started Jul 27 05:54:03 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 195732 kb
Host smart-1374549d-bd5b-487f-afe4-240051531c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831682983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1831682983
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1257483374
Short name T354
Test name
Test status
Simulation time 102241512 ps
CPU time 4.36 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:13 PM PDT 24
Peak memory 196720 kb
Host smart-701951f0-3eca-4fef-9b3f-931e004f5721
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257483374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1257483374
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1338743224
Short name T378
Test name
Test status
Simulation time 113425012 ps
CPU time 0.63 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:54:05 PM PDT 24
Peak memory 194712 kb
Host smart-9feabe45-33f5-45bc-9fa0-0b3cf345853f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338743224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1338743224
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2629581830
Short name T275
Test name
Test status
Simulation time 162775870 ps
CPU time 1.15 seconds
Started Jul 27 05:54:03 PM PDT 24
Finished Jul 27 05:54:05 PM PDT 24
Peak memory 196712 kb
Host smart-13e31c36-0b45-488d-ae2a-6f1ef972bce8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629581830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2629581830
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3739313122
Short name T359
Test name
Test status
Simulation time 510919163 ps
CPU time 1.99 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:54:06 PM PDT 24
Peak memory 198632 kb
Host smart-23a834bb-42da-42cb-adf8-3146cd666861
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739313122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3739313122
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.426909047
Short name T371
Test name
Test status
Simulation time 319597184 ps
CPU time 2.06 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:54:07 PM PDT 24
Peak memory 197660 kb
Host smart-5f832568-1ae7-4ff3-b3e3-137645785ba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426909047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
426909047
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1311243368
Short name T341
Test name
Test status
Simulation time 25456911 ps
CPU time 1.01 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:54:05 PM PDT 24
Peak memory 196304 kb
Host smart-46f3b5dc-3577-4732-b7c7-5b2e24c1f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311243368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1311243368
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1338609389
Short name T453
Test name
Test status
Simulation time 48237896 ps
CPU time 1.16 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:09 PM PDT 24
Peak memory 197340 kb
Host smart-b331403f-6ad1-4891-8bd5-c600f4b2bdf8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338609389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1338609389
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3704047816
Short name T665
Test name
Test status
Simulation time 368908021 ps
CPU time 4.39 seconds
Started Jul 27 05:54:03 PM PDT 24
Finished Jul 27 05:54:08 PM PDT 24
Peak memory 198512 kb
Host smart-b4208eea-1dc0-446d-bad3-b6136f0bc100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704047816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3704047816
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.4157980501
Short name T188
Test name
Test status
Simulation time 57969794 ps
CPU time 0.91 seconds
Started Jul 27 05:54:05 PM PDT 24
Finished Jul 27 05:54:06 PM PDT 24
Peak memory 195928 kb
Host smart-a285991d-c4a1-4ff2-8368-73b6f6b9fee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157980501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.4157980501
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.423449892
Short name T555
Test name
Test status
Simulation time 20528005 ps
CPU time 0.75 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:54:06 PM PDT 24
Peak memory 196508 kb
Host smart-ec816bb2-5379-43ad-b0cc-4b4fc5475b7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423449892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.423449892
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1994255097
Short name T63
Test name
Test status
Simulation time 5034044845 ps
CPU time 25.38 seconds
Started Jul 27 05:54:02 PM PDT 24
Finished Jul 27 05:54:28 PM PDT 24
Peak memory 198612 kb
Host smart-7135e1d1-14fe-438b-9e2a-e86906ebabb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994255097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1994255097
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3565158692
Short name T407
Test name
Test status
Simulation time 49118900214 ps
CPU time 889.54 seconds
Started Jul 27 05:54:01 PM PDT 24
Finished Jul 27 06:08:50 PM PDT 24
Peak memory 198740 kb
Host smart-e831d01d-27b8-43c4-8b5a-50f638330cc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3565158692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3565158692
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3616050163
Short name T36
Test name
Test status
Simulation time 43912413 ps
CPU time 0.64 seconds
Started Jul 27 05:54:03 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 195340 kb
Host smart-e29502e1-d158-4898-b528-0ebccc8b364a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616050163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3616050163
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4030976187
Short name T254
Test name
Test status
Simulation time 43970890 ps
CPU time 0.69 seconds
Started Jul 27 05:54:02 PM PDT 24
Finished Jul 27 05:54:03 PM PDT 24
Peak memory 194464 kb
Host smart-bc9effea-ffd3-45af-a148-0bb135314b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030976187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4030976187
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2227889764
Short name T416
Test name
Test status
Simulation time 2142575100 ps
CPU time 23.72 seconds
Started Jul 27 05:54:02 PM PDT 24
Finished Jul 27 05:54:25 PM PDT 24
Peak memory 196264 kb
Host smart-c7115136-2b27-45eb-b45a-0e1543e83d65
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227889764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2227889764
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1752274120
Short name T233
Test name
Test status
Simulation time 46495595 ps
CPU time 0.84 seconds
Started Jul 27 05:54:06 PM PDT 24
Finished Jul 27 05:54:07 PM PDT 24
Peak memory 196320 kb
Host smart-a87172a6-abbe-42d2-ae92-2e4408fc9674
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752274120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1752274120
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2481144671
Short name T567
Test name
Test status
Simulation time 47860599 ps
CPU time 1.12 seconds
Started Jul 27 05:54:00 PM PDT 24
Finished Jul 27 05:54:02 PM PDT 24
Peak memory 197388 kb
Host smart-9b0f4040-be2d-4f2a-b844-1cc475d99d68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481144671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2481144671
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.603701785
Short name T294
Test name
Test status
Simulation time 59593355 ps
CPU time 1.11 seconds
Started Jul 27 05:54:01 PM PDT 24
Finished Jul 27 05:54:03 PM PDT 24
Peak memory 196748 kb
Host smart-fe60d9db-2147-43bd-9aa7-4d4ac9fba975
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603701785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.603701785
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4023357225
Short name T276
Test name
Test status
Simulation time 1093400471 ps
CPU time 1.99 seconds
Started Jul 27 05:54:05 PM PDT 24
Finished Jul 27 05:54:07 PM PDT 24
Peak memory 197332 kb
Host smart-3836d9b0-17fc-4d33-a9cd-91ac1cf1bc0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023357225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4023357225
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2562730632
Short name T461
Test name
Test status
Simulation time 35610825 ps
CPU time 0.65 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:54:05 PM PDT 24
Peak memory 195404 kb
Host smart-76dcf738-e854-4792-93dd-089ce6fe8150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562730632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2562730632
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2867923909
Short name T361
Test name
Test status
Simulation time 96558052 ps
CPU time 0.72 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:54:05 PM PDT 24
Peak memory 196620 kb
Host smart-51d3f470-0852-437a-9f9d-ae2337342835
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867923909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2867923909
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1341963592
Short name T669
Test name
Test status
Simulation time 55506585 ps
CPU time 1.29 seconds
Started Jul 27 05:54:04 PM PDT 24
Finished Jul 27 05:54:05 PM PDT 24
Peak memory 198504 kb
Host smart-1a383d9e-9be6-4e2c-b797-c1f0ece0e7e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341963592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1341963592
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2528656528
Short name T285
Test name
Test status
Simulation time 108591480 ps
CPU time 1.09 seconds
Started Jul 27 05:54:06 PM PDT 24
Finished Jul 27 05:54:07 PM PDT 24
Peak memory 197160 kb
Host smart-8a6f96ad-cb2d-43bc-8f65-aaa537ea614c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528656528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2528656528
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2037437565
Short name T289
Test name
Test status
Simulation time 101183607 ps
CPU time 1.08 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:11 PM PDT 24
Peak memory 196928 kb
Host smart-3321dd69-9055-4b5d-9127-cc6bf711e253
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037437565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2037437565
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3221646444
Short name T247
Test name
Test status
Simulation time 6718975835 ps
CPU time 73.21 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 198572 kb
Host smart-88cc1b27-c187-4bac-9269-86e8b1d83495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221646444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3221646444
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.562181239
Short name T149
Test name
Test status
Simulation time 37027742 ps
CPU time 0.62 seconds
Started Jul 27 05:54:16 PM PDT 24
Finished Jul 27 05:54:16 PM PDT 24
Peak memory 195100 kb
Host smart-be2e6750-3810-4673-96cb-6d7802d866be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562181239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.562181239
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4252642642
Short name T274
Test name
Test status
Simulation time 102770838 ps
CPU time 0.91 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:09 PM PDT 24
Peak memory 197688 kb
Host smart-b3492ed4-4a56-4f76-8175-ca7ce3c61ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252642642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4252642642
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.126875278
Short name T484
Test name
Test status
Simulation time 1499466769 ps
CPU time 20.96 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:29 PM PDT 24
Peak memory 197316 kb
Host smart-41e42d0a-1eb6-434b-946e-7794ffa3bbd9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126875278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.126875278
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4240196401
Short name T606
Test name
Test status
Simulation time 71751790 ps
CPU time 1.09 seconds
Started Jul 27 05:54:16 PM PDT 24
Finished Jul 27 05:54:17 PM PDT 24
Peak memory 198456 kb
Host smart-963fefd2-25b8-40de-9e05-8af32335e997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240196401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4240196401
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2758294739
Short name T215
Test name
Test status
Simulation time 171140018 ps
CPU time 1.41 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:10 PM PDT 24
Peak memory 197612 kb
Host smart-128922a5-f6b2-437f-9cfd-392775f60d8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758294739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2758294739
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.317135028
Short name T468
Test name
Test status
Simulation time 128485241 ps
CPU time 2.54 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:13 PM PDT 24
Peak memory 198524 kb
Host smart-e53da1be-cdba-4c23-af17-b63c992f76a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317135028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.317135028
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2568442802
Short name T181
Test name
Test status
Simulation time 94845918 ps
CPU time 2.07 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:12 PM PDT 24
Peak memory 196720 kb
Host smart-0b5490c8-74c4-49b0-b8a2-b3334394603a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568442802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2568442802
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4038410828
Short name T444
Test name
Test status
Simulation time 78333587 ps
CPU time 1.35 seconds
Started Jul 27 05:54:06 PM PDT 24
Finished Jul 27 05:54:07 PM PDT 24
Peak memory 196440 kb
Host smart-912b258e-7d45-4cb3-a31d-bce21ea54e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038410828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4038410828
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3604761123
Short name T133
Test name
Test status
Simulation time 24315650 ps
CPU time 0.75 seconds
Started Jul 27 05:54:01 PM PDT 24
Finished Jul 27 05:54:02 PM PDT 24
Peak memory 194884 kb
Host smart-0c34d074-38d4-41d2-8b04-6b50e6acefa8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604761123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3604761123
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2905667705
Short name T386
Test name
Test status
Simulation time 914942610 ps
CPU time 5.75 seconds
Started Jul 27 05:54:09 PM PDT 24
Finished Jul 27 05:54:15 PM PDT 24
Peak memory 198476 kb
Host smart-183b3e38-6e9f-4d41-8a99-ad7d5c1c7f30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905667705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2905667705
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1738020805
Short name T226
Test name
Test status
Simulation time 78991271 ps
CPU time 1.46 seconds
Started Jul 27 05:54:06 PM PDT 24
Finished Jul 27 05:54:08 PM PDT 24
Peak memory 197348 kb
Host smart-4a00f624-82b0-43fd-baaa-4ddaf9f7b5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738020805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1738020805
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1395782876
Short name T577
Test name
Test status
Simulation time 84788603 ps
CPU time 1.51 seconds
Started Jul 27 05:54:02 PM PDT 24
Finished Jul 27 05:54:04 PM PDT 24
Peak memory 197412 kb
Host smart-579c5a62-f7cd-4d3e-9d8b-e03d3158d1d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395782876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1395782876
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2780925605
Short name T687
Test name
Test status
Simulation time 3718518643 ps
CPU time 100.25 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:55:50 PM PDT 24
Peak memory 198608 kb
Host smart-db4b95c5-3c7a-44a2-adb1-a92ef8535e02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780925605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2780925605
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.210019375
Short name T412
Test name
Test status
Simulation time 41347052031 ps
CPU time 1206.41 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 06:14:17 PM PDT 24
Peak memory 198748 kb
Host smart-9559234e-f8f2-4afa-892b-7fa9fae30846
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=210019375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.210019375
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2135650827
Short name T512
Test name
Test status
Simulation time 16468218 ps
CPU time 0.62 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:09 PM PDT 24
Peak memory 194596 kb
Host smart-e8632a5c-ce06-43fc-9b78-fca3d267e467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135650827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2135650827
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.138162559
Short name T415
Test name
Test status
Simulation time 78942515 ps
CPU time 0.85 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:12 PM PDT 24
Peak memory 195972 kb
Host smart-aa31e5a3-d041-417e-804d-c3b6b4492b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138162559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.138162559
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.343148233
Short name T406
Test name
Test status
Simulation time 323160258 ps
CPU time 4.26 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:14 PM PDT 24
Peak memory 196508 kb
Host smart-fcaf673d-d774-4b0c-85a3-5e7619e5ee02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343148233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.343148233
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3003311734
Short name T466
Test name
Test status
Simulation time 27643812 ps
CPU time 0.68 seconds
Started Jul 27 05:54:11 PM PDT 24
Finished Jul 27 05:54:12 PM PDT 24
Peak memory 195700 kb
Host smart-5e432531-ec9c-4849-81bb-ee1ae1f09991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003311734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3003311734
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3811124396
Short name T259
Test name
Test status
Simulation time 485622170 ps
CPU time 1.21 seconds
Started Jul 27 05:54:15 PM PDT 24
Finished Jul 27 05:54:16 PM PDT 24
Peak memory 196320 kb
Host smart-2b300e61-8e1a-4d96-9978-20ba6d2b79fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811124396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3811124396
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1014506941
Short name T255
Test name
Test status
Simulation time 217309770 ps
CPU time 2.36 seconds
Started Jul 27 05:54:09 PM PDT 24
Finished Jul 27 05:54:12 PM PDT 24
Peak memory 197796 kb
Host smart-03d85d19-09c6-4ad8-bb95-176eee9cc071
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014506941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1014506941
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3275781601
Short name T625
Test name
Test status
Simulation time 495394807 ps
CPU time 2.73 seconds
Started Jul 27 05:54:13 PM PDT 24
Finished Jul 27 05:54:16 PM PDT 24
Peak memory 196360 kb
Host smart-0b4b050e-bfd0-437f-b3c2-31fc5bce4005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275781601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3275781601
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3179626356
Short name T441
Test name
Test status
Simulation time 55838246 ps
CPU time 1.27 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:10 PM PDT 24
Peak memory 197060 kb
Host smart-df3ede39-b31e-43ec-98dd-0accccdfd15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179626356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3179626356
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2859719776
Short name T107
Test name
Test status
Simulation time 164434501 ps
CPU time 0.95 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:11 PM PDT 24
Peak memory 196368 kb
Host smart-905e005c-0a1e-436e-81e0-2da617f23a87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859719776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2859719776
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1488038587
Short name T307
Test name
Test status
Simulation time 436458824 ps
CPU time 5.79 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:14 PM PDT 24
Peak memory 198136 kb
Host smart-f371d830-57be-4062-a58d-a10ff45b3ef3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488038587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1488038587
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.595104266
Short name T409
Test name
Test status
Simulation time 27659774 ps
CPU time 0.88 seconds
Started Jul 27 05:54:09 PM PDT 24
Finished Jul 27 05:54:11 PM PDT 24
Peak memory 195680 kb
Host smart-46adccec-37b2-43f0-9742-4204a4f7b7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595104266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.595104266
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3104638118
Short name T495
Test name
Test status
Simulation time 60226600 ps
CPU time 1.09 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:11 PM PDT 24
Peak memory 197024 kb
Host smart-4849cf30-58f9-460a-925c-740812997163
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104638118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3104638118
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1036077620
Short name T501
Test name
Test status
Simulation time 24169344944 ps
CPU time 154.88 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:56:45 PM PDT 24
Peak memory 198612 kb
Host smart-85f12945-c938-411e-950d-0205b85b2d59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036077620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1036077620
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.4133307709
Short name T471
Test name
Test status
Simulation time 227309502801 ps
CPU time 2569.46 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 06:36:58 PM PDT 24
Peak memory 198736 kb
Host smart-71712c92-251a-425f-b11a-ac426090a546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4133307709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.4133307709
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2336027037
Short name T511
Test name
Test status
Simulation time 30530169 ps
CPU time 0.56 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:09 PM PDT 24
Peak memory 195124 kb
Host smart-6bd9a21c-c2f7-4d07-8f20-c2a34877d086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336027037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2336027037
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2352397775
Short name T644
Test name
Test status
Simulation time 17062939 ps
CPU time 0.7 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:11 PM PDT 24
Peak memory 194516 kb
Host smart-f426c4b2-29d2-4514-b2e3-6283f5a6a38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352397775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2352397775
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3986950571
Short name T298
Test name
Test status
Simulation time 544743740 ps
CPU time 8.05 seconds
Started Jul 27 05:54:12 PM PDT 24
Finished Jul 27 05:54:20 PM PDT 24
Peak memory 196968 kb
Host smart-235a53fb-413c-4d9a-a6ed-9dff89db4ed0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986950571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3986950571
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.399986910
Short name T211
Test name
Test status
Simulation time 26138698 ps
CPU time 0.75 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:11 PM PDT 24
Peak memory 196060 kb
Host smart-4e828646-163b-4dfe-8ff8-a15ea9a0cfa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399986910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.399986910
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.416998236
Short name T579
Test name
Test status
Simulation time 56712685 ps
CPU time 0.94 seconds
Started Jul 27 05:54:13 PM PDT 24
Finished Jul 27 05:54:14 PM PDT 24
Peak memory 196444 kb
Host smart-fd7111a0-0fd4-4129-8ca0-38f215c1ca19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416998236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.416998236
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3199059508
Short name T324
Test name
Test status
Simulation time 62192830 ps
CPU time 2.58 seconds
Started Jul 27 05:54:11 PM PDT 24
Finished Jul 27 05:54:13 PM PDT 24
Peak memory 197032 kb
Host smart-510e575f-6f79-450e-b530-5a38b5efbea5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199059508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3199059508
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3735053916
Short name T340
Test name
Test status
Simulation time 70650679 ps
CPU time 1.76 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:12 PM PDT 24
Peak memory 196316 kb
Host smart-d68f7ef8-3134-460c-a58d-f94b8b79c5e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735053916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3735053916
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2566845560
Short name T707
Test name
Test status
Simulation time 144030261 ps
CPU time 1.27 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:12 PM PDT 24
Peak memory 197120 kb
Host smart-5d3f40a9-4d39-4671-88fb-325f4694c255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566845560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2566845560
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2839221129
Short name T599
Test name
Test status
Simulation time 140043741 ps
CPU time 1.25 seconds
Started Jul 27 05:54:12 PM PDT 24
Finished Jul 27 05:54:13 PM PDT 24
Peak memory 198488 kb
Host smart-471947a9-7528-4d66-a958-894dd21cfb13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839221129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2839221129
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3198222454
Short name T165
Test name
Test status
Simulation time 100975748 ps
CPU time 4.8 seconds
Started Jul 27 05:54:14 PM PDT 24
Finished Jul 27 05:54:19 PM PDT 24
Peak memory 198460 kb
Host smart-3785921d-52ee-4537-9fee-4f9588cb689f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198222454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3198222454
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3091341420
Short name T586
Test name
Test status
Simulation time 96752072 ps
CPU time 1 seconds
Started Jul 27 05:54:13 PM PDT 24
Finished Jul 27 05:54:14 PM PDT 24
Peak memory 196716 kb
Host smart-ea49f963-ee16-4848-846b-4618e3f95c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091341420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3091341420
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.534644912
Short name T159
Test name
Test status
Simulation time 40226396 ps
CPU time 1.28 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:12 PM PDT 24
Peak memory 198476 kb
Host smart-003b577c-070e-43b8-8a61-47b356b24de6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534644912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.534644912
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1573327421
Short name T218
Test name
Test status
Simulation time 4771754383 ps
CPU time 66.35 seconds
Started Jul 27 05:54:15 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 198612 kb
Host smart-929e4b2a-57c5-4b61-9298-6bb9a4e27c12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573327421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1573327421
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2639184143
Short name T60
Test name
Test status
Simulation time 154635357572 ps
CPU time 893.03 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 06:09:03 PM PDT 24
Peak memory 198808 kb
Host smart-7132ed8c-76dd-4731-bd59-823874ec2309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2639184143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2639184143
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1508722139
Short name T35
Test name
Test status
Simulation time 48526951 ps
CPU time 0.56 seconds
Started Jul 27 05:54:20 PM PDT 24
Finished Jul 27 05:54:21 PM PDT 24
Peak memory 194388 kb
Host smart-21cf8282-0517-44b3-9a7e-a5045777cb2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508722139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1508722139
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1383436612
Short name T465
Test name
Test status
Simulation time 109809115 ps
CPU time 0.89 seconds
Started Jul 27 05:54:12 PM PDT 24
Finished Jul 27 05:54:13 PM PDT 24
Peak memory 197024 kb
Host smart-ed568b6e-fa5e-4100-a0b7-126655a7c8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383436612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1383436612
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3120326557
Short name T597
Test name
Test status
Simulation time 2273556547 ps
CPU time 16.9 seconds
Started Jul 27 05:54:08 PM PDT 24
Finished Jul 27 05:54:25 PM PDT 24
Peak memory 196088 kb
Host smart-a6455a3a-9ce7-4b0e-81cc-88b378d34279
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120326557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3120326557
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2094735213
Short name T224
Test name
Test status
Simulation time 247005013 ps
CPU time 0.91 seconds
Started Jul 27 05:54:22 PM PDT 24
Finished Jul 27 05:54:23 PM PDT 24
Peak memory 197680 kb
Host smart-59f6b85e-c4e6-4ae6-a4dd-1e0e4e487ee8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094735213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2094735213
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.313572239
Short name T262
Test name
Test status
Simulation time 191268364 ps
CPU time 0.96 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:11 PM PDT 24
Peak memory 197272 kb
Host smart-a5b55a0f-dd13-426f-bdf0-eeec7e22fe13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313572239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.313572239
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3332317148
Short name T436
Test name
Test status
Simulation time 380252014 ps
CPU time 3.21 seconds
Started Jul 27 05:54:12 PM PDT 24
Finished Jul 27 05:54:16 PM PDT 24
Peak memory 197036 kb
Host smart-a7ebfc83-81ea-4cc8-bab7-ca8e0b0f1563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332317148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3332317148
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3886423040
Short name T155
Test name
Test status
Simulation time 74882105 ps
CPU time 1.4 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:11 PM PDT 24
Peak memory 197592 kb
Host smart-275dcf8c-9093-4e77-89d2-9d4a86ad887a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886423040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3886423040
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2051132421
Short name T16
Test name
Test status
Simulation time 21055153 ps
CPU time 0.88 seconds
Started Jul 27 05:54:16 PM PDT 24
Finished Jul 27 05:54:17 PM PDT 24
Peak memory 196896 kb
Host smart-6de3540f-a01e-44bd-98cb-5b37e8c295e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051132421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2051132421
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2747151969
Short name T617
Test name
Test status
Simulation time 373141170 ps
CPU time 5.71 seconds
Started Jul 27 05:54:10 PM PDT 24
Finished Jul 27 05:54:16 PM PDT 24
Peak memory 198492 kb
Host smart-92d53ecd-3978-4b3b-b19e-a12623a59784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747151969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2747151969
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1278462707
Short name T408
Test name
Test status
Simulation time 201442630 ps
CPU time 1.07 seconds
Started Jul 27 05:54:17 PM PDT 24
Finished Jul 27 05:54:18 PM PDT 24
Peak memory 196808 kb
Host smart-d5146b69-6d2f-402d-938b-842d6428f05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278462707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1278462707
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1034917715
Short name T198
Test name
Test status
Simulation time 184709942 ps
CPU time 1.05 seconds
Started Jul 27 05:54:15 PM PDT 24
Finished Jul 27 05:54:16 PM PDT 24
Peak memory 196252 kb
Host smart-6ba97bd0-4a47-4fdb-8e88-34f5f6010eed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034917715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1034917715
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3401375709
Short name T677
Test name
Test status
Simulation time 73451867217 ps
CPU time 212.3 seconds
Started Jul 27 05:54:21 PM PDT 24
Finished Jul 27 05:57:53 PM PDT 24
Peak memory 198604 kb
Host smart-4d6f7ac1-5f1d-4dea-9257-952a8d9ce03a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401375709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3401375709
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2259016229
Short name T283
Test name
Test status
Simulation time 23889443 ps
CPU time 0.59 seconds
Started Jul 27 05:54:26 PM PDT 24
Finished Jul 27 05:54:27 PM PDT 24
Peak memory 195124 kb
Host smart-28a34602-65f0-4597-8a8f-e3cfafc61a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259016229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2259016229
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.631602460
Short name T710
Test name
Test status
Simulation time 24271037 ps
CPU time 0.77 seconds
Started Jul 27 05:54:16 PM PDT 24
Finished Jul 27 05:54:17 PM PDT 24
Peak memory 195692 kb
Host smart-96a20b78-d1aa-415a-9495-a8feeb053866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631602460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.631602460
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3694124377
Short name T279
Test name
Test status
Simulation time 500680630 ps
CPU time 17.93 seconds
Started Jul 27 05:54:25 PM PDT 24
Finished Jul 27 05:54:43 PM PDT 24
Peak memory 198416 kb
Host smart-ec70b130-aaec-4232-8951-5fd21a4c4feb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694124377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3694124377
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2049144000
Short name T20
Test name
Test status
Simulation time 25794138 ps
CPU time 0.66 seconds
Started Jul 27 05:54:28 PM PDT 24
Finished Jul 27 05:54:28 PM PDT 24
Peak memory 194920 kb
Host smart-03aaff61-de0f-425a-8503-764ea9e00896
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049144000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2049144000
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1262859736
Short name T263
Test name
Test status
Simulation time 120315160 ps
CPU time 0.85 seconds
Started Jul 27 05:54:17 PM PDT 24
Finished Jul 27 05:54:18 PM PDT 24
Peak memory 196868 kb
Host smart-a2574dda-fefc-47eb-9203-3df2cee25566
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262859736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1262859736
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2077954294
Short name T174
Test name
Test status
Simulation time 51710835 ps
CPU time 1.96 seconds
Started Jul 27 05:54:25 PM PDT 24
Finished Jul 27 05:54:27 PM PDT 24
Peak memory 198648 kb
Host smart-375d73a7-ea1b-495f-9c84-ee01c78e727a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077954294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2077954294
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2607598461
Short name T682
Test name
Test status
Simulation time 618919573 ps
CPU time 2.14 seconds
Started Jul 27 05:54:18 PM PDT 24
Finished Jul 27 05:54:20 PM PDT 24
Peak memory 196756 kb
Host smart-f4859aaf-bf75-4d0a-94a5-863352fa16a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607598461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2607598461
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1315961743
Short name T578
Test name
Test status
Simulation time 76656633 ps
CPU time 1.35 seconds
Started Jul 27 05:54:19 PM PDT 24
Finished Jul 27 05:54:21 PM PDT 24
Peak memory 197556 kb
Host smart-5b70b467-6b1f-4413-a249-1eae23e80919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315961743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1315961743
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1774431951
Short name T629
Test name
Test status
Simulation time 151891525 ps
CPU time 1.03 seconds
Started Jul 27 05:54:17 PM PDT 24
Finished Jul 27 05:54:18 PM PDT 24
Peak memory 197144 kb
Host smart-b106aa97-7443-4f10-950f-1a32ae182ccb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774431951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1774431951
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.837099617
Short name T284
Test name
Test status
Simulation time 1516447752 ps
CPU time 4.66 seconds
Started Jul 27 05:54:27 PM PDT 24
Finished Jul 27 05:54:31 PM PDT 24
Peak memory 198476 kb
Host smart-58b4e9b8-ef13-4a5f-93f3-fe3753715655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837099617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.837099617
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2321311292
Short name T481
Test name
Test status
Simulation time 285067411 ps
CPU time 1.44 seconds
Started Jul 27 05:54:17 PM PDT 24
Finished Jul 27 05:54:18 PM PDT 24
Peak memory 197268 kb
Host smart-b2c52f21-a8da-4032-8294-227295e2d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321311292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2321311292
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2966621811
Short name T177
Test name
Test status
Simulation time 169708084 ps
CPU time 1.04 seconds
Started Jul 27 05:54:17 PM PDT 24
Finished Jul 27 05:54:18 PM PDT 24
Peak memory 196372 kb
Host smart-5f613fec-495a-4fc5-a48c-e343ac96161d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966621811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2966621811
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3668067557
Short name T394
Test name
Test status
Simulation time 27582485100 ps
CPU time 119.08 seconds
Started Jul 27 05:54:26 PM PDT 24
Finished Jul 27 05:56:25 PM PDT 24
Peak memory 198620 kb
Host smart-28661713-fca6-4b8c-8372-d3891e1dcad4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668067557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3668067557
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1591682356
Short name T633
Test name
Test status
Simulation time 143937050775 ps
CPU time 859.1 seconds
Started Jul 27 05:54:26 PM PDT 24
Finished Jul 27 06:08:45 PM PDT 24
Peak memory 198740 kb
Host smart-6e64c1a9-947b-413d-99d2-b524016e75c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1591682356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1591682356
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.368835620
Short name T467
Test name
Test status
Simulation time 14249490 ps
CPU time 0.58 seconds
Started Jul 27 05:54:24 PM PDT 24
Finished Jul 27 05:54:24 PM PDT 24
Peak memory 194468 kb
Host smart-91f6e608-f6c0-47a5-9514-9cc46b7ed6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368835620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.368835620
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1421293179
Short name T703
Test name
Test status
Simulation time 22120180 ps
CPU time 0.66 seconds
Started Jul 27 05:54:25 PM PDT 24
Finished Jul 27 05:54:26 PM PDT 24
Peak memory 195204 kb
Host smart-8ffeeff0-4ecd-4f3e-9a81-3a9209f6886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421293179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1421293179
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3167792381
Short name T688
Test name
Test status
Simulation time 1554787708 ps
CPU time 19.3 seconds
Started Jul 27 05:54:27 PM PDT 24
Finished Jul 27 05:54:46 PM PDT 24
Peak memory 198532 kb
Host smart-c9efe152-0209-440d-a0b5-ab21f2e17f94
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167792381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3167792381
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1262704581
Short name T674
Test name
Test status
Simulation time 160250491 ps
CPU time 0.83 seconds
Started Jul 27 05:54:27 PM PDT 24
Finished Jul 27 05:54:28 PM PDT 24
Peak memory 196976 kb
Host smart-b8a1fc43-c069-4fc7-9f17-9194d2309df4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262704581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1262704581
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.4053165436
Short name T493
Test name
Test status
Simulation time 112861451 ps
CPU time 0.77 seconds
Started Jul 27 05:54:25 PM PDT 24
Finished Jul 27 05:54:26 PM PDT 24
Peak memory 195852 kb
Host smart-8302fedb-672e-448b-8e7f-df2fe61c45ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053165436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.4053165436
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.595006828
Short name T350
Test name
Test status
Simulation time 44287800 ps
CPU time 1.79 seconds
Started Jul 27 05:54:29 PM PDT 24
Finished Jul 27 05:54:31 PM PDT 24
Peak memory 198516 kb
Host smart-66326079-8ad9-464c-8894-e14c96ebfabc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595006828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.595006828
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.32095672
Short name T173
Test name
Test status
Simulation time 82940069 ps
CPU time 1.98 seconds
Started Jul 27 05:54:29 PM PDT 24
Finished Jul 27 05:54:31 PM PDT 24
Peak memory 197284 kb
Host smart-22ed9d13-3108-4401-9cf6-526605e65487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32095672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.32095672
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1001541236
Short name T637
Test name
Test status
Simulation time 220892671 ps
CPU time 1.33 seconds
Started Jul 27 05:54:25 PM PDT 24
Finished Jul 27 05:54:27 PM PDT 24
Peak memory 197520 kb
Host smart-16228b3d-ff1e-4c7f-82d9-d255ecf7f77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001541236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1001541236
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.413595758
Short name T320
Test name
Test status
Simulation time 130573138 ps
CPU time 1.38 seconds
Started Jul 27 05:54:26 PM PDT 24
Finished Jul 27 05:54:27 PM PDT 24
Peak memory 197572 kb
Host smart-8b8b1c17-af3c-463b-9c03-1ea1b2e197ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413595758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.413595758
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1736582866
Short name T146
Test name
Test status
Simulation time 96520469 ps
CPU time 4.67 seconds
Started Jul 27 05:54:25 PM PDT 24
Finished Jul 27 05:54:30 PM PDT 24
Peak memory 198548 kb
Host smart-0bedc077-d63c-4d29-ba1b-837dd304960f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736582866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1736582866
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2949085741
Short name T588
Test name
Test status
Simulation time 185895947 ps
CPU time 1.27 seconds
Started Jul 27 05:54:26 PM PDT 24
Finished Jul 27 05:54:27 PM PDT 24
Peak memory 197344 kb
Host smart-f9cbddd3-f5e9-471d-af2a-b8caac223bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949085741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2949085741
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3741055976
Short name T229
Test name
Test status
Simulation time 258048038 ps
CPU time 1.22 seconds
Started Jul 27 05:54:25 PM PDT 24
Finished Jul 27 05:54:26 PM PDT 24
Peak memory 196060 kb
Host smart-ccd82a16-a31f-44aa-96a9-f22a1e64876f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741055976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3741055976
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2749726724
Short name T479
Test name
Test status
Simulation time 13149841240 ps
CPU time 151.78 seconds
Started Jul 27 05:54:24 PM PDT 24
Finished Jul 27 05:56:56 PM PDT 24
Peak memory 198604 kb
Host smart-3ee09979-f9d8-40e2-805e-567e9b7b0420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749726724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2749726724
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3620427192
Short name T54
Test name
Test status
Simulation time 129367249409 ps
CPU time 719.98 seconds
Started Jul 27 05:54:25 PM PDT 24
Finished Jul 27 06:06:25 PM PDT 24
Peak memory 198764 kb
Host smart-e9f9ec09-cd2f-47a1-a696-b5a2410f812f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3620427192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3620427192
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1208910328
Short name T150
Test name
Test status
Simulation time 19961182 ps
CPU time 0.56 seconds
Started Jul 27 05:52:25 PM PDT 24
Finished Jul 27 05:52:26 PM PDT 24
Peak memory 194416 kb
Host smart-666a61c5-c2ea-4a37-93b2-79ed0f06446a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208910328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1208910328
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2899615428
Short name T598
Test name
Test status
Simulation time 45088287 ps
CPU time 0.92 seconds
Started Jul 27 05:52:22 PM PDT 24
Finished Jul 27 05:52:23 PM PDT 24
Peak memory 197032 kb
Host smart-525ffb08-80d4-4193-bc71-ad3c1bd403c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899615428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2899615428
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1700121607
Short name T639
Test name
Test status
Simulation time 1338453930 ps
CPU time 22.07 seconds
Started Jul 27 05:52:24 PM PDT 24
Finished Jul 27 05:52:47 PM PDT 24
Peak memory 197372 kb
Host smart-a750b6aa-fd08-4ccb-9b95-5e24f5ee5533
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700121607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1700121607
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1617023122
Short name T636
Test name
Test status
Simulation time 317285430 ps
CPU time 0.96 seconds
Started Jul 27 05:52:23 PM PDT 24
Finished Jul 27 05:52:24 PM PDT 24
Peak memory 196952 kb
Host smart-e20fc860-1f58-4a09-a3ef-5ae1a3c16799
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617023122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1617023122
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.307848405
Short name T642
Test name
Test status
Simulation time 40070257 ps
CPU time 1.12 seconds
Started Jul 27 05:52:25 PM PDT 24
Finished Jul 27 05:52:27 PM PDT 24
Peak memory 196320 kb
Host smart-4df4a741-b8cd-48e9-abb1-5781eda9b1b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307848405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.307848405
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2184822223
Short name T615
Test name
Test status
Simulation time 67522981 ps
CPU time 2.95 seconds
Started Jul 27 05:52:25 PM PDT 24
Finished Jul 27 05:52:28 PM PDT 24
Peak memory 198552 kb
Host smart-2f61e273-5f26-45ac-b3f2-6684bf7d88a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184822223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2184822223
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1768623717
Short name T542
Test name
Test status
Simulation time 507883857 ps
CPU time 2.82 seconds
Started Jul 27 05:52:24 PM PDT 24
Finished Jul 27 05:52:27 PM PDT 24
Peak memory 197552 kb
Host smart-25599970-04f2-4329-a8af-78da523e797d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768623717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1768623717
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2609153944
Short name T377
Test name
Test status
Simulation time 25793029 ps
CPU time 0.72 seconds
Started Jul 27 05:52:17 PM PDT 24
Finished Jul 27 05:52:18 PM PDT 24
Peak memory 195816 kb
Host smart-e5c1fc82-80cb-4bf9-bfa3-4f53036d02b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609153944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2609153944
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.391251623
Short name T652
Test name
Test status
Simulation time 38753917 ps
CPU time 1.32 seconds
Started Jul 27 05:52:23 PM PDT 24
Finished Jul 27 05:52:25 PM PDT 24
Peak memory 197592 kb
Host smart-6709e9b0-b4a6-4a09-bec6-f30ec53f8900
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391251623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.391251623
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.939583456
Short name T123
Test name
Test status
Simulation time 874834648 ps
CPU time 2.92 seconds
Started Jul 27 05:52:24 PM PDT 24
Finished Jul 27 05:52:27 PM PDT 24
Peak memory 198232 kb
Host smart-d6a62daf-04e6-4257-abc7-cfd4bde2060a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939583456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.939583456
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.440101380
Short name T195
Test name
Test status
Simulation time 67177834 ps
CPU time 1.3 seconds
Started Jul 27 05:52:17 PM PDT 24
Finished Jul 27 05:52:19 PM PDT 24
Peak memory 197312 kb
Host smart-b5a0be72-c6ca-4365-8926-162f7594c273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440101380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.440101380
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.451663109
Short name T220
Test name
Test status
Simulation time 170290291 ps
CPU time 0.88 seconds
Started Jul 27 05:52:18 PM PDT 24
Finished Jul 27 05:52:19 PM PDT 24
Peak memory 195748 kb
Host smart-925c9da3-8c1a-4744-ae17-5d693d55825d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451663109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.451663109
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2832427387
Short name T628
Test name
Test status
Simulation time 21437226322 ps
CPU time 153.27 seconds
Started Jul 27 05:52:25 PM PDT 24
Finished Jul 27 05:54:58 PM PDT 24
Peak memory 198596 kb
Host smart-ef6cbf22-04c0-43ef-806c-4378bb8ce7bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832427387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2832427387
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2438067640
Short name T106
Test name
Test status
Simulation time 48455873 ps
CPU time 0.56 seconds
Started Jul 27 05:52:22 PM PDT 24
Finished Jul 27 05:52:23 PM PDT 24
Peak memory 195104 kb
Host smart-68e3b019-093b-49b1-892f-488aeb20706a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438067640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2438067640
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.4073106898
Short name T568
Test name
Test status
Simulation time 186939642 ps
CPU time 0.9 seconds
Started Jul 27 05:52:23 PM PDT 24
Finished Jul 27 05:52:24 PM PDT 24
Peak memory 196916 kb
Host smart-ec82a1b6-d2f2-4b90-91b6-572041b3f387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073106898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.4073106898
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.234717332
Short name T205
Test name
Test status
Simulation time 1899015682 ps
CPU time 25.87 seconds
Started Jul 27 05:52:25 PM PDT 24
Finished Jul 27 05:52:51 PM PDT 24
Peak memory 197452 kb
Host smart-d780794a-96db-40e1-9923-f0f1d40548be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234717332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.234717332
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.335251006
Short name T302
Test name
Test status
Simulation time 227363742 ps
CPU time 0.79 seconds
Started Jul 27 05:52:23 PM PDT 24
Finished Jul 27 05:52:24 PM PDT 24
Peak memory 196360 kb
Host smart-a6b6c23b-82b9-4793-98ff-cf3a69b56f96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335251006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.335251006
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2717801055
Short name T389
Test name
Test status
Simulation time 124156781 ps
CPU time 0.82 seconds
Started Jul 27 05:52:26 PM PDT 24
Finished Jul 27 05:52:27 PM PDT 24
Peak memory 196744 kb
Host smart-b36c24e9-bc61-4b38-b58f-ad4ab5330b10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717801055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2717801055
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3037380930
Short name T575
Test name
Test status
Simulation time 68790787 ps
CPU time 2.67 seconds
Started Jul 27 05:52:27 PM PDT 24
Finished Jul 27 05:52:30 PM PDT 24
Peak memory 198636 kb
Host smart-59851442-db64-4bf4-a87b-116327cb22c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037380930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3037380930
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3476187165
Short name T234
Test name
Test status
Simulation time 378820375 ps
CPU time 3 seconds
Started Jul 27 05:52:23 PM PDT 24
Finished Jul 27 05:52:26 PM PDT 24
Peak memory 196328 kb
Host smart-c77269eb-41dc-4cc0-839c-32bf6f5f2b49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476187165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3476187165
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.748968601
Short name T523
Test name
Test status
Simulation time 24239420 ps
CPU time 0.95 seconds
Started Jul 27 05:52:22 PM PDT 24
Finished Jul 27 05:52:23 PM PDT 24
Peak memory 196468 kb
Host smart-41242b0b-2ef7-4145-bef1-ca6126c03f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748968601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.748968601
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3190762141
Short name T115
Test name
Test status
Simulation time 24265006 ps
CPU time 0.9 seconds
Started Jul 27 05:52:26 PM PDT 24
Finished Jul 27 05:52:27 PM PDT 24
Peak memory 197084 kb
Host smart-64230ada-1745-4ab1-811d-d96e8a0f52df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190762141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3190762141
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1304908640
Short name T380
Test name
Test status
Simulation time 114314481 ps
CPU time 2.02 seconds
Started Jul 27 05:52:23 PM PDT 24
Finished Jul 27 05:52:25 PM PDT 24
Peak memory 198496 kb
Host smart-8f45b522-23e2-42dd-94e4-839a11b69449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304908640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1304908640
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3523757704
Short name T207
Test name
Test status
Simulation time 450189380 ps
CPU time 1.07 seconds
Started Jul 27 05:52:25 PM PDT 24
Finished Jul 27 05:52:26 PM PDT 24
Peak memory 196812 kb
Host smart-6d465d68-e3d8-4ef5-aa96-0dc17c433835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523757704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3523757704
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4064106086
Short name T590
Test name
Test status
Simulation time 39216604 ps
CPU time 1.17 seconds
Started Jul 27 05:52:25 PM PDT 24
Finished Jul 27 05:52:26 PM PDT 24
Peak memory 196080 kb
Host smart-19242089-5108-4713-922c-f51229e79a51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064106086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4064106086
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2626806315
Short name T373
Test name
Test status
Simulation time 32113080540 ps
CPU time 208.12 seconds
Started Jul 27 05:52:24 PM PDT 24
Finished Jul 27 05:55:53 PM PDT 24
Peak memory 198624 kb
Host smart-11a9ceca-4168-4ab5-8248-92867281dd45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626806315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2626806315
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2127918129
Short name T15
Test name
Test status
Simulation time 17961906 ps
CPU time 0.55 seconds
Started Jul 27 05:52:30 PM PDT 24
Finished Jul 27 05:52:30 PM PDT 24
Peak memory 194424 kb
Host smart-bf2f1755-080d-4f40-945b-8ddbf16d83b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127918129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2127918129
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1407869852
Short name T605
Test name
Test status
Simulation time 96863327 ps
CPU time 0.86 seconds
Started Jul 27 05:52:34 PM PDT 24
Finished Jul 27 05:52:35 PM PDT 24
Peak memory 195876 kb
Host smart-8120da49-0c1e-4653-9a83-63ab40193f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407869852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1407869852
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.587345325
Short name T618
Test name
Test status
Simulation time 433105829 ps
CPU time 5.68 seconds
Started Jul 27 05:52:32 PM PDT 24
Finished Jul 27 05:52:38 PM PDT 24
Peak memory 196652 kb
Host smart-270109cc-4691-4f08-b074-ee9f4be75d9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587345325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.587345325
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.749945582
Short name T685
Test name
Test status
Simulation time 170990013 ps
CPU time 0.99 seconds
Started Jul 27 05:52:33 PM PDT 24
Finished Jul 27 05:52:35 PM PDT 24
Peak memory 196860 kb
Host smart-eb9241f0-286b-41e5-bdf6-c0d5675e0147
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749945582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.749945582
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1472946745
Short name T622
Test name
Test status
Simulation time 19446533 ps
CPU time 0.71 seconds
Started Jul 27 05:52:30 PM PDT 24
Finished Jul 27 05:52:31 PM PDT 24
Peak memory 194836 kb
Host smart-ca838aaf-2089-4c98-b9d5-5609d4ab1524
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472946745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1472946745
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1777771674
Short name T103
Test name
Test status
Simulation time 340031415 ps
CPU time 3.62 seconds
Started Jul 27 05:52:30 PM PDT 24
Finished Jul 27 05:52:34 PM PDT 24
Peak memory 198672 kb
Host smart-0d104197-1e5b-498a-9a19-ba9de99e0282
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777771674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1777771674
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3164913076
Short name T654
Test name
Test status
Simulation time 537620873 ps
CPU time 2.52 seconds
Started Jul 27 05:52:31 PM PDT 24
Finished Jul 27 05:52:34 PM PDT 24
Peak memory 196372 kb
Host smart-f7ef4f70-c749-49a5-9eb6-4799904f3794
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164913076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3164913076
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1546505939
Short name T640
Test name
Test status
Simulation time 54816546 ps
CPU time 1.26 seconds
Started Jul 27 05:52:31 PM PDT 24
Finished Jul 27 05:52:32 PM PDT 24
Peak memory 197524 kb
Host smart-de12fd01-b38d-45ce-b0c4-915852c7c1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546505939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1546505939
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.404971795
Short name T405
Test name
Test status
Simulation time 100669796 ps
CPU time 0.75 seconds
Started Jul 27 05:52:30 PM PDT 24
Finished Jul 27 05:52:31 PM PDT 24
Peak memory 196588 kb
Host smart-37d2eacb-f4c1-4e0e-84ee-df453a4b6131
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404971795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.404971795
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3061439649
Short name T671
Test name
Test status
Simulation time 323744274 ps
CPU time 4.15 seconds
Started Jul 27 05:52:33 PM PDT 24
Finished Jul 27 05:52:37 PM PDT 24
Peak memory 198520 kb
Host smart-e5775c89-cc04-4a76-b7a3-560d20651ee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061439649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3061439649
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.807565652
Short name T270
Test name
Test status
Simulation time 103051579 ps
CPU time 1.23 seconds
Started Jul 27 05:52:30 PM PDT 24
Finished Jul 27 05:52:32 PM PDT 24
Peak memory 196388 kb
Host smart-b10a1708-b363-458f-9e7b-da91cc784958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807565652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.807565652
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1751236478
Short name T345
Test name
Test status
Simulation time 212377753 ps
CPU time 1.01 seconds
Started Jul 27 05:52:30 PM PDT 24
Finished Jul 27 05:52:32 PM PDT 24
Peak memory 196168 kb
Host smart-3e958811-af64-4c05-8622-6ca196d4d913
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751236478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1751236478
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1127526655
Short name T305
Test name
Test status
Simulation time 25981099550 ps
CPU time 178.54 seconds
Started Jul 27 05:52:29 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 198636 kb
Host smart-e3857c60-ec43-41b5-be51-473544a06ff1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127526655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1127526655
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2893906225
Short name T580
Test name
Test status
Simulation time 59927591 ps
CPU time 0.57 seconds
Started Jul 27 05:52:39 PM PDT 24
Finished Jul 27 05:52:40 PM PDT 24
Peak memory 194420 kb
Host smart-76b79fbe-32dc-4584-abb6-69696de9c3a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893906225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2893906225
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1014153714
Short name T490
Test name
Test status
Simulation time 17263175 ps
CPU time 0.7 seconds
Started Jul 27 05:52:33 PM PDT 24
Finished Jul 27 05:52:34 PM PDT 24
Peak memory 194636 kb
Host smart-211fca96-06f0-4833-ae5b-2a2fefe5e991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014153714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1014153714
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3123473774
Short name T638
Test name
Test status
Simulation time 185770521 ps
CPU time 6.31 seconds
Started Jul 27 05:52:39 PM PDT 24
Finished Jul 27 05:52:46 PM PDT 24
Peak memory 197444 kb
Host smart-47dac4d6-8e0e-499a-b5d5-a4a6cfd254ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123473774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3123473774
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3936761843
Short name T349
Test name
Test status
Simulation time 274797572 ps
CPU time 0.91 seconds
Started Jul 27 05:52:39 PM PDT 24
Finished Jul 27 05:52:40 PM PDT 24
Peak memory 196592 kb
Host smart-789043a7-fc1f-45d0-a147-266393d5d5d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936761843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3936761843
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2301664191
Short name T355
Test name
Test status
Simulation time 133733922 ps
CPU time 1.08 seconds
Started Jul 27 05:52:32 PM PDT 24
Finished Jul 27 05:52:33 PM PDT 24
Peak memory 196624 kb
Host smart-a467c042-683b-4763-89dd-8ed1edd44936
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301664191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2301664191
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2783349758
Short name T147
Test name
Test status
Simulation time 136748850 ps
CPU time 1.53 seconds
Started Jul 27 05:52:31 PM PDT 24
Finished Jul 27 05:52:33 PM PDT 24
Peak memory 197248 kb
Host smart-c0a718f5-00b4-4ae5-8e0c-32224e347068
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783349758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2783349758
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3164001631
Short name T524
Test name
Test status
Simulation time 239209124 ps
CPU time 3.7 seconds
Started Jul 27 05:52:33 PM PDT 24
Finished Jul 27 05:52:36 PM PDT 24
Peak memory 197800 kb
Host smart-d2e7feec-c6c6-4de6-acbb-220855955e72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164001631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3164001631
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.233621650
Short name T100
Test name
Test status
Simulation time 575936058 ps
CPU time 0.94 seconds
Started Jul 27 05:52:32 PM PDT 24
Finished Jul 27 05:52:33 PM PDT 24
Peak memory 196512 kb
Host smart-7cabb74d-341f-49dc-9288-216496c07824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233621650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.233621650
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1124698868
Short name T330
Test name
Test status
Simulation time 136174601 ps
CPU time 1.07 seconds
Started Jul 27 05:52:34 PM PDT 24
Finished Jul 27 05:52:35 PM PDT 24
Peak memory 197168 kb
Host smart-7173acc7-ad66-4963-a089-85f977721e53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124698868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1124698868
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1637264041
Short name T540
Test name
Test status
Simulation time 5445915109 ps
CPU time 5.24 seconds
Started Jul 27 05:52:38 PM PDT 24
Finished Jul 27 05:52:44 PM PDT 24
Peak memory 198572 kb
Host smart-9604218f-2ebf-46ee-8ca6-da63f6e01051
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637264041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1637264041
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.8552193
Short name T194
Test name
Test status
Simulation time 390599201 ps
CPU time 1.24 seconds
Started Jul 27 05:52:29 PM PDT 24
Finished Jul 27 05:52:30 PM PDT 24
Peak memory 196280 kb
Host smart-194010c0-3cb9-433c-998b-17be5e8783cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8552193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.8552193
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.343899288
Short name T400
Test name
Test status
Simulation time 84792376 ps
CPU time 1.27 seconds
Started Jul 27 05:52:31 PM PDT 24
Finished Jul 27 05:52:33 PM PDT 24
Peak memory 197516 kb
Host smart-d2cdaf83-e789-4a9a-9dfb-59b98bbe2271
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343899288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.343899288
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2878566113
Short name T7
Test name
Test status
Simulation time 9342448256 ps
CPU time 111.16 seconds
Started Jul 27 05:52:42 PM PDT 24
Finished Jul 27 05:54:34 PM PDT 24
Peak memory 198604 kb
Host smart-b835f69e-42a0-42f7-8735-c20301d85edc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878566113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2878566113
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3703617989
Short name T66
Test name
Test status
Simulation time 333514668146 ps
CPU time 2353.1 seconds
Started Jul 27 05:52:38 PM PDT 24
Finished Jul 27 06:31:52 PM PDT 24
Peak memory 198752 kb
Host smart-9f379501-9de8-4e4f-aee3-a7c410cccd7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3703617989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3703617989
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2167878418
Short name T71
Test name
Test status
Simulation time 13200136 ps
CPU time 0.59 seconds
Started Jul 27 05:52:38 PM PDT 24
Finished Jul 27 05:52:39 PM PDT 24
Peak memory 194400 kb
Host smart-7340f9bd-95e2-4743-978c-8704e8e72196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167878418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2167878418
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3509583958
Short name T332
Test name
Test status
Simulation time 228200618 ps
CPU time 0.79 seconds
Started Jul 27 05:52:41 PM PDT 24
Finished Jul 27 05:52:42 PM PDT 24
Peak memory 195876 kb
Host smart-28cfedc9-bf49-4000-b4f3-2f00307e65d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509583958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3509583958
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1017067973
Short name T547
Test name
Test status
Simulation time 1009362388 ps
CPU time 27.6 seconds
Started Jul 27 05:52:40 PM PDT 24
Finished Jul 27 05:53:07 PM PDT 24
Peak memory 197224 kb
Host smart-1aa8618d-6932-46e7-a7fd-b0222911db94
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017067973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1017067973
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3665652573
Short name T72
Test name
Test status
Simulation time 324609776 ps
CPU time 1.08 seconds
Started Jul 27 05:52:40 PM PDT 24
Finished Jul 27 05:52:41 PM PDT 24
Peak memory 198340 kb
Host smart-a2286086-cd41-43e9-b551-cfd539fecf63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665652573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3665652573
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2410732791
Short name T520
Test name
Test status
Simulation time 92191859 ps
CPU time 1.35 seconds
Started Jul 27 05:52:38 PM PDT 24
Finished Jul 27 05:52:40 PM PDT 24
Peak memory 198500 kb
Host smart-655861d8-abac-43bc-b8cc-09713bd190fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410732791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2410732791
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.604392425
Short name T316
Test name
Test status
Simulation time 42567303 ps
CPU time 1.08 seconds
Started Jul 27 05:52:40 PM PDT 24
Finished Jul 27 05:52:41 PM PDT 24
Peak memory 197444 kb
Host smart-bc4727bd-b37f-4688-80ce-0d6405e741af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604392425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.604392425
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.4117420974
Short name T477
Test name
Test status
Simulation time 93048695 ps
CPU time 2.21 seconds
Started Jul 27 05:52:42 PM PDT 24
Finished Jul 27 05:52:45 PM PDT 24
Peak memory 197708 kb
Host smart-14dfca1b-30d9-4dfc-b34d-d19d900e381f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117420974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
4117420974
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.135729503
Short name T447
Test name
Test status
Simulation time 70745273 ps
CPU time 1.33 seconds
Started Jul 27 05:52:38 PM PDT 24
Finished Jul 27 05:52:39 PM PDT 24
Peak memory 197520 kb
Host smart-10e2d883-2cfe-408f-979f-1566dd4535d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135729503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.135729503
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.854439422
Short name T51
Test name
Test status
Simulation time 25563914 ps
CPU time 0.92 seconds
Started Jul 27 05:52:38 PM PDT 24
Finished Jul 27 05:52:39 PM PDT 24
Peak memory 196336 kb
Host smart-45b648e5-b226-4a29-8edf-502b1c7d7a18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854439422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.854439422
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1062500945
Short name T374
Test name
Test status
Simulation time 23797676 ps
CPU time 1.1 seconds
Started Jul 27 05:52:42 PM PDT 24
Finished Jul 27 05:52:44 PM PDT 24
Peak memory 198524 kb
Host smart-871a6bb4-7716-4667-8491-6a11728309f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062500945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1062500945
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2947011377
Short name T538
Test name
Test status
Simulation time 104208779 ps
CPU time 1.06 seconds
Started Jul 27 05:52:37 PM PDT 24
Finished Jul 27 05:52:38 PM PDT 24
Peak memory 195968 kb
Host smart-daa5bcdc-dd65-4a0b-b159-4937fecc2eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947011377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2947011377
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.928024780
Short name T74
Test name
Test status
Simulation time 147139032 ps
CPU time 0.96 seconds
Started Jul 27 05:52:39 PM PDT 24
Finished Jul 27 05:52:41 PM PDT 24
Peak memory 197248 kb
Host smart-f0a73f81-8d08-4194-9345-7bca6096d2d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928024780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.928024780
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.806121653
Short name T299
Test name
Test status
Simulation time 47364161291 ps
CPU time 174.42 seconds
Started Jul 27 05:52:39 PM PDT 24
Finished Jul 27 05:55:34 PM PDT 24
Peak memory 198624 kb
Host smart-fbbca5be-1bbc-407a-be66-31622ef7b00a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806121653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.806121653
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.72036525
Short name T918
Test name
Test status
Simulation time 94138241 ps
CPU time 1.18 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191744 kb
Host smart-67bdb449-2db8-40b2-90ff-b588b8424c2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=72036525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.72036525
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1184344834
Short name T913
Test name
Test status
Simulation time 216308615 ps
CPU time 1.05 seconds
Started Jul 27 05:55:17 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 191576 kb
Host smart-18d597ae-097f-433d-9d76-8f07b2e04dff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184344834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1184344834
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3382818178
Short name T898
Test name
Test status
Simulation time 53993631 ps
CPU time 1.38 seconds
Started Jul 27 05:55:24 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 191876 kb
Host smart-8f9f2a46-11c5-4359-9cd3-3ce647344ad8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3382818178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3382818178
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2299697263
Short name T901
Test name
Test status
Simulation time 65649253 ps
CPU time 0.87 seconds
Started Jul 27 05:55:17 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 196256 kb
Host smart-b5acb3ae-899a-4569-84df-871633ce47ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299697263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2299697263
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1322719195
Short name T887
Test name
Test status
Simulation time 57253050 ps
CPU time 1.48 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 191756 kb
Host smart-7bae7e02-a498-4f76-baa8-66fa82d76d1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1322719195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1322719195
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3678570208
Short name T924
Test name
Test status
Simulation time 38369273 ps
CPU time 1.02 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191764 kb
Host smart-5ce40d25-4efa-4682-b9fe-0eb7db1262a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678570208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3678570208
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3964194654
Short name T934
Test name
Test status
Simulation time 78395755 ps
CPU time 1.46 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 191880 kb
Host smart-b3f980c6-333b-48c6-9629-45f225e90fb4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3964194654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3964194654
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.863811209
Short name T935
Test name
Test status
Simulation time 96538799 ps
CPU time 1.47 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 191812 kb
Host smart-d74639e2-6f3e-4575-9eb6-4607d29fa7a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863811209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.863811209
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3161270446
Short name T895
Test name
Test status
Simulation time 128700467 ps
CPU time 1.09 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191800 kb
Host smart-fa428296-0008-4316-9474-428512cbbd56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3161270446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3161270446
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2467360876
Short name T886
Test name
Test status
Simulation time 55177495 ps
CPU time 0.97 seconds
Started Jul 27 05:55:24 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 198016 kb
Host smart-2bb17e39-480b-4276-ae18-05ced0e5a035
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467360876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2467360876
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3250776629
Short name T912
Test name
Test status
Simulation time 827938988 ps
CPU time 0.91 seconds
Started Jul 27 05:55:16 PM PDT 24
Finished Jul 27 05:55:17 PM PDT 24
Peak memory 191816 kb
Host smart-ef27e42b-31d2-43eb-9b76-044c4b13d9fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3250776629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3250776629
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3456565638
Short name T865
Test name
Test status
Simulation time 211072220 ps
CPU time 0.78 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 191648 kb
Host smart-dbdf52ce-bd16-48d3-953e-278e688e46b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456565638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3456565638
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2253516717
Short name T910
Test name
Test status
Simulation time 33711518 ps
CPU time 0.84 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 191616 kb
Host smart-771727ff-ed60-4abc-95a3-6451b9efa114
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2253516717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2253516717
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.805677126
Short name T870
Test name
Test status
Simulation time 108158707 ps
CPU time 0.94 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191708 kb
Host smart-bc90e4b2-c871-40d7-8e5f-bcd63e72ca6f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805677126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.805677126
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3256205689
Short name T940
Test name
Test status
Simulation time 68654070 ps
CPU time 1.33 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 191804 kb
Host smart-79a0b3b1-24f9-4e0e-8eb3-4737fe810c64
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3256205689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3256205689
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1880280788
Short name T847
Test name
Test status
Simulation time 76287681 ps
CPU time 1.2 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 198148 kb
Host smart-e64a4e55-bc52-439f-84b3-958e919b5c59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880280788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1880280788
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.152104126
Short name T933
Test name
Test status
Simulation time 46371520 ps
CPU time 1.32 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 191788 kb
Host smart-a1404099-2316-487b-b0b8-02973832cb41
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=152104126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.152104126
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3563466310
Short name T922
Test name
Test status
Simulation time 72165313 ps
CPU time 1.41 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 198176 kb
Host smart-391fb77a-8de0-4dfb-8505-7715859364f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563466310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3563466310
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1212575587
Short name T921
Test name
Test status
Simulation time 109585790 ps
CPU time 0.9 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 191824 kb
Host smart-3dbaea25-236d-466d-b885-5f1b0673d41a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1212575587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1212575587
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2715234736
Short name T867
Test name
Test status
Simulation time 42739879 ps
CPU time 1.18 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191784 kb
Host smart-d0f4e0b4-41d5-4a2d-9af4-6b84ed3a3082
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715234736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2715234736
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1903669461
Short name T906
Test name
Test status
Simulation time 44432212 ps
CPU time 1.27 seconds
Started Jul 27 05:55:21 PM PDT 24
Finished Jul 27 05:55:22 PM PDT 24
Peak memory 191828 kb
Host smart-dc46ca9f-9525-45fb-a071-f3ae27829872
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1903669461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1903669461
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3464908376
Short name T883
Test name
Test status
Simulation time 142973252 ps
CPU time 0.98 seconds
Started Jul 27 05:55:20 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 191796 kb
Host smart-7cd5bebe-9df6-432b-8512-962a0cb886ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464908376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3464908376
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3613624103
Short name T873
Test name
Test status
Simulation time 190701477 ps
CPU time 1.08 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191780 kb
Host smart-89774d30-b0e3-4cff-93d6-0d0c9ec36378
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3613624103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3613624103
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2885992781
Short name T900
Test name
Test status
Simulation time 180614289 ps
CPU time 1.27 seconds
Started Jul 27 05:55:22 PM PDT 24
Finished Jul 27 05:55:23 PM PDT 24
Peak memory 191768 kb
Host smart-c447dcdd-1976-4af4-9975-5d63b7cf672e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885992781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2885992781
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2432470038
Short name T931
Test name
Test status
Simulation time 108727976 ps
CPU time 1.28 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 191880 kb
Host smart-54207dda-b7df-4d44-b485-42c4c1ed4661
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2432470038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2432470038
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3732697347
Short name T841
Test name
Test status
Simulation time 112771731 ps
CPU time 0.8 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 191552 kb
Host smart-2798fd35-2094-4876-8bee-43e589c171f7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732697347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3732697347
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2656344791
Short name T851
Test name
Test status
Simulation time 42569229 ps
CPU time 1.23 seconds
Started Jul 27 05:55:20 PM PDT 24
Finished Jul 27 05:55:22 PM PDT 24
Peak memory 198104 kb
Host smart-a8bcbb84-e660-4eb1-b4e2-e8b360f2dd1e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2656344791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2656344791
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2504935919
Short name T877
Test name
Test status
Simulation time 120899306 ps
CPU time 1.09 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 191808 kb
Host smart-475d51d3-d747-4d2f-a30c-8d9579564e47
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504935919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2504935919
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3686373823
Short name T857
Test name
Test status
Simulation time 120418914 ps
CPU time 1.17 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 191844 kb
Host smart-02c054c5-be13-4110-97d3-f2fb083c1bcf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3686373823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3686373823
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2508112300
Short name T919
Test name
Test status
Simulation time 65494915 ps
CPU time 0.88 seconds
Started Jul 27 05:55:20 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 197100 kb
Host smart-7758c84f-e481-4c2a-9ef2-27a83609739a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508112300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2508112300
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1702679791
Short name T846
Test name
Test status
Simulation time 35983017 ps
CPU time 0.85 seconds
Started Jul 27 05:55:20 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 196232 kb
Host smart-ec5b46a1-9d23-47ac-8f1d-d5bd28b70387
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1702679791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1702679791
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.112132830
Short name T938
Test name
Test status
Simulation time 107190461 ps
CPU time 0.78 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191588 kb
Host smart-bd0e73ed-9509-4a0d-a602-db7b38c11270
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112132830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.112132830
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.333227272
Short name T911
Test name
Test status
Simulation time 33220339 ps
CPU time 0.81 seconds
Started Jul 27 05:55:17 PM PDT 24
Finished Jul 27 05:55:18 PM PDT 24
Peak memory 196268 kb
Host smart-1d56482c-43db-4b2b-9a79-e164268dbf23
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=333227272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.333227272
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3652804533
Short name T872
Test name
Test status
Simulation time 65128687 ps
CPU time 0.93 seconds
Started Jul 27 05:55:21 PM PDT 24
Finished Jul 27 05:55:22 PM PDT 24
Peak memory 191600 kb
Host smart-8f16753a-a328-4618-9917-f3fc3fb43e2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652804533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3652804533
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2988822767
Short name T889
Test name
Test status
Simulation time 92487391 ps
CPU time 1.16 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 198276 kb
Host smart-1b7bb982-a222-428f-92c0-df45b3f3d857
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2988822767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2988822767
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.747487988
Short name T916
Test name
Test status
Simulation time 268862104 ps
CPU time 1.45 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 191776 kb
Host smart-b228acc4-4638-4e34-8f7f-06a1e5e8637e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747487988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.747487988
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.637719599
Short name T905
Test name
Test status
Simulation time 152898046 ps
CPU time 1.52 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 191784 kb
Host smart-c8dce9a2-a975-4011-a146-7bd0c0fef5b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=637719599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.637719599
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3680321457
Short name T892
Test name
Test status
Simulation time 141178278 ps
CPU time 0.99 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 191600 kb
Host smart-ebe35aae-7839-4605-84d2-811537e80851
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680321457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3680321457
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1516488260
Short name T936
Test name
Test status
Simulation time 45448832 ps
CPU time 0.98 seconds
Started Jul 27 05:55:21 PM PDT 24
Finished Jul 27 05:55:22 PM PDT 24
Peak memory 197484 kb
Host smart-b4b42767-4e6d-4898-a089-657ae609cbc5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1516488260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1516488260
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3179039857
Short name T937
Test name
Test status
Simulation time 29100069 ps
CPU time 0.9 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 191592 kb
Host smart-91d51d61-c319-4cb2-8a5a-ad2b1fad1568
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179039857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3179039857
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4252962883
Short name T896
Test name
Test status
Simulation time 47513119 ps
CPU time 1.22 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 191852 kb
Host smart-7745e6f8-b4b3-4797-bd51-f08d6664d493
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4252962883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4252962883
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1905442505
Short name T890
Test name
Test status
Simulation time 131049629 ps
CPU time 1.29 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 191832 kb
Host smart-0f562cfa-221f-4383-95fb-46f7d669e44e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905442505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1905442505
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4260022098
Short name T848
Test name
Test status
Simulation time 454140335 ps
CPU time 0.84 seconds
Started Jul 27 05:55:31 PM PDT 24
Finished Jul 27 05:55:32 PM PDT 24
Peak memory 191612 kb
Host smart-b3b2fbd2-9daa-4a71-a3b5-e15d0bac34e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4260022098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4260022098
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3305136972
Short name T876
Test name
Test status
Simulation time 45590834 ps
CPU time 1 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 191588 kb
Host smart-23c49ec8-49aa-4593-92be-466df0e39358
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305136972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3305136972
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4183689601
Short name T859
Test name
Test status
Simulation time 137976113 ps
CPU time 0.99 seconds
Started Jul 27 05:55:31 PM PDT 24
Finished Jul 27 05:55:32 PM PDT 24
Peak memory 191788 kb
Host smart-565d37b8-6333-4404-9f8b-370a79cd735e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4183689601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4183689601
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2927478486
Short name T929
Test name
Test status
Simulation time 419536099 ps
CPU time 0.72 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 05:55:29 PM PDT 24
Peak memory 191600 kb
Host smart-5c94ab5c-ea59-4b1c-915f-b5aeb7ad15c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927478486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2927478486
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2028617254
Short name T899
Test name
Test status
Simulation time 98219428 ps
CPU time 0.89 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 196328 kb
Host smart-14de13a4-4ee9-4a4e-899f-8e234666d75f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2028617254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2028617254
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2325976388
Short name T874
Test name
Test status
Simulation time 223924959 ps
CPU time 1.08 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 191740 kb
Host smart-d6e4c14c-724c-40ca-880a-a153641d684c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325976388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2325976388
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3591645085
Short name T878
Test name
Test status
Simulation time 355622651 ps
CPU time 1.51 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 05:55:30 PM PDT 24
Peak memory 198124 kb
Host smart-8bd6cc2a-9611-4cc7-b086-d67d9965cb67
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3591645085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3591645085
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3140364586
Short name T894
Test name
Test status
Simulation time 34256328 ps
CPU time 1.09 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 198128 kb
Host smart-9e8648d0-4b30-4c90-b1c5-4ce3cc6af08c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140364586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3140364586
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2409185404
Short name T928
Test name
Test status
Simulation time 89023997 ps
CPU time 1.3 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 198116 kb
Host smart-bd369a64-4323-4536-9015-14a86a164124
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2409185404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2409185404
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2449569598
Short name T856
Test name
Test status
Simulation time 51408778 ps
CPU time 1.44 seconds
Started Jul 27 05:55:24 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 198104 kb
Host smart-7e86c358-4f8d-4a6a-9e8c-74cac979d202
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449569598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2449569598
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3139601962
Short name T882
Test name
Test status
Simulation time 63646040 ps
CPU time 1.12 seconds
Started Jul 27 05:55:30 PM PDT 24
Finished Jul 27 05:55:32 PM PDT 24
Peak memory 197344 kb
Host smart-3da624c7-8440-4ab2-ae45-0b51ecaa9d6f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3139601962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3139601962
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.193723653
Short name T909
Test name
Test status
Simulation time 91735439 ps
CPU time 1.51 seconds
Started Jul 27 05:55:24 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 191784 kb
Host smart-3714e8f0-0840-4370-93ea-8472d7ee8337
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193723653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.193723653
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3517379849
Short name T852
Test name
Test status
Simulation time 872334195 ps
CPU time 1.2 seconds
Started Jul 27 05:55:31 PM PDT 24
Finished Jul 27 05:55:33 PM PDT 24
Peak memory 198196 kb
Host smart-7e54f1fd-bbc3-4a97-9a92-b110d29c1c86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3517379849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3517379849
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2051864659
Short name T868
Test name
Test status
Simulation time 24616785 ps
CPU time 0.77 seconds
Started Jul 27 05:55:32 PM PDT 24
Finished Jul 27 05:55:33 PM PDT 24
Peak memory 196164 kb
Host smart-bc7f2bfb-276b-4933-8071-04429f84e5c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051864659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2051864659
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3365472581
Short name T907
Test name
Test status
Simulation time 80100319 ps
CPU time 1.15 seconds
Started Jul 27 05:55:30 PM PDT 24
Finished Jul 27 05:55:32 PM PDT 24
Peak memory 191776 kb
Host smart-ee98fa22-5d31-4654-a59b-b4b0264ca71a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3365472581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3365472581
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1094280034
Short name T863
Test name
Test status
Simulation time 1100594824 ps
CPU time 1.47 seconds
Started Jul 27 05:55:27 PM PDT 24
Finished Jul 27 05:55:29 PM PDT 24
Peak memory 198220 kb
Host smart-e2c0b156-1138-4ba3-a8b8-8598aa80fdb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094280034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1094280034
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1045557428
Short name T926
Test name
Test status
Simulation time 33906440 ps
CPU time 0.92 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 197448 kb
Host smart-277e813a-8413-466e-84ab-3780bbfe0d2a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1045557428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1045557428
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894588030
Short name T914
Test name
Test status
Simulation time 343209464 ps
CPU time 1.39 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 191768 kb
Host smart-1a7feff6-31f6-4f4b-b3dd-5356b86f7c93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894588030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2894588030
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.289972772
Short name T858
Test name
Test status
Simulation time 29651491 ps
CPU time 0.79 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 191600 kb
Host smart-2a98face-96a9-4762-9566-e830637e9aa4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=289972772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.289972772
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1585787332
Short name T893
Test name
Test status
Simulation time 205868647 ps
CPU time 1.4 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 191776 kb
Host smart-7290a525-ac3c-47dd-bc3a-79e1ea817899
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585787332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1585787332
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3059326146
Short name T854
Test name
Test status
Simulation time 149434646 ps
CPU time 1.13 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 191764 kb
Host smart-2f9ea68c-94e1-4a09-83d6-ab8bdaac2b7a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3059326146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3059326146
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2353318584
Short name T891
Test name
Test status
Simulation time 80732057 ps
CPU time 0.73 seconds
Started Jul 27 05:55:31 PM PDT 24
Finished Jul 27 05:55:32 PM PDT 24
Peak memory 195308 kb
Host smart-f4de7e9b-c434-4841-b83d-8937d02381f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353318584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2353318584
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3874338153
Short name T925
Test name
Test status
Simulation time 145561407 ps
CPU time 1.02 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 197340 kb
Host smart-45528ce6-9aad-468c-bbbf-321ff6765edc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3874338153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3874338153
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.324806724
Short name T927
Test name
Test status
Simulation time 134979773 ps
CPU time 1.07 seconds
Started Jul 27 05:55:32 PM PDT 24
Finished Jul 27 05:55:34 PM PDT 24
Peak memory 191828 kb
Host smart-a1041f43-4abb-4e71-a3cb-de8b18062ab1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324806724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.324806724
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3214256296
Short name T939
Test name
Test status
Simulation time 263002142 ps
CPU time 1.09 seconds
Started Jul 27 05:55:31 PM PDT 24
Finished Jul 27 05:55:32 PM PDT 24
Peak memory 191800 kb
Host smart-2f58f31e-7d2a-4736-b9c8-69d18253a1a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3214256296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3214256296
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.454606179
Short name T932
Test name
Test status
Simulation time 41546766 ps
CPU time 1.45 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 198172 kb
Host smart-d5dec3da-a01f-43b5-b091-1a0030d8221e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454606179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.454606179
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3856494049
Short name T884
Test name
Test status
Simulation time 76235194 ps
CPU time 0.73 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 191660 kb
Host smart-3d300eec-26ef-41d9-b171-8224d512c071
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3856494049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3856494049
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.918296502
Short name T860
Test name
Test status
Simulation time 142939695 ps
CPU time 1.23 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 191796 kb
Host smart-0c6b3492-8db8-4fcf-9cf1-1589e06cd2c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918296502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.918296502
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1223637636
Short name T845
Test name
Test status
Simulation time 34194151 ps
CPU time 0.76 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 05:55:29 PM PDT 24
Peak memory 191788 kb
Host smart-546199ee-a02a-4155-af8a-5ca9242c35d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1223637636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1223637636
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3326923706
Short name T881
Test name
Test status
Simulation time 77040681 ps
CPU time 1.46 seconds
Started Jul 27 05:55:29 PM PDT 24
Finished Jul 27 05:55:31 PM PDT 24
Peak memory 191816 kb
Host smart-355d48de-2b4e-4ebb-acb3-c5b4d39fd77f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326923706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3326923706
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4226825104
Short name T866
Test name
Test status
Simulation time 29120080 ps
CPU time 0.79 seconds
Started Jul 27 05:55:24 PM PDT 24
Finished Jul 27 05:55:25 PM PDT 24
Peak memory 196152 kb
Host smart-ec016ec1-ecad-4b2b-830c-6c339fbc83fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4226825104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4226825104
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.486351332
Short name T864
Test name
Test status
Simulation time 107026676 ps
CPU time 0.93 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 191776 kb
Host smart-f3228d60-591a-45fb-bd0a-9c69a0e66ffe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486351332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.486351332
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.150549995
Short name T844
Test name
Test status
Simulation time 84327438 ps
CPU time 1.28 seconds
Started Jul 27 05:55:27 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 191800 kb
Host smart-2bb6a271-9405-4801-8d6e-4d2485af5f40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=150549995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.150549995
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3011385779
Short name T923
Test name
Test status
Simulation time 48670487 ps
CPU time 0.84 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 197396 kb
Host smart-35400105-a688-4c1a-8df3-dd76a5dd5ee2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011385779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3011385779
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3179921193
Short name T849
Test name
Test status
Simulation time 248398143 ps
CPU time 0.99 seconds
Started Jul 27 05:55:30 PM PDT 24
Finished Jul 27 05:55:32 PM PDT 24
Peak memory 191776 kb
Host smart-80c5dae2-2fa4-4faa-b5f6-ce8787b31716
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3179921193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3179921193
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1554837193
Short name T888
Test name
Test status
Simulation time 216152171 ps
CPU time 0.95 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 191788 kb
Host smart-89498c85-b5f2-49cd-b41a-b52863f0dd21
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554837193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1554837193
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3824982878
Short name T917
Test name
Test status
Simulation time 74339001 ps
CPU time 1.44 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 05:55:30 PM PDT 24
Peak memory 198136 kb
Host smart-696af8cd-9eea-4c86-b5ef-50928aa044d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3824982878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3824982878
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.60872867
Short name T880
Test name
Test status
Simulation time 90671117 ps
CPU time 1.31 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 191740 kb
Host smart-4b24bf55-70b6-4a5a-bfd8-347677c3a3cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60872867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.60872867
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2181536349
Short name T853
Test name
Test status
Simulation time 196660063 ps
CPU time 1.07 seconds
Started Jul 27 05:55:28 PM PDT 24
Finished Jul 27 05:55:30 PM PDT 24
Peak memory 197308 kb
Host smart-5ffbd831-eb13-41be-8692-7cc476a5a1db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2181536349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2181536349
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1217613957
Short name T879
Test name
Test status
Simulation time 39904815 ps
CPU time 1.01 seconds
Started Jul 27 05:55:32 PM PDT 24
Finished Jul 27 05:55:33 PM PDT 24
Peak memory 191792 kb
Host smart-8442ab12-a39c-4dbd-ab4d-f2d392e389e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217613957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1217613957
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3996277741
Short name T875
Test name
Test status
Simulation time 43789628 ps
CPU time 0.98 seconds
Started Jul 27 05:55:32 PM PDT 24
Finished Jul 27 05:55:33 PM PDT 24
Peak memory 191784 kb
Host smart-01aaa12c-cc73-4a02-b7f0-a55d45611961
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3996277741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3996277741
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3880158264
Short name T862
Test name
Test status
Simulation time 73400335 ps
CPU time 1.3 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 198076 kb
Host smart-691d0e84-aa53-4aa8-8077-10b0dab938ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880158264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3880158264
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3085582705
Short name T850
Test name
Test status
Simulation time 126608565 ps
CPU time 1.38 seconds
Started Jul 27 05:55:25 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 198128 kb
Host smart-b447c716-2256-4864-8d4f-3f4b587ce651
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3085582705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3085582705
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1976037883
Short name T885
Test name
Test status
Simulation time 99617714 ps
CPU time 1.05 seconds
Started Jul 27 05:55:32 PM PDT 24
Finished Jul 27 05:55:34 PM PDT 24
Peak memory 191804 kb
Host smart-ee1bc688-a346-48ac-98ae-7d59a7f89406
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976037883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1976037883
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2875972869
Short name T855
Test name
Test status
Simulation time 245772053 ps
CPU time 1.19 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 198188 kb
Host smart-f7fc54ee-2672-4736-8ee7-bbef8e69342b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2875972869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2875972869
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.282932849
Short name T930
Test name
Test status
Simulation time 79747169 ps
CPU time 1.17 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 191772 kb
Host smart-451dff94-994a-4e7b-a24c-2c3b7466e068
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282932849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.282932849
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4095056337
Short name T871
Test name
Test status
Simulation time 73381476 ps
CPU time 1.22 seconds
Started Jul 27 05:55:27 PM PDT 24
Finished Jul 27 05:55:28 PM PDT 24
Peak memory 191732 kb
Host smart-d2ed679d-8ad9-484c-94d2-3629da37bf63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4095056337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4095056337
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2711495180
Short name T920
Test name
Test status
Simulation time 39422165 ps
CPU time 1.16 seconds
Started Jul 27 05:55:27 PM PDT 24
Finished Jul 27 05:55:29 PM PDT 24
Peak memory 191828 kb
Host smart-a8c0a2ff-fbb1-41df-8fbd-1480394344d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711495180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2711495180
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1258759232
Short name T843
Test name
Test status
Simulation time 193012303 ps
CPU time 1.11 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 191836 kb
Host smart-c4f85b8f-8f6d-41b1-87ba-58a087adde0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1258759232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1258759232
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3448364359
Short name T915
Test name
Test status
Simulation time 97624061 ps
CPU time 0.83 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 191524 kb
Host smart-43b5e0c8-ee9e-4cac-bbbb-38ebd4533ea6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448364359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3448364359
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2133316616
Short name T897
Test name
Test status
Simulation time 35000860 ps
CPU time 1.04 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191760 kb
Host smart-b1717788-7ffa-4650-8319-454dd75525dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2133316616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2133316616
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1151419839
Short name T869
Test name
Test status
Simulation time 109033895 ps
CPU time 0.8 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191552 kb
Host smart-7d482ac8-e543-4b20-9684-db6d1fd09395
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151419839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1151419839
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.823732954
Short name T902
Test name
Test status
Simulation time 35184471 ps
CPU time 1 seconds
Started Jul 27 05:55:19 PM PDT 24
Finished Jul 27 05:55:20 PM PDT 24
Peak memory 191808 kb
Host smart-0aeea3f4-e444-4d42-bc4f-fb34a0e60d3c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=823732954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.823732954
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1937333596
Short name T908
Test name
Test status
Simulation time 556133345 ps
CPU time 1.06 seconds
Started Jul 27 05:55:21 PM PDT 24
Finished Jul 27 05:55:22 PM PDT 24
Peak memory 191800 kb
Host smart-f788998b-fe06-41fc-b80a-233539438366
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937333596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1937333596
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1302258883
Short name T904
Test name
Test status
Simulation time 161746761 ps
CPU time 1.22 seconds
Started Jul 27 05:55:18 PM PDT 24
Finished Jul 27 05:55:19 PM PDT 24
Peak memory 191760 kb
Host smart-2d449691-7aa2-433b-b44d-f4ef65438b67
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1302258883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1302258883
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4082168000
Short name T903
Test name
Test status
Simulation time 23503205 ps
CPU time 0.77 seconds
Started Jul 27 05:55:21 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 191608 kb
Host smart-029ddff2-63bb-438d-a3fd-38dd01864aeb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082168000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4082168000
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.270029111
Short name T842
Test name
Test status
Simulation time 151142251 ps
CPU time 0.82 seconds
Started Jul 27 05:55:26 PM PDT 24
Finished Jul 27 05:55:27 PM PDT 24
Peak memory 191604 kb
Host smart-8968ffaf-23bc-4d7c-b859-69d25b15673a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=270029111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.270029111
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1623723774
Short name T861
Test name
Test status
Simulation time 128579323 ps
CPU time 1.01 seconds
Started Jul 27 05:55:23 PM PDT 24
Finished Jul 27 05:55:24 PM PDT 24
Peak memory 191776 kb
Host smart-00421ffb-48ac-4597-924a-78c469f98de0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623723774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1623723774
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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