Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4386468	1			T24	1		T25	21		T1	1719
all_pins[1]	4386468	1			T24	1		T25	21		T1	1719
all_pins[2]	4386468	1			T24	1		T25	21		T1	1719
all_pins[3]	4386468	1			T24	1		T25	21		T1	1719
all_pins[4]	4386468	1			T24	1		T25	21		T1	1719
all_pins[5]	4386468	1			T24	1		T25	21		T1	1719
all_pins[6]	4386468	1			T24	1		T25	21		T1	1719
all_pins[7]	4386468	1			T24	1		T25	21		T1	1719
all_pins[8]	4386468	1			T24	1		T25	21		T1	1719
all_pins[9]	4386468	1			T24	1		T25	21		T1	1719
all_pins[10]	4386468	1			T24	1		T25	21		T1	1719
all_pins[11]	4386468	1			T24	1		T25	21		T1	1719
all_pins[12]	4386468	1			T24	1		T25	21		T1	1719
all_pins[13]	4386468	1			T24	1		T25	21		T1	1719
all_pins[14]	4386468	1			T24	1		T25	21		T1	1719
all_pins[15]	4386468	1			T24	1		T25	21		T1	1719
all_pins[16]	4386468	1			T24	1		T25	21		T1	1719
all_pins[17]	4386468	1			T24	1		T25	21		T1	1719
all_pins[18]	4386468	1			T24	1		T25	21		T1	1719
all_pins[19]	4386468	1			T24	1		T25	21		T1	1719
all_pins[20]	4386468	1			T24	1		T25	21		T1	1719
all_pins[21]	4386468	1			T24	1		T25	21		T1	1719
all_pins[22]	4386468	1			T24	1		T25	21		T1	1719
all_pins[23]	4386468	1			T24	1		T25	21		T1	1719
all_pins[24]	4386468	1			T24	1		T25	21		T1	1719
all_pins[25]	4386468	1			T24	1		T25	21		T1	1719
all_pins[26]	4386468	1			T24	1		T25	21		T1	1719
all_pins[27]	4386468	1			T24	1		T25	21		T1	1719
all_pins[28]	4386468	1			T24	1		T25	21		T1	1719
all_pins[29]	4386468	1			T24	1		T25	21		T1	1719
all_pins[30]	4386468	1			T24	1		T25	21		T1	1719
all_pins[31]	4386468	1			T24	1		T25	21		T1	1719

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	87146985	1			T24	32		T25	672		T1	34529
values[0x1]	53219991	1			T1	20479		T12	1634		T2	168146
transitions[0x0=>0x1]	31875286	1			T1	12441		T12	962		T2	99906
transitions[0x1=>0x0]	31875134	1			T1	12441		T12	962		T2	99906

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2727177	1			T24	1		T25	21		T1	1066
all_pins[0]	values[0x1]	1659291	1			T1	653		T12	43		T2	5306
all_pins[0]	transitions[0x0=>0x1]	1027061	1			T1	443		T12	38		T2	3249
all_pins[0]	transitions[0x1=>0x0]	1031628	1			T1	333		T12	20		T2	3095
all_pins[1]	values[0x0]	2723090	1			T24	1		T25	21		T1	1007
all_pins[1]	values[0x1]	1663378	1			T1	712		T12	49		T2	5183
all_pins[1]	transitions[0x0=>0x1]	998363	1			T1	433		T12	29		T2	3184
all_pins[1]	transitions[0x1=>0x0]	994276	1			T1	374		T12	23		T2	3307
all_pins[2]	values[0x0]	2727422	1			T24	1		T25	21		T1	1151
all_pins[2]	values[0x1]	1659046	1			T1	568		T12	58		T2	5126
all_pins[2]	transitions[0x0=>0x1]	991976	1			T1	341		T12	38		T2	2945
all_pins[2]	transitions[0x1=>0x0]	996308	1			T1	485		T12	29		T2	3002
all_pins[3]	values[0x0]	2721034	1			T24	1		T25	21		T1	1133
all_pins[3]	values[0x1]	1665434	1			T1	586		T12	58		T2	5074
all_pins[3]	transitions[0x0=>0x1]	998257	1			T1	353		T12	34		T2	3167
all_pins[3]	transitions[0x1=>0x0]	991869	1			T1	335		T12	34		T2	3219
all_pins[4]	values[0x0]	2716922	1			T24	1		T25	21		T1	1051
all_pins[4]	values[0x1]	1669546	1			T1	668		T12	78		T2	4986
all_pins[4]	transitions[0x0=>0x1]	997693	1			T1	397		T12	38		T2	2954
all_pins[4]	transitions[0x1=>0x0]	993581	1			T1	315		T12	18		T2	3042
all_pins[5]	values[0x0]	2723431	1			T24	1		T25	21		T1	1000
all_pins[5]	values[0x1]	1663037	1			T1	719		T12	70		T2	5343
all_pins[5]	transitions[0x0=>0x1]	993011	1			T1	454		T12	26		T2	3377
all_pins[5]	transitions[0x1=>0x0]	999520	1			T1	403		T12	34		T2	3020
all_pins[6]	values[0x0]	2719306	1			T24	1		T25	21		T1	1022
all_pins[6]	values[0x1]	1667162	1			T1	697		T12	43		T2	5449
all_pins[6]	transitions[0x0=>0x1]	997015	1			T1	346		T12	14		T2	3222
all_pins[6]	transitions[0x1=>0x0]	992890	1			T1	368		T12	41		T2	3116
all_pins[7]	values[0x0]	2721190	1			T24	1		T25	21		T1	994
all_pins[7]	values[0x1]	1665278	1			T1	725		T12	57		T2	5137
all_pins[7]	transitions[0x0=>0x1]	994595	1			T1	414		T12	37		T2	2925
all_pins[7]	transitions[0x1=>0x0]	996479	1			T1	386		T12	23		T2	3237
all_pins[8]	values[0x0]	2718613	1			T24	1		T25	21		T1	1158
all_pins[8]	values[0x1]	1667855	1			T1	561		T12	53		T2	5598
all_pins[8]	transitions[0x0=>0x1]	996038	1			T1	312		T12	34		T2	3265
all_pins[8]	transitions[0x1=>0x0]	993461	1			T1	476		T12	38		T2	2804
all_pins[9]	values[0x0]	2725948	1			T24	1		T25	21		T1	1126
all_pins[9]	values[0x1]	1660520	1			T1	593		T12	56		T2	5384
all_pins[9]	transitions[0x0=>0x1]	993683	1			T1	391		T12	42		T2	3138
all_pins[9]	transitions[0x1=>0x0]	1001018	1			T1	359		T12	39		T2	3352
all_pins[10]	values[0x0]	2716633	1			T24	1		T25	21		T1	1044
all_pins[10]	values[0x1]	1669835	1			T1	675		T12	51		T2	5091
all_pins[10]	transitions[0x0=>0x1]	998143	1			T1	475		T12	20		T2	2936
all_pins[10]	transitions[0x1=>0x0]	988828	1			T1	393		T12	25		T2	3229
all_pins[11]	values[0x0]	2723728	1			T24	1		T25	21		T1	1179
all_pins[11]	values[0x1]	1662740	1			T1	540		T12	71		T2	5209
all_pins[11]	transitions[0x0=>0x1]	993653	1			T1	340		T12	41		T2	3171
all_pins[11]	transitions[0x1=>0x0]	1000748	1			T1	475		T12	21		T2	3053
all_pins[12]	values[0x0]	2724719	1			T24	1		T25	21		T1	1103
all_pins[12]	values[0x1]	1661749	1			T1	616		T12	50		T2	5270
all_pins[12]	transitions[0x0=>0x1]	994229	1			T1	380		T12	23		T2	3134
all_pins[12]	transitions[0x1=>0x0]	995220	1			T1	304		T12	44		T2	3073
all_pins[13]	values[0x0]	2722772	1			T24	1		T25	21		T1	1056
all_pins[13]	values[0x1]	1663696	1			T1	663		T12	55		T2	5159
all_pins[13]	transitions[0x0=>0x1]	996927	1			T1	414		T12	34		T2	3014
all_pins[13]	transitions[0x1=>0x0]	994980	1			T1	367		T12	29		T2	3125
all_pins[14]	values[0x0]	2729536	1			T24	1		T25	21		T1	1149
all_pins[14]	values[0x1]	1656932	1			T1	570		T12	50		T2	5239
all_pins[14]	transitions[0x0=>0x1]	992508	1			T1	342		T12	22		T2	3153
all_pins[14]	transitions[0x1=>0x0]	999272	1			T1	435		T12	27		T2	3073
all_pins[15]	values[0x0]	2733670	1			T24	1		T25	21		T1	1057
all_pins[15]	values[0x1]	1652798	1			T1	662		T12	32		T2	5336
all_pins[15]	transitions[0x0=>0x1]	989891	1			T1	416		T12	14		T2	3188
all_pins[15]	transitions[0x1=>0x0]	994025	1			T1	324		T12	32		T2	3091
all_pins[16]	values[0x0]	2719925	1			T24	1		T25	21		T1	1122
all_pins[16]	values[0x1]	1666543	1			T1	597		T12	52		T2	5511
all_pins[16]	transitions[0x0=>0x1]	1000519	1			T1	377		T12	45		T2	3256
all_pins[16]	transitions[0x1=>0x0]	986774	1			T1	442		T12	25		T2	3081
all_pins[17]	values[0x0]	2723493	1			T24	1		T25	21		T1	1091
all_pins[17]	values[0x1]	1662975	1			T1	628		T12	59		T2	5241
all_pins[17]	transitions[0x0=>0x1]	993860	1			T1	353		T12	35		T2	2988
all_pins[17]	transitions[0x1=>0x0]	997428	1			T1	322		T12	28		T2	3258
all_pins[18]	values[0x0]	2729856	1			T24	1		T25	21		T1	1012
all_pins[18]	values[0x1]	1656612	1			T1	707		T12	64		T2	5286
all_pins[18]	transitions[0x0=>0x1]	990381	1			T1	434		T12	39		T2	3131
all_pins[18]	transitions[0x1=>0x0]	996744	1			T1	355		T12	34		T2	3086
all_pins[19]	values[0x0]	2718806	1			T24	1		T25	21		T1	1127
all_pins[19]	values[0x1]	1667662	1			T1	592		T12	35		T2	5390
all_pins[19]	transitions[0x0=>0x1]	1001069	1			T1	321		T12	12		T2	3095
all_pins[19]	transitions[0x1=>0x0]	990019	1			T1	436		T12	41		T2	2991
all_pins[20]	values[0x0]	2720518	1			T24	1		T25	21		T1	1124
all_pins[20]	values[0x1]	1665950	1			T1	595		T12	37		T2	5334
all_pins[20]	transitions[0x0=>0x1]	997522	1			T1	420		T12	24		T2	3019
all_pins[20]	transitions[0x1=>0x0]	999234	1			T1	417		T12	22		T2	3075
all_pins[21]	values[0x0]	2720669	1			T24	1		T25	21		T1	969
all_pins[21]	values[0x1]	1665799	1			T1	750		T12	56		T2	5381
all_pins[21]	transitions[0x0=>0x1]	994115	1			T1	489		T12	31		T2	3270
all_pins[21]	transitions[0x1=>0x0]	994266	1			T1	334		T12	12		T2	3223
all_pins[22]	values[0x0]	2727463	1			T24	1		T25	21		T1	1057
all_pins[22]	values[0x1]	1659005	1			T1	662		T12	52		T2	4967
all_pins[22]	transitions[0x0=>0x1]	991327	1			T1	338		T12	35		T2	2895
all_pins[22]	transitions[0x1=>0x0]	998121	1			T1	426		T12	39		T2	3309
all_pins[23]	values[0x0]	2722560	1			T24	1		T25	21		T1	1098
all_pins[23]	values[0x1]	1663908	1			T1	621		T12	51		T2	5207
all_pins[23]	transitions[0x0=>0x1]	997099	1			T1	361		T12	39		T2	3266
all_pins[23]	transitions[0x1=>0x0]	992196	1			T1	402		T12	40		T2	3026
all_pins[24]	values[0x0]	2726701	1			T24	1		T25	21		T1	1136
all_pins[24]	values[0x1]	1659767	1			T1	583		T12	70		T2	4930
all_pins[24]	transitions[0x0=>0x1]	993652	1			T1	346		T12	48		T2	2862
all_pins[24]	transitions[0x1=>0x0]	997793	1			T1	384		T12	29		T2	3139
all_pins[25]	values[0x0]	2727318	1			T24	1		T25	21		T1	973
all_pins[25]	values[0x1]	1659150	1			T1	746		T12	50		T2	5404
all_pins[25]	transitions[0x0=>0x1]	995794	1			T1	496		T12	14		T2	3305
all_pins[25]	transitions[0x1=>0x0]	996411	1			T1	333		T12	34		T2	2831
all_pins[26]	values[0x0]	2718490	1			T24	1		T25	21		T1	1073
all_pins[26]	values[0x1]	1667978	1			T1	646		T12	34		T2	5280
all_pins[26]	transitions[0x0=>0x1]	995612	1			T1	363		T12	18		T2	3153
all_pins[26]	transitions[0x1=>0x0]	986784	1			T1	463		T12	34		T2	3277
all_pins[27]	values[0x0]	2724741	1			T24	1		T25	21		T1	1053
all_pins[27]	values[0x1]	1661727	1			T1	666		T12	34		T2	5431
all_pins[27]	transitions[0x0=>0x1]	991840	1			T1	400		T12	28		T2	3308
all_pins[27]	transitions[0x1=>0x0]	998091	1			T1	380		T12	28		T2	3157
all_pins[28]	values[0x0]	2722271	1			T24	1		T25	21		T1	1057
all_pins[28]	values[0x1]	1664197	1			T1	662		T12	53		T2	5288
all_pins[28]	transitions[0x0=>0x1]	995839	1			T1	419		T12	31		T2	3116
all_pins[28]	transitions[0x1=>0x0]	993369	1			T1	423		T12	12		T2	3259
all_pins[29]	values[0x0]	2723512	1			T24	1		T25	21		T1	1055
all_pins[29]	values[0x1]	1662956	1			T1	664		T12	53		T2	5165
all_pins[29]	transitions[0x0=>0x1]	993560	1			T1	363		T12	37		T2	3081
all_pins[29]	transitions[0x1=>0x0]	994801	1			T1	361		T12	37		T2	3204
all_pins[30]	values[0x0]	2723013	1			T24	1		T25	21		T1	1110
all_pins[30]	values[0x1]	1663455	1			T1	609		T12	35		T2	5289
all_pins[30]	transitions[0x0=>0x1]	995429	1			T1	370		T12	25		T2	3080
all_pins[30]	transitions[0x1=>0x0]	994930	1			T1	425		T12	43		T2	2956
all_pins[31]	values[0x0]	2722458	1			T24	1		T25	21		T1	1176
all_pins[31]	values[0x1]	1664010	1			T1	543		T12	25		T2	5152
all_pins[31]	transitions[0x0=>0x1]	994625	1			T1	340		T12	17		T2	3059
all_pins[31]	transitions[0x1=>0x0]	994070	1			T1	406		T12	27		T2	3196