Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[1]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[2]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[3]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[4]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[5]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[6]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[7]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[8]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[9]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[10]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[11]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[12]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[13]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[14]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[15]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[16]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[17]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[18]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[19]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[20]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[21]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[22]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[23]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[24]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[25]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[26]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[27]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[28]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[29]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[30]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[31]	14169188	1			T24	673		T25	21		T1	11404

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

268085754

1

T24

17338

T25

672

T1

104126

auto[1]

185328262

1

T24

4198

T1

260802

T11

3449

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

363836134

1

T24

16508

T25

672

T1

277325

auto[1]

89577882

1

T24

5028

T1

87603

T11

5155

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

337455700

1

T24

10945

T25

672

T1

223554

auto[1]

115958316

1

T24

10591

T1

141374

T11

5468

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5226062	1			T24	242		T25	21		T1	1579
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3908995	1			T24	25		T1	3788		T11	24
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1403636	1			T24	115		T1	1365		T11	74
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1751136	1			T24	194		T1	364		T11	105
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	482969	1			T24	27		T1	2785		T2	559
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1396390	1			T24	70		T1	1523		T11	54
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5221319	1			T24	227		T25	21		T1	1462
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3912143	1			T24	18		T1	3980		T11	18
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1406716	1			T24	84		T1	1244		T11	95
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1747857	1			T24	239		T1	343		T11	66
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	481609	1			T24	21		T1	3076		T2	576
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1399544	1			T24	84		T1	1299		T11	86
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5219170	1			T24	163		T25	21		T1	1549
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3915870	1			T24	18		T1	4007		T11	26
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1412629	1			T24	85		T1	1333		T11	92
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1745958	1			T24	288		T1	330		T11	79
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	482167	1			T24	32		T1	2768		T2	633
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1393394	1			T24	87		T1	1417		T11	64
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5216554	1			T24	223		T25	21		T1	1577
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3925699	1			T24	24		T1	3993		T11	30
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1411096	1			T24	83		T1	1300		T11	72
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1741644	1			T24	241		T1	327		T11	90
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	481655	1			T24	27		T1	2719		T2	546
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1392540	1			T24	75		T1	1488		T11	69
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5224597	1			T24	206		T25	21		T1	1607
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3913026	1			T24	18		T1	4153		T11	24
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1409928	1			T24	92		T1	1384		T11	60
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1744107	1			T24	229		T1	264		T11	83
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	481114	1			T24	39		T1	2557		T2	621
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1396416	1			T24	89		T1	1439		T11	88
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5223147	1			T24	318		T25	21		T1	1608
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3912652	1			T24	44		T1	4123		T11	19
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1414660	1			T24	89		T1	1338		T11	76
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1740753	1			T24	142		T1	288		T11	107
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	482114	1			T24	19		T1	2717		T2	631
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1395862	1			T24	61		T1	1330		T11	52
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5212440	1			T24	130		T25	21		T1	1543
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3923854	1			T24	13		T1	3676		T11	23
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1410309	1			T24	42		T1	1454		T11	82
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1746804	1			T24	353		T1	379		T11	81
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	478411	1			T24	39		T1	2991		T2	636
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1397370	1			T24	96		T1	1361		T11	90
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5222388	1			T24	188		T25	21		T1	1506
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3917828	1			T24	19		T1	3827		T11	25
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1404809	1			T24	65		T1	1454		T11	74
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1748753	1			T24	254		T1	385		T11	86
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	480668	1			T24	36		T1	2902		T2	632
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1394742	1			T24	111		T1	1330		T11	98
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5211897	1			T24	139		T25	21		T1	1543
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3919956	1			T24	12		T1	4065		T11	25
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1407510	1			T24	67		T1	1330		T11	53
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1750621	1			T24	294		T1	308		T11	104
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	482039	1			T24	44		T1	2814		T2	662
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1397165	1			T24	117		T1	1344		T11	92
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5229999	1			T24	266		T25	21		T1	1561
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3911946	1			T24	48		T1	4018		T11	28
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1409994	1			T24	70		T1	1431		T11	77
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1744707	1			T24	205		T1	298		T11	84
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	478054	1			T24	21		T1	2600		T2	703
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1394488	1			T24	63		T1	1496		T11	88
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5212844	1			T24	228		T25	21		T1	1544
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3925007	1			T24	34		T1	4003		T11	24
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1407959	1			T24	79		T1	1238		T11	92
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1747521	1			T24	236		T1	323		T11	75
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	482103	1			T24	27		T1	2857		T2	616
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1393754	1			T24	69		T1	1439		T11	84
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5217580	1			T24	210		T25	21		T1	1628
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3916332	1			T24	23		T1	4331		T11	21
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1406605	1			T24	97		T1	1429		T11	52
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1751329	1			T24	225		T1	244		T11	115
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	482099	1			T24	30		T1	2484		T2	731
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1395243	1			T24	88		T1	1288		T11	92
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5217822	1			T24	210		T25	21		T1	1563
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3923694	1			T24	21		T1	3967		T11	28
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1405426	1			T24	53		T1	1551		T11	80
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1749285	1			T24	268		T1	303		T11	98
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	483015	1			T24	35		T1	2641		T2	589
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1389946	1			T24	86		T1	1379		T11	65
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5213336	1			T24	223		T25	21		T1	1535
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3916342	1			T24	28		T1	4067		T11	25
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1405651	1			T24	105		T1	1572		T11	38
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1755454	1			T24	204		T1	289		T11	118
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	481647	1			T24	35		T1	2680		T2	725
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1396758	1			T24	78		T1	1261		T11	90
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5231241	1			T24	281		T25	21		T1	1514
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3906680	1			T24	36		T1	4039		T11	22
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1408460	1			T24	115		T1	1289		T11	90
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1742387	1			T24	162		T1	340		T11	113
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	481761	1			T24	23		T1	2757		T2	568
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1398659	1			T24	56		T1	1465		T11	78
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5217634	1			T24	220		T25	21		T1	1471
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3921448	1			T24	36		T1	3965		T11	26
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1402592	1			T24	81		T1	1315		T11	65
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1750249	1			T24	230		T1	344		T11	76
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	484159	1			T24	30		T1	3020		T2	687
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1393106	1			T24	76		T1	1289		T11	80
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5226362	1			T24	217		T25	21		T1	1539
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3915342	1			T24	24		T1	4227		T11	22
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1407905	1			T24	55		T1	1323		T11	82
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1744915	1			T24	265		T1	313		T11	72
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	482786	1			T24	32		T1	2590		T2	579
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1391878	1			T24	80		T1	1412		T11	71
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5227608	1			T24	216		T25	21		T1	1598
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3913421	1			T24	14		T1	4207		T11	31
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1399753	1			T24	112		T1	1290		T11	91
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1757956	1			T24	238		T1	313		T11	90
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	481467	1			T24	31		T1	2665		T2	672
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1388983	1			T24	62		T1	1331		T11	58
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5219059	1			T24	174		T25	21		T1	1564
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3918936	1			T24	27		T1	3958		T11	22
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1403949	1			T24	96		T1	1380		T11	96
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1749717	1			T24	273		T1	277		T11	90
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	485006	1			T24	35		T1	2936		T2	584
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1392521	1			T24	68		T1	1289		T11	93
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5227213	1			T24	242		T25	21		T1	1621
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3914219	1			T24	27		T1	3995		T11	25
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1408951	1			T24	105		T1	1397		T11	70
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1746459	1			T24	196		T1	304		T11	94
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	480963	1			T24	20		T1	2717		T2	692
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1391383	1			T24	83		T1	1370		T11	70
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5229821	1			T24	208		T25	21		T1	1568
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3914702	1			T24	26		T1	3867		T11	25
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1404705	1			T24	97		T1	1215		T11	86
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1751517	1			T24	234		T1	346		T11	80
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	483096	1			T24	30		T1	3015		T2	563
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1385347	1			T24	78		T1	1393		T11	91
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5218002	1			T24	329		T25	21		T1	1556
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3914125	1			T24	36		T1	3968		T11	23
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1402323	1			T24	74		T1	1396		T11	82
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1754297	1			T24	147		T1	330		T11	76
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	486673	1			T24	19		T1	2835		T2	627
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1393768	1			T24	68		T1	1319		T11	83
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5222877	1			T24	300		T25	21		T1	1608
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3916290	1			T24	28		T1	4024		T11	27
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1406671	1			T24	60		T1	1278		T11	86
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1747926	1			T24	210		T1	341		T11	68
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	482183	1			T24	28		T1	2761		T2	674
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1393241	1			T24	47		T1	1392		T11	91
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5224224	1			T24	259		T25	21		T1	1557
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3922497	1			T24	29		T1	4352		T11	27
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1406060	1			T24	95		T1	1406		T11	67
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1748237	1			T24	192		T1	298		T11	82
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	481235	1			T24	20		T1	2540		T2	677
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1386935	1			T24	78		T1	1251		T11	102
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5235659	1			T24	279		T25	21		T1	1519
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3910470	1			T24	29		T1	4325		T11	25
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1405216	1			T24	72		T1	1400		T11	91
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1745280	1			T24	205		T1	317		T11	90
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	483970	1			T24	21		T1	2622		T2	730
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1388593	1			T24	67		T1	1221		T11	74
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5222929	1			T24	278		T25	21		T1	1615
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3912916	1			T24	31		T1	4009		T11	21
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1406137	1			T24	87		T1	1404		T11	68
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1751426	1			T24	170		T1	340		T11	96
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	483579	1			T24	26		T1	2752		T2	599
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1392201	1			T24	81		T1	1284		T11	96
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5231420	1			T24	221		T25	21		T1	1576
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3912010	1			T24	15		T1	4030		T11	29
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1405777	1			T24	64		T1	1405		T11	85
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1751854	1			T24	289		T1	325		T11	80
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	480555	1			T24	25		T1	2650		T2	572
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1387572	1			T24	59		T1	1418		T11	80
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5231317	1			T24	316		T25	21		T1	1574
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3915299	1			T24	32		T1	4019		T11	25
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1404124	1			T24	51		T1	1207		T11	54
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1747357	1			T24	162		T1	346		T11	88
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	483799	1			T24	14		T1	2737		T2	590
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1387292	1			T24	98		T1	1521		T11	123
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5216315	1			T24	227		T25	21		T1	1565
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3925266	1			T24	20		T1	4093		T11	20
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1404247	1			T24	65		T1	1429		T11	102
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1749182	1			T24	236		T1	294		T11	76
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	484261	1			T24	38		T1	2698		T2	593
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1389917	1			T24	87		T1	1325		T11	99
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5226525	1			T24	336		T25	21		T1	1571
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3910455	1			T24	45		T1	4058		T11	22
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1406814	1			T24	100		T1	1299		T11	96
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1752162	1			T24	136		T1	338		T11	70
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	482968	1			T24	14		T1	2758		T2	693
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1390264	1			T24	42		T1	1380		T11	97
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5223911	1			T24	161		T25	21		T1	1636
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3918062	1			T24	18		T1	4432		T11	28
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1402315	1			T24	55		T1	1476		T11	60
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1748607	1			T24	312		T1	235		T11	99
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	482762	1			T24	45		T1	2326		T2	742
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1393531	1			T24	82		T1	1299		T11	80
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5226233	1			T24	258		T25	21		T1	1604
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3915954	1			T24	34		T1	4047		T11	26
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1403832	1			T24	88		T1	1548		T11	104
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1746033	1			T24	216		T1	339		T11	74
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	484816	1			T24	33		T1	2496		T2	661
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1392320	1			T24	44		T1	1370		T11	85

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal