Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[1]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[2]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[3]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[4]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[5]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[6]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[7]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[8]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[9]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[10]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[11]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[12]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[13]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[14]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[15]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[16]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[17]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[18]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[19]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[20]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[21]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[22]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[23]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[24]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[25]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[26]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[27]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[28]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[29]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[30]	14169188	1			T24	673		T25	21		T1	11404
bins_for_gpio_bits[31]	14169188	1			T24	673		T25	21		T1	11404

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

268085754

1

T24

17338

T25

672

T1

104126

auto[1]

185328262

1

T24

4198

T1

260802

T11

3449

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

268079024

1

T24

17338

T25

672

T1

104158

auto[1]

185334992

1

T24

4198

T1

260770

T11

3460

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8131565	1			T24	538		T25	21		T1	3034
bins_for_gpio_bits[0]	auto[0]	auto[1]	249092	1			T24	13		T1	274		T11	15
bins_for_gpio_bits[0]	auto[1]	auto[0]	249269	1			T24	13		T1	274		T11	15
bins_for_gpio_bits[0]	auto[1]	auto[1]	5539262	1			T24	109		T1	7822		T11	63
bins_for_gpio_bits[1]	auto[0]	auto[0]	8125539	1			T24	534		T25	21		T1	2789
bins_for_gpio_bits[1]	auto[0]	auto[1]	250181	1			T24	16		T1	261		T11	24
bins_for_gpio_bits[1]	auto[1]	auto[0]	250353	1			T24	16		T1	260		T11	24
bins_for_gpio_bits[1]	auto[1]	auto[1]	5543115	1			T24	107		T1	8094		T11	80
bins_for_gpio_bits[2]	auto[0]	auto[0]	8127314	1			T24	516		T25	21		T1	2945
bins_for_gpio_bits[2]	auto[0]	auto[1]	250214	1			T24	20		T1	270		T11	22
bins_for_gpio_bits[2]	auto[1]	auto[0]	250443	1			T24	20		T1	267		T11	22
bins_for_gpio_bits[2]	auto[1]	auto[1]	5541217	1			T24	117		T1	7922		T11	68
bins_for_gpio_bits[3]	auto[0]	auto[0]	8119445	1			T24	531		T25	21		T1	2930
bins_for_gpio_bits[3]	auto[0]	auto[1]	249641	1			T24	16		T1	275		T11	17
bins_for_gpio_bits[3]	auto[1]	auto[0]	249849	1			T24	16		T1	274		T11	18
bins_for_gpio_bits[3]	auto[1]	auto[1]	5550253	1			T24	110		T1	7925		T11	82
bins_for_gpio_bits[4]	auto[0]	auto[0]	8128997	1			T24	509		T25	21		T1	2953
bins_for_gpio_bits[4]	auto[0]	auto[1]	249424	1			T24	18		T1	304		T11	20
bins_for_gpio_bits[4]	auto[1]	auto[0]	249635	1			T24	18		T1	302		T11	20
bins_for_gpio_bits[4]	auto[1]	auto[1]	5541132	1			T24	128		T1	7845		T11	92
bins_for_gpio_bits[5]	auto[0]	auto[0]	8128542	1			T24	537		T25	21		T1	2966
bins_for_gpio_bits[5]	auto[0]	auto[1]	249825	1			T24	12		T1	268		T11	16
bins_for_gpio_bits[5]	auto[1]	auto[0]	250018	1			T24	12		T1	268		T11	16
bins_for_gpio_bits[5]	auto[1]	auto[1]	5540803	1			T24	112		T1	7902		T11	55
bins_for_gpio_bits[6]	auto[0]	auto[0]	8119079	1			T24	507		T25	21		T1	3089
bins_for_gpio_bits[6]	auto[0]	auto[1]	250259	1			T24	18		T1	288		T11	21
bins_for_gpio_bits[6]	auto[1]	auto[0]	250474	1			T24	18		T1	287		T11	21
bins_for_gpio_bits[6]	auto[1]	auto[1]	5549376	1			T24	130		T1	7740		T11	92
bins_for_gpio_bits[7]	auto[0]	auto[0]	8125902	1			T24	486		T25	21		T1	3072
bins_for_gpio_bits[7]	auto[0]	auto[1]	249823	1			T24	21		T1	274		T11	18
bins_for_gpio_bits[7]	auto[1]	auto[0]	250048	1			T24	21		T1	273		T11	18
bins_for_gpio_bits[7]	auto[1]	auto[1]	5543415	1			T24	145		T1	7785		T11	105
bins_for_gpio_bits[8]	auto[0]	auto[0]	8119866	1			T24	477		T25	21		T1	2904
bins_for_gpio_bits[8]	auto[0]	auto[1]	249971	1			T24	23		T1	279		T11	21
bins_for_gpio_bits[8]	auto[1]	auto[0]	250162	1			T24	23		T1	277		T11	21
bins_for_gpio_bits[8]	auto[1]	auto[1]	5549189	1			T24	150		T1	7944		T11	96
bins_for_gpio_bits[9]	auto[0]	auto[0]	8134954	1			T24	529		T25	21		T1	3003
bins_for_gpio_bits[9]	auto[0]	auto[1]	249572	1			T24	12		T1	289		T11	16
bins_for_gpio_bits[9]	auto[1]	auto[0]	249746	1			T24	12		T1	287		T11	16
bins_for_gpio_bits[9]	auto[1]	auto[1]	5534916	1			T24	120		T1	7825		T11	100
bins_for_gpio_bits[10]	auto[0]	auto[0]	8118955	1			T24	530		T25	21		T1	2846
bins_for_gpio_bits[10]	auto[0]	auto[1]	249115	1			T24	13		T1	260		T11	21
bins_for_gpio_bits[10]	auto[1]	auto[0]	249369	1			T24	13		T1	259		T11	21
bins_for_gpio_bits[10]	auto[1]	auto[1]	5551749	1			T24	117		T1	8039		T11	87
bins_for_gpio_bits[11]	auto[0]	auto[0]	8126038	1			T24	515		T25	21		T1	3006
bins_for_gpio_bits[11]	auto[0]	auto[1]	249287	1			T24	17		T1	296		T11	18
bins_for_gpio_bits[11]	auto[1]	auto[0]	249476	1			T24	17		T1	295		T11	18
bins_for_gpio_bits[11]	auto[1]	auto[1]	5544387	1			T24	124		T1	7807		T11	95
bins_for_gpio_bits[12]	auto[0]	auto[0]	8122834	1			T24	517		T25	21		T1	3125
bins_for_gpio_bits[12]	auto[0]	auto[1]	249478	1			T24	14		T1	294		T11	19
bins_for_gpio_bits[12]	auto[1]	auto[0]	249699	1			T24	14		T1	292		T11	20
bins_for_gpio_bits[12]	auto[1]	auto[1]	5547177	1			T24	128		T1	7693		T11	74
bins_for_gpio_bits[13]	auto[0]	auto[0]	8124654	1			T24	515		T25	21		T1	3108
bins_for_gpio_bits[13]	auto[0]	auto[1]	249581	1			T24	17		T1	290		T11	17
bins_for_gpio_bits[13]	auto[1]	auto[0]	249787	1			T24	17		T1	288		T11	17
bins_for_gpio_bits[13]	auto[1]	auto[1]	5545166	1			T24	124		T1	7718		T11	98
bins_for_gpio_bits[14]	auto[0]	auto[0]	8131736	1			T24	547		T25	21		T1	2873
bins_for_gpio_bits[14]	auto[0]	auto[1]	250161	1			T24	11		T1	270		T11	22
bins_for_gpio_bits[14]	auto[1]	auto[0]	250352	1			T24	11		T1	270		T11	22
bins_for_gpio_bits[14]	auto[1]	auto[1]	5536939	1			T24	104		T1	7991		T11	78
bins_for_gpio_bits[15]	auto[0]	auto[0]	8120614	1			T24	517		T25	21		T1	2854
bins_for_gpio_bits[15]	auto[0]	auto[1]	249668	1			T24	14		T1	277		T11	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	249861	1			T24	14		T1	276		T11	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	5549045	1			T24	128		T1	7997		T11	90
bins_for_gpio_bits[16]	auto[0]	auto[0]	8129036	1			T24	524		T25	21		T1	2881
bins_for_gpio_bits[16]	auto[0]	auto[1]	249932	1			T24	13		T1	295		T11	20
bins_for_gpio_bits[16]	auto[1]	auto[0]	250146	1			T24	13		T1	294		T11	21
bins_for_gpio_bits[16]	auto[1]	auto[1]	5540074	1			T24	123		T1	7934		T11	73
bins_for_gpio_bits[17]	auto[0]	auto[0]	8134929	1			T24	555		T25	21		T1	2922
bins_for_gpio_bits[17]	auto[0]	auto[1]	250156	1			T24	11		T1	280		T11	20
bins_for_gpio_bits[17]	auto[1]	auto[0]	250388	1			T24	11		T1	279		T11	20
bins_for_gpio_bits[17]	auto[1]	auto[1]	5533715	1			T24	96		T1	7923		T11	69
bins_for_gpio_bits[18]	auto[0]	auto[0]	8122343	1			T24	529		T25	21		T1	2944
bins_for_gpio_bits[18]	auto[0]	auto[1]	250137	1			T24	14		T1	278		T11	21
bins_for_gpio_bits[18]	auto[1]	auto[0]	250382	1			T24	14		T1	277		T11	22
bins_for_gpio_bits[18]	auto[1]	auto[1]	5546326	1			T24	116		T1	7905		T11	94
bins_for_gpio_bits[19]	auto[0]	auto[0]	8131672	1			T24	525		T25	21		T1	3038
bins_for_gpio_bits[19]	auto[0]	auto[1]	250765	1			T24	18		T1	286		T11	21
bins_for_gpio_bits[19]	auto[1]	auto[0]	250951	1			T24	18		T1	284		T11	21
bins_for_gpio_bits[19]	auto[1]	auto[1]	5535800	1			T24	112		T1	7796		T11	74
bins_for_gpio_bits[20]	auto[0]	auto[0]	8136446	1			T24	522		T25	21		T1	2876
bins_for_gpio_bits[20]	auto[0]	auto[1]	249410	1			T24	17		T1	254		T11	23
bins_for_gpio_bits[20]	auto[1]	auto[0]	249597	1			T24	17		T1	253		T11	24
bins_for_gpio_bits[20]	auto[1]	auto[1]	5533735	1			T24	117		T1	8021		T11	93
bins_for_gpio_bits[21]	auto[0]	auto[0]	8124819	1			T24	534		T25	21		T1	2996
bins_for_gpio_bits[21]	auto[0]	auto[1]	249584	1			T24	16		T1	287		T11	20
bins_for_gpio_bits[21]	auto[1]	auto[0]	249803	1			T24	16		T1	286		T11	21
bins_for_gpio_bits[21]	auto[1]	auto[1]	5544982	1			T24	107		T1	7835		T11	86
bins_for_gpio_bits[22]	auto[0]	auto[0]	8126367	1			T24	561		T25	21		T1	2956
bins_for_gpio_bits[22]	auto[0]	auto[1]	250849	1			T24	9		T1	272		T11	19
bins_for_gpio_bits[22]	auto[1]	auto[0]	251107	1			T24	9		T1	271		T11	20
bins_for_gpio_bits[22]	auto[1]	auto[1]	5540865	1			T24	94		T1	7905		T11	99
bins_for_gpio_bits[23]	auto[0]	auto[0]	8128611	1			T24	531		T25	21		T1	2974
bins_for_gpio_bits[23]	auto[0]	auto[1]	249726	1			T24	15		T1	288		T11	25
bins_for_gpio_bits[23]	auto[1]	auto[0]	249910	1			T24	15		T1	287		T11	25
bins_for_gpio_bits[23]	auto[1]	auto[1]	5540941	1			T24	112		T1	7855		T11	104
bins_for_gpio_bits[24]	auto[0]	auto[0]	8136233	1			T24	543		T25	21		T1	2951
bins_for_gpio_bits[24]	auto[0]	auto[1]	249773	1			T24	13		T1	285		T11	20
bins_for_gpio_bits[24]	auto[1]	auto[0]	249922	1			T24	13		T1	285		T11	20
bins_for_gpio_bits[24]	auto[1]	auto[1]	5533260	1			T24	104		T1	7883		T11	79
bins_for_gpio_bits[25]	auto[0]	auto[0]	8130001	1			T24	522		T25	21		T1	3078
bins_for_gpio_bits[25]	auto[0]	auto[1]	250252	1			T24	13		T1	281		T11	25
bins_for_gpio_bits[25]	auto[1]	auto[0]	250491	1			T24	13		T1	281		T11	25
bins_for_gpio_bits[25]	auto[1]	auto[1]	5538444	1			T24	125		T1	7764		T11	92
bins_for_gpio_bits[26]	auto[0]	auto[0]	8139303	1			T24	559		T25	21		T1	3033
bins_for_gpio_bits[26]	auto[0]	auto[1]	249518	1			T24	15		T1	273		T11	20
bins_for_gpio_bits[26]	auto[1]	auto[0]	249748	1			T24	15		T1	273		T11	20
bins_for_gpio_bits[26]	auto[1]	auto[1]	5530619	1			T24	84		T1	7825		T11	89
bins_for_gpio_bits[27]	auto[0]	auto[0]	8133310	1			T24	515		T25	21		T1	2862
bins_for_gpio_bits[27]	auto[0]	auto[1]	249293	1			T24	14		T1	267		T11	22
bins_for_gpio_bits[27]	auto[1]	auto[0]	249488	1			T24	14		T1	265		T11	23
bins_for_gpio_bits[27]	auto[1]	auto[1]	5537097	1			T24	130		T1	8010		T11	126
bins_for_gpio_bits[28]	auto[0]	auto[0]	8119128	1			T24	512		T25	21		T1	3002
bins_for_gpio_bits[28]	auto[0]	auto[1]	250355	1			T24	16		T1	286		T11	21
bins_for_gpio_bits[28]	auto[1]	auto[0]	250616	1			T24	16		T1	286		T11	22
bins_for_gpio_bits[28]	auto[1]	auto[1]	5549089	1			T24	129		T1	7830		T11	98
bins_for_gpio_bits[29]	auto[0]	auto[0]	8135242	1			T24	565		T25	21		T1	2932
bins_for_gpio_bits[29]	auto[0]	auto[1]	250044	1			T24	7		T1	276		T11	24
bins_for_gpio_bits[29]	auto[1]	auto[0]	250259	1			T24	7		T1	276		T11	25
bins_for_gpio_bits[29]	auto[1]	auto[1]	5533643	1			T24	94		T1	7920		T11	95
bins_for_gpio_bits[30]	auto[0]	auto[0]	8124463	1			T24	511		T25	21		T1	3055
bins_for_gpio_bits[30]	auto[0]	auto[1]	250115	1			T24	17		T1	293		T11	26
bins_for_gpio_bits[30]	auto[1]	auto[0]	250370	1			T24	17		T1	292		T11	26
bins_for_gpio_bits[30]	auto[1]	auto[1]	5544240	1			T24	128		T1	7764		T11	82
bins_for_gpio_bits[31]	auto[0]	auto[0]	8126033	1			T24	550		T25	21		T1	3175
bins_for_gpio_bits[31]	auto[0]	auto[1]	249853	1			T24	12		T1	316		T11	24
bins_for_gpio_bits[31]	auto[1]	auto[0]	250065	1			T24	12		T1	316		T11	25
bins_for_gpio_bits[31]	auto[1]	auto[1]	5543237	1			T24	99		T1	7597		T11	87